From 43bc35b26ee09c7439088b41fdc5a1004c0c1569 Mon Sep 17 00:00:00 2001
From: bunnie <bunnie@kosagi.com>
Date: Thu, 30 Jan 2025 04:17:57 -0800
Subject: [PATCH] modify i2c reset condition to have wait states

this is necessary because the cpu can easily outrun the udma
block as the reset is processing, causing the re-initialization
to fail.
---
 libs/cramium-hal/src/udma/i2c.rs | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/libs/cramium-hal/src/udma/i2c.rs b/libs/cramium-hal/src/udma/i2c.rs
index 9c2ab9818..40169d71d 100644
--- a/libs/cramium-hal/src/udma/i2c.rs
+++ b/libs/cramium-hal/src/udma/i2c.rs
@@ -303,10 +303,6 @@ impl<'a> I2c<'a> {
     }
 
     pub fn reset(&mut self) {
-        // reset the block
-        self.udma_reset(Bank::Custom);
-        self.udma_reset(Bank::Tx);
-        self.udma_reset(Bank::Rx);
         // reset the block, if MPW. If NTO, this needs to be handled by the upper level code with a
         // reset to udma_global
         #[cfg(feature = "mpw")]
@@ -323,6 +319,19 @@ impl<'a> I2c<'a> {
                 I2cChannel::Channel3 => PeriphId::I2c3,
             });
         }
+        for _i in 0..20 {
+            // dummy read
+            let _ = self.csr.rf(utra::udma_i2c_0::REG_STATUS_R_BUSY);
+        }
+        // reset the block
+        self.udma_reset(Bank::Custom);
+        self.udma_reset(Bank::Tx);
+        self.udma_reset(Bank::Rx);
+
+        for _i in 0..20 {
+            // dummy read
+            let _ = self.csr.rf(utra::udma_i2c_0::REG_STATUS_R_BUSY);
+        }
 
         self.send_cmd_list(&[I2cCmd::Config(self.divider)]);
         self.pending.take();