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Yury Norov
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bitfield: add FIELD_GET_SIGNED()
The bitfields are designed in assumption that fields contain unsigned integer values, thus extracting the values from the field implies zero-extending. Some drivers need to sign-extend their fields, and currently do it like: dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11); dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11); It's error-prone because it relies on user to provide the correct index of the most significant bit and proper 32 vs 64 function flavor. Thus, introduce a FIELD_GET_SIGNED(). With the new API, the above snippet turns into the more convenient: dc_re += FIELD_GET_SIGNED(0xfff000, tmp); dc_im += FIELD_GET_SIGNED(0xfff, tmp); It compiles (on x86_64) into just a couple instructions: shl and sar. When the mask includes MSB, the '<< __builtin_clzll(mask)' part becomes a NOP, and the compiler only emits a single sar: long long foo(long long reg) { 10: f3 0f 1e fa endbr64 return FIELD_GET_SIGNED(GENMASK_ULL(63, 60), reg); 14: 48 89 f8 mov %rdi,%rax 17: 48 c1 f8 3c sar $0x3c,%rax } 32-bit code generation is equally well. On arm32: long long foo(long long reg) { return FIELD_GET_SIGNED(0x00f00000ULL, reg); } generates: foo(long long): lsls r1, r0, #8 asrs r0, r1, #28 asrs r1, r1, #31 bx lr Signed-off-by: Yury Norov <ynorov@nvidia.com>
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include/linux/bitfield.h

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@@ -178,6 +178,22 @@
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__FIELD_GET(_mask, _reg, "FIELD_GET: "); \
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})
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/**
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* FIELD_GET_SIGNED() - extract a signed bitfield element
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* @mask: shifted mask defining the field's length and position
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* @reg: value of entire bitfield
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*
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* Returns the sign-extended field specified by @_mask from the
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* bitfield passed in as @reg by masking and shifting it down.
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*/
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#define FIELD_GET_SIGNED(mask, reg) \
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({ \
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__BF_FIELD_CHECK(mask, reg, 0U, "FIELD_GET_SIGNED: "); \
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((__signed_scalar_typeof(mask)) \
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(((long long)(reg) << __builtin_clzll(mask)) >> \
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(__builtin_clzll(mask) + __builtin_ctzll(mask)))); \
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})
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/**
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* FIELD_MODIFY() - modify a bitfield element
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* @_mask: shifted mask defining the field's length and position

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