From 16837fdc35eb0f4bc87583c5d334e0021a46ef2e Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Fri, 8 Nov 2024 11:42:24 -0800
Subject: [PATCH] Revert latch fix that causes Verilator failures

---
 src/riscv_core/veer_el2/rtl/lib/beh_lib.sv | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
index 9912fc815..083989933 100644
--- a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
+++ b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
@@ -760,10 +760,16 @@ module `TEC_RV_ICG
 
    assign      enable = EN | SE;
 
+`ifdef VERILATOR
+   always @(negedge CK) begin
+      en_ff <= enable;
+   end
+`else
    always @(CK, enable) begin
       if(!CK)
         en_ff = enable;
    end
+`endif
    assign Q = CK & en_ff;
 
 endmodule