improve description

Author: cirosantilli

README.md

@@ -2,14 +2,16 @@
 
 [![Build Status](https://travis-ci.org/cirosantilli/x86-assembly-cheat.svg?branch=master)](https://travis-ci.org/cirosantilli/x86-assembly-cheat)
 
-x86 userland minimal examples. Hundreds of runnable asserts. Linux focus for now, but highly OS portable. Containers (ELF), linking, calling conventions. System land at: [x86 Bare Metal Examples](https://github.com/cirosantilli/x86-bare-metal-examples)
+x86 userland minimal examples. Hundreds of runnable asserts. Containers (ELF), linking, calling conventions. System land cheat at: <https://github.com/cirosantilli/x86-bare-metal-examples>
 
 1.  [Getting started](getting-started.md)
 1.  Introduction
     1.  [How to learn](how-to-learn.md)
     1.  [Instruction sets](instruction-sets.md)
         1.  [Other architectures](other-architectures.md)
+            1. [ARM](https://github.com/cirosantilli/arm-assembly-cheat)
             1. [RISC-V](risc-v.md)
+            1. [Microcontrollers](microcontrollers.md)
         1.  [RISC vs CISC](risc-vs-cisc.md)
             1.  [Microcode](microcode.md)
         1.  [System vs application programming](system-vs-application-programming.md)
@@ -21,10 +23,11 @@ x86 userland minimal examples. Hundreds of runnable asserts. Linux focus for now
     1.  [Intel processor history](intel-processor-history.md)
     1.  [Intel vs AT&T syntax](intel-vs-atet-syntax.md)
         1.  [intel2gas](intel2gas.md)
-    1.  [CPU Optimizations](cpu-optimizations.md)
-    1.  [CPU bugs](cpu-bugs.md)
     1.  [Implementations](implementations.md)
     1.  [Extensions](extensions.md)
+    1.  [CPU Hardware design](cpu-hardware-design.md)
+        1.  [CPU Optimizations](cpu-optimizations.md)
+        1.  [CPU bugs](cpu-bugs.md)
 1.  [IA-32](ia-32.md)
     1.  [main.asm](main.asm)
     1.  [hello_world.asm](hello_world.asm)

bibliography.md

@@ -88,5 +88,11 @@
 
     Binutils cannot be used as a library to disassemble? Sad.
 
+## Cool projects
+
+Useless but cool and educational:
+
+-   <https://github.com/flouthoc/calc.asm>
+
 [Itanium C++ ABI]: http://mentorembedded.github.io/cxx-abi/abi.html
 [System V ABI AMD64]: http://www.x86-64.org/documentation_folder/abi-0.99.pdf

cpu-hardware-design.md

@@ -0,0 +1,5 @@
+# CPU hardware design
+
+- <http://electronics.stackexchange.com/questions/122050/what-limits-cpu-speed>
+- <http://cs.stackexchange.com/questions/22589/why-does-a-processor-have-32-registers>
+- <http://electronics.stackexchange.com/questions/158053/what-components-or-circuitry-exist-that-can-provide-extremely-high-speed-accura>

gas/altmacro.S

@@ -66,7 +66,7 @@ ENTRY
 
     # Percent
 
-        Appears to work only on argumetns passed or their default values.
+        Appears to work only on arguments passed or their default values.
     */
 
             .macro PERCENT x

implementations.md

@@ -31,3 +31,7 @@ Intel and AMD have cross-licensing agreements:
 - http://www.anandtech.com/show/2873
 - http://www.eetimes.com/document.asp?doc_id=1129690
 - Interview with W. Jerry Sanders http://silicongenesis.stanford.edu/transcripts/sanders.htm
+
+## Open implementations
+
+<https://github.com/marmolejo/zet> TODO legal?

lib/driver.c

@@ -10,5 +10,5 @@
 int PRE_CDECL asm_main(void) POST_CDECL;
 
 int main(void) {
-  return asm_main();
+    return asm_main();
 }

microcontrollers.md

@@ -0,0 +1,21 @@
+# Microcontrollers
+
+## Vs microprocessor
+
+There is a spectrum, so difficult to say.
+
+Microcontrollers are small SoCs... memory is inside chip.
+
+They have IO dedicated pins.
+
+TODO: response time is smaller.
+
+TODO: most have predictable instruction times, and are better for hard real time.
+
+TODO: the latency between signal and result is smaller
+
+TODO: often programmed to run on bare metal, while microprocessors are more often programmed to run on top of an OS (e.g. Linux). But there are also OSes for microcontrollers, mostly real time ones: <http://www.embedded.com/design/operating-systems/4425751/Comparing-microcontroller-real-time-operating-systems>, e.g. QNX. Those OSes can even implement the POSIX C API.
+
+Microcontrollers can have either internal or external clock sources: <http://electronics.stackexchange.com/questions/15455/internal-or-external-oscillator> TODO CPUs?
+
+<http://electronics.stackexchange.com/questions/1092/whats-the-difference-between-a-microcontroller-and-a-microprocessor>

other-architectures.md

@@ -4,28 +4,6 @@ This tutorial focuses only on the x86 architecture families.
 
 Here are some other popular architectures which you should have in mind as well:
 
-## ARM
-
-<https://en.wikipedia.org/wiki/ARM_architecture>
-
-Great majority of mobile phones.
-
-Low power consumption.
-
-RISC.
-
-armv7 is a version of arm that added floating point operations: <http://stackoverflow.com/questions/7080525/why-use-armeabi-v7a-code-over-armeabi-code>
-
-### Open implementations
-
-<https://en.wikipedia.org/wiki/Amber_%28processor_core%29> TODO how does it compare in performance / cost?
-
-ARM has already sued people in the past for implementing ARM ISA: http://www.eetimes.com/author.asp?section_id=36&doc_id=1287452 so not open.
-
-<http://semiengineering.com/an-alternative-to-x86-arm-architectures/>:
-
-> Asanovic joked that the shortest unit of time is not the moment between a traffic light turning green in New York City and the cab driver behind the first vehicle blowing the horn; it’s someone announcing that they have created an open-source, ARM-compatible core and receiving a “cease and desist” letter from a law firm representing ARM.
-
 ## PowerPC
 
 <https://en.wikipedia.org/wiki/PowerPC>
@@ -48,11 +26,14 @@ Officially supported on Android.
 
 <http://www.androidauthority.com/nintendo-64-android-l-microcontrollers-story-mips-538596/>
 
+Lextra story: <http://probell.com/lexra/> It is not possible to patent an entire ISA as there is too much prior art, but companies patent instead specific novel instructions, and the compatibility break kills off reimplementors.
+
 ### Open implementations
 
-Seems closed?
+Seems closed? TODO legal?
 
-Open implementation: <https://brej.org/yellow_star/> TODO legal?
+- <https://brej.org/yellow_star/>
+- <https://github.com/jmahler/mips-cpu>
 
 ## SPARC
 

risc-v.md

@@ -4,12 +4,6 @@
 
 Most promising open ;
 
-They have a full working software toolchain:
-
-- <https://github.com/riscv/riscv-linux> GCC
-- <https://github.com/riscv/riscv-tools>
-- <http://riscv.org/software-tools/riscv-qemu/>
-
 Created in 2010. BSD license.
 
 Userspace fixed in 2014, but kernel land not yet as of 2016. So the Linux port may have to change.
@@ -22,27 +16,21 @@ TODO: any real hardware produced besides FPGA?
 
 Debian port: <https://wiki.debian.org/RISC-V>
 
-## Rocket
-
-<https://github.com/ucb-bar/rocket-chip>
-
-Written in Chisel, which is Scala based: <https://github.com/ucb-bar/chisel>
-
-By Berkley people.
-
-2015 presentation by Yunsup Lee <https://www.youtube.com/watch?v=Ir3h3qWcNlg>
+## Software toolchain
 
-A single source coce + some input parameters can generate:
+- <https://github.com/riscv/riscv-linux> GCC
+- <https://github.com/riscv/riscv-tools>
+- <http://riscv.org/software-tools/riscv-qemu/>
 
-- C++ simulator code
-- FPGA Verilog
-- ASIC Verilog
+Emulators: Spike is dedicated for this project:
 
-TODO: any plans for silicon production?
+- <http://stackoverflow.com/questions/32881106/riscv-qemu-scall-versus-spike-ecall>
+- <http://52.32.189.224/angel-simulator/> JavaScript!
 
-http://www.lowrisc.org/docs/untether-v0.2/
+There are two types of simulation you can do:
 
-2016 thesis on it: <http://www.eecs.berkeley.edu/~waterman/papers/phd-thesis.pdf>
+- functional: assembly comes in and is emulated. Faster. Does not use the hardware implementation at all, and therefore does not test it: what is does test are software tools like compiler and kernel ports. May or not be cycle accurate as well, with performance hit if yes.
+- RTL: the entire hardware is emulated. Slower, but more precise. You need the underlying hardware implementation. Always cycle accurate.
 
 ## lowRISC
 
@@ -53,6 +41,8 @@ RISC-V ASIC and FPGA implementation.
 
 RISC-V is only the API.
 
+Uses Rocket, but one major innovation is that it includes IO devices, while Rocket needed an ARM IP for that: <https://youtu.be/9BU5yNeyI5k?t=91>
+
 Mass production planned for 2017: <http://www.lowrisc.org/about/>
 
 By Cambridge people.
@@ -63,9 +53,37 @@ Google summer of code projects in 2016: http://www.lowrisc.org/blog/2016/03/appl
 
 Initial implementation reuse part of FPGA hardware: http://www.lowrisc.org/docs/untether-v0.2/ , they are trying to open things up further.
 
+Uses Verilator for simulation.
+
+## Rocket
+
+Tooling to generate Chips.
+
+<https://github.com/ucb-bar/rocket-chip>
+
+Uses Chisel, which is Scala based: <https://github.com/ucb-bar/chisel>
+
+Used by lowRISC.
+
+By Berkley people.
+
+2015 presentation by Yunsup Lee <https://www.youtube.com/watch?v=Ir3h3qWcNlg>
+
+A single source code + some input parameters can generate:
+
+- C++ simulator code
+- FPGA Verilog
+- ASIC Verilog
+
+TODO: any plans for silicon production?
+
+http://www.lowrisc.org/docs/untether-v0.2/
+
+2016 thesis on it: <http://www.eecs.berkeley.edu/~waterman/papers/phd-thesis.pdf>
+
 ## SiFive
 
-http://sifive.com/
+<http://sifive.com/>
 
 Startup around RISC-V tech by Berkley people, contributors to <https://github.com/riscv/riscv-tools>
 
@@ -83,7 +101,7 @@ The project owner works at Rackspace, who is partnering with Google for open sou
 
 ## OpenRISC
 
-https://en.wikipedia.org/wiki/OpenRISC
+<https://en.wikipedia.org/wiki/OpenRISC>
 
 LGPL / GPL. TODO: history?
 
@@ -97,6 +115,8 @@ ETH Zurich.
 
 Previously closed source custom ISA I think, then opened and front-end hacked for RISC-V.
 
+Uses ModelSim...
+
 ## News
 
 2016 indiegogo https://www.indiegogo.com/projects/risc-v-microprocessor/x/6766065#/
@@ -108,3 +128,17 @@ Previously closed source custom ISA I think, then opened and front-end hacked fo
 <http://riscv.org/2016/04/risc-v-offers-simple-modular-isa/>
 
 <https://www.quora.com/Would-RISC-V-become-the-dominant-CPU-architecture-in-the-next-5-years-given-that-Google-Oracle-and-HP-are-strongly-rallying-behind-RISC-V>
+
+## Tethered vs untethered
+
+<https://youtu.be/XSyH9T-Cj4w?t=64> tethered cannot do IO on itself: <https://www.youtube.com/watch?v=XSyH9T-Cj4w>
+
+Rocket it tethered, lowRISC untethered.
+
+## Hardware implementations
+
+- <https://github.com/lowRISC/lowrisc-chip>
+- <https://github.com/ucb-bar/rocket-chip>
+- <https://github.com/ucb-bar/riscv-boom>
+- <https://github.com/cliffordwolf/picorv32>
+- Pulpino