Merge changes from topic "stm32mp15-dt-updates" into integration

* changes:
  refactor(stm32mp15-fdts): remove timers15 node
  refactor(stm32mp15-fdts): remove unused secure-status properties
  refactor(stm32mp15-fdts): remove RCC secure-status

Author: madhukar-Arm

fdts/stm32mp157a-avenger96.dts

@@ -163,7 +163,6 @@
 &iwdg2 {
 	timeout-sec = <32>;
 	status = "okay";
-	secure-status = "okay";
 };
 
 &pwr_regulators {
@@ -172,7 +171,6 @@
 };
 
 &rcc {
-	secure-status = "disabled";
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P

fdts/stm32mp157c-ed1.dts

@@ -201,7 +201,6 @@
 };
 
 &rcc {
-	secure-status = "disabled";
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P

fdts/stm32mp157c-odyssey-som.dtsi

@@ -203,7 +203,6 @@
 };
 
 &rcc {
-	secure-status = "disabled";
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P

fdts/stm32mp15xx-dhcom-som.dtsi

@@ -160,7 +160,6 @@
 &iwdg2 {
 	timeout-sec = <32>;
 	status = "okay";
-	secure-status = "okay";
 };
 
 &pwr_regulators {
@@ -187,7 +186,6 @@
 };
 
 &rcc {
-	secure-status = "disabled";
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P

fdts/stm32mp15xx-dhcor-som.dtsi

@@ -155,7 +155,6 @@
 &iwdg2 {
 	timeout-sec = <32>;
 	status = "okay";
-	secure-status = "okay";
 };
 
 &pwr_regulators {
@@ -182,7 +181,6 @@
 };
 
 &rcc {
-	secure-status = "disabled";
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P

fdts/stm32mp15xx-dkx.dtsi

@@ -180,7 +180,6 @@
 &iwdg2 {
 	timeout-sec = <32>;
 	status = "okay";
-	secure-status = "okay";
 };
 
 &pwr_regulators {
@@ -189,7 +188,6 @@
 };
 
 &rcc {
-	secure-status = "disabled";
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P
@@ -304,10 +302,6 @@
 	status = "okay";
 };
 
-&timers15 {
-	secure-status = "okay";
-};
-
 &uart4 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart4_pins_a>;

fdts/stm32mp15xx-osd32.dtsi

@@ -181,7 +181,6 @@
 
 /* CLOCK init */
 &rcc {
-	secure-status = "disabled";
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P