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- // Copyright (c) 2021 - 2023 Intel Corporation
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+ // Copyright (c) 2021 - 2024 Intel Corporation
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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/*
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Image Layout
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+----------------------------------------+ <- 0x0
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- | CONFIG | (0x40000) 256 KB
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- +----------------------------------------+ <- 0x40000
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- | MAILBOX | (0x1000) 4 KB
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- +----------------------------------------+ <- 0x41000
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- | TEMP_STACK | (0x20000) 128 KB
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- +----------------------------------------+ <- 0x61000
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- | TEMP_HEAP | (0x20000) 128 KB
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- +----------------------------------------+ <- 0x81000
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- | FREE | (0x1000) 4 KB
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- +----------------------------------------+ <- 0x82000
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| PAYLOAD | (0xC2D000) 12.18 MB
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+ +----------------------------------------+ <- 0xC2D000
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+ | CONFIG | (0x40000) 256 kB
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+ +----------------------------------------+ <- 0xC6D000
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+ | MAILBOX | (0x1000) 4 kB
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+ +----------------------------------------+ <- 0xC6E000
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+ | TEMP_STACK | (0x20000) 128 kB
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+ +----------------------------------------+ <- 0xC8E000
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+ | TEMP_HEAP | (0x20000) 128 kB
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+ +----------------------------------------+ <- 0xCAE000
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+ | FREE | (0x1000) 4 kB
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+----------------------------------------+ <- 0xCAF000
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- | METADATA | (0x1000) 4 KB
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+ | METADATA | (0x1000) 4 kB
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+----------------------------------------+ <- 0xCB0000
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| IPL | (0x348000) 3.28 MB
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+----------------------------------------+ <- 0xFF8000
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- | RESET_VECTOR | (0x8000) 32 KB
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+ | RESET_VECTOR | (0x8000) 32 kB
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+----------------------------------------+ <- 0x1000000
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Image size: 0x1000000 (16 MB)
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*/
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// Image Layout Configuration
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- pub const TD_SHIM_CONFIG_OFFSET : u32 = 0x0 ;
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- pub const TD_SHIM_CONFIG_SIZE : u32 = 0x40000 ; // 256 KB
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+ pub const TD_SHIM_PAYLOAD_OFFSET : u32 = 0x0 ;
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+ pub const TD_SHIM_PAYLOAD_SIZE : u32 = 0xC2D000 ; // 12.18 MB
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- pub const TD_SHIM_MAILBOX_OFFSET : u32 = 0x40000 ;
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- pub const TD_SHIM_MAILBOX_SIZE : u32 = 0x1000 ; // 4 KB
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+ pub const TD_SHIM_CONFIG_OFFSET : u32 = 0xC2D000 ;
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+ pub const TD_SHIM_CONFIG_SIZE : u32 = 0x40000 ; // 256 kB
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- pub const TD_SHIM_TEMP_STACK_OFFSET : u32 = 0x41000 ;
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- pub const TD_SHIM_TEMP_STACK_SIZE : u32 = 0x20000 ; // 128 KB
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+ pub const TD_SHIM_MAILBOX_OFFSET : u32 = 0xC6D000 ;
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+ pub const TD_SHIM_MAILBOX_SIZE : u32 = 0x1000 ; // 4 kB
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- pub const TD_SHIM_TEMP_HEAP_OFFSET : u32 = 0x61000 ;
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- pub const TD_SHIM_TEMP_HEAP_SIZE : u32 = 0x20000 ; // 128 KB
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+ pub const TD_SHIM_TEMP_STACK_OFFSET : u32 = 0xC6E000 ;
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+ pub const TD_SHIM_TEMP_STACK_SIZE : u32 = 0x20000 ; // 128 kB
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- pub const TD_SHIM_FREE_OFFSET : u32 = 0x81000 ;
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- pub const TD_SHIM_FREE_SIZE : u32 = 0x1000 ; // 4 KB
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+ pub const TD_SHIM_TEMP_HEAP_OFFSET : u32 = 0xC8E000 ;
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+ pub const TD_SHIM_TEMP_HEAP_SIZE : u32 = 0x20000 ; // 128 kB
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- pub const TD_SHIM_PAYLOAD_OFFSET : u32 = 0x82000 ;
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- pub const TD_SHIM_PAYLOAD_SIZE : u32 = 0xC2D000 ; // 12.18 MB
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+ pub const TD_SHIM_FREE_OFFSET : u32 = 0xCAE000 ;
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+ pub const TD_SHIM_FREE_SIZE : u32 = 0x1000 ; // 4 kB
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pub const TD_SHIM_METADATA_OFFSET : u32 = 0xCAF000 ;
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- pub const TD_SHIM_METADATA_SIZE : u32 = 0x1000 ; // 4 KB
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+ pub const TD_SHIM_METADATA_SIZE : u32 = 0x1000 ; // 4 kB
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pub const TD_SHIM_IPL_OFFSET : u32 = 0xCB0000 ;
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pub const TD_SHIM_IPL_SIZE : u32 = 0x348000 ; // 3.28 MB
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pub const TD_SHIM_RESET_VECTOR_OFFSET : u32 = 0xFF8000 ;
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- pub const TD_SHIM_RESET_VECTOR_SIZE : u32 = 0x8000 ; // 32 KB
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+ pub const TD_SHIM_RESET_VECTOR_SIZE : u32 = 0x8000 ; // 32 kB
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// Offset when Loading into Memory
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pub const TD_SHIM_FIRMWARE_BASE : u32 = 0xFF000000 ;
@@ -67,12 +67,12 @@ pub const TD_SHIM_SEC_CORE_INFO_OFFSET: u32 = 0xFFFFAC;
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pub const TD_SHIM_SEC_CORE_INFO_BASE : u32 = 0xFFFFFFAC ;
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// Base Address after Loaded into Memory
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- pub const TD_SHIM_CONFIG_BASE : u32 = 0xFF000000 ;
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- pub const TD_SHIM_MAILBOX_BASE : u32 = 0xFF040000 ;
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- pub const TD_SHIM_TEMP_STACK_BASE : u32 = 0xFF041000 ;
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- pub const TD_SHIM_TEMP_HEAP_BASE : u32 = 0xFF061000 ;
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- pub const TD_SHIM_FREE_BASE : u32 = 0xFF081000 ;
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- pub const TD_SHIM_PAYLOAD_BASE : u32 = 0xFF082000 ;
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+ pub const TD_SHIM_PAYLOAD_BASE : u32 = 0xFF000000 ;
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+ pub const TD_SHIM_CONFIG_BASE : u32 = 0xFFC2D000 ;
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+ pub const TD_SHIM_MAILBOX_BASE : u32 = 0xFFC6D000 ;
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+ pub const TD_SHIM_TEMP_STACK_BASE : u32 = 0xFFC6E000 ;
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+ pub const TD_SHIM_TEMP_HEAP_BASE : u32 = 0xFFC8E000 ;
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+ pub const TD_SHIM_FREE_BASE : u32 = 0xFFCAE000 ;
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pub const TD_SHIM_METADATA_BASE : u32 = 0xFFCAF000 ;
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pub const TD_SHIM_IPL_BASE : u32 = 0xFFCB0000 ;
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pub const TD_SHIM_RESET_VECTOR_BASE : u32 = 0xFFFF8000 ;
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