diff --git a/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml
index 8c6b4ca625ec..3b51686d0d1d 100644
--- a/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml
@@ -4,21 +4,21 @@
 $id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: UltraRisc DP1000 Pin Controller
+title: UltraRISC DP1000 Pin Controller
 maintainers:
   - Jia Wang <wangjia@ultrarisc.com>
 
 description: |
-  UltraRisc RISC-V SoC DP1000 pin controller.
+  UltraRISC RISC-V SoC DP1000 pin controller.
   <dt-bindings/pinctrl/ur-dp1000-pinctrl.h> contains the pinmux definitions.
 
 properties:
   compatible:
     const: ultrarisc,dp1000-pinctrl
-  
+
   reg:
     maxItems: 1
-  
+
   pinctrl-single,register-width:
     description:
       The width of the register used to configure the pinmux.
@@ -52,8 +52,7 @@ patternProperties:
           pinctrl-pins:
             description:
               The list of Pins and their mux settings that properties in the
-              node apply to. This should be set using the UR_DP1000_IOPAD 
-              macros.
+              node apply to. The format: `PORT  PIN  FUNCTION`.
             minItems: 1
             maxItems: 32
             items:
@@ -61,7 +60,8 @@ patternProperties:
           pinconf-pins:
             description:
               The list of Pins and their bias settings that properties in the
-              node apply to. This should be set using the UR_DP1000_BIAS macros.
+              node apply to. The format: `PORT  PIN  BIAS`.The BIAS should be
+              set using the UR_DP1000_BIAS macros.
             minItems: 1
             maxItems: 32
             items:
@@ -81,25 +81,25 @@ examples:
 
       i2c0_pins: i2c0_pins {
         pinctrl-pins = <
-          UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0)
-          UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0)
+          UR_DP1000_IOMUX_A  12  UR_FUNC0
+          UR_DP1000_IOMUX_A  13  UR_FUNC0
           >;
-          
+
         pinconf-pins = <
-          UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF)
-          UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF)
+          UR_DP1000_IOMUX_A  12  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+          UR_DP1000_IOMUX_A  13  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
           >;
       };
 
       i2c1_pins: i2c1_pins {
         pinctrl-pins = <
-          UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0)
-          UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0)
+          UR_DP1000_IOMUX_B  6  UR_FUNC0
+          UR_DP1000_IOMUX_B  7  UR_FUNC0
           >;
-          
+
         pinconf-pins = <
-          UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF)
-          UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF)
+          UR_DP1000_IOMUX_B  6  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+          UR_DP1000_IOMUX_B  7  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
           >;
       };
-    };
\ No newline at end of file
+    };
diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile
index 9eac56549340..df8efe1a3ed7 100644
--- a/arch/riscv/boot/dts/ultrarisc/Makefile
+++ b/arch/riscv/boot/dts/ultrarisc/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb
 dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb
 dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb
+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi
index e82fcf2901ab..85b013f66bbd 100644
--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi
@@ -4,143 +4,130 @@
  */
 
 #include <dt-bindings/pinctrl/ur-dp1000-pinctrl.h>
+#include "dp1000.dtsi"
+
+&pmx0 {
+	i2c0_pins: i2c0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  12  UR_FUNC0
+		UR_DP1000_IOMUX_A  13  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  12  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  13  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c1_pins: i2c1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_B  6  UR_FUNC0
+		UR_DP1000_IOMUX_B  7  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_B  6  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_B  7  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c2_pins: i2c2_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  0  UR_FUNC0
+		UR_DP1000_IOMUX_C  1  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  0  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  1  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c3_pins: i2c3_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  2  UR_FUNC0
+		UR_DP1000_IOMUX_C  3  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  2  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  3  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart0_pins: uart0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  8  UR_FUNC1
+		UR_DP1000_IOMUX_A  9  UR_FUNC1
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  8  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  9  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart1_pins: uart1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_B  4  UR_FUNC0
+		UR_DP1000_IOMUX_B  5  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_B  4  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_B  5  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart2_pins: uart2_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  4  UR_FUNC0
+		UR_DP1000_IOMUX_C  5  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  4  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  5  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	spi0_pins: spi0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_D  0  UR_FUNC1
+		UR_DP1000_IOMUX_D  1  UR_FUNC1
+		UR_DP1000_IOMUX_D  2  UR_FUNC1
+		UR_DP1000_IOMUX_D  3  UR_FUNC1
+		UR_DP1000_IOMUX_D  4  UR_FUNC1
+		UR_DP1000_IOMUX_D  5  UR_FUNC1
+		UR_DP1000_IOMUX_D  6  UR_FUNC1
+		UR_DP1000_IOMUX_D  7  UR_FUNC1
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_D  0  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  1  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  2  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  3  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  4  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  5  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  6  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  7  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
 
-/ {
-
-	soc {
-		pmx0: pinmux@11081000 {
-			compatible = "ultrarisc,dp1000-pinctrl";
-			reg = <0x0 0x11081000  0x0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#pinctrl-cells = <2>;
-			pinctrl-single,register-width = <32>;
-			pinctrl-single,function-mask = <0x3ff>;
-			pinctrl-use-default;
-
-			i2c0_pins: i2c0_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			i2c1_pins: i2c1_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			i2c2_pins: i2c2_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			i2c3_pins: i2c3_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			uart0_pins: uart0_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			uart1_pins: uart1_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			uart2_pins: uart2_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			spi0_pins: spi0_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			spi1_pins: spi1_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-		};
+	spi1_pins: spi1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  0  UR_FUNC0
+		UR_DP1000_IOMUX_A  1  UR_FUNC0
+		UR_DP1000_IOMUX_A  2  UR_FUNC0
+		UR_DP1000_IOMUX_A  3  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  0  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  1  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  2  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  3  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
 	};
 };
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts
index 34622a33e63b..46fe457b5f52 100644
--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts
@@ -3,10 +3,16 @@
  * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd.
  */
 
-#include "dp1000.dts"
 #include "dp1000-evb-pinctrl.dtsi"
 #include <dt-bindings/iio/temperature/thermocouple.h>
 
+/ {
+	chosen {
+		bootargs = "earlycon=sbi console=ttyS1,115200";
+		stdout-path = &uart1;
+	};
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi
index e82fcf2901ab..85b013f66bbd 100644
--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi
@@ -4,143 +4,130 @@
  */
 
 #include <dt-bindings/pinctrl/ur-dp1000-pinctrl.h>
+#include "dp1000.dtsi"
+
+&pmx0 {
+	i2c0_pins: i2c0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  12  UR_FUNC0
+		UR_DP1000_IOMUX_A  13  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  12  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  13  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c1_pins: i2c1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_B  6  UR_FUNC0
+		UR_DP1000_IOMUX_B  7  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_B  6  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_B  7  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c2_pins: i2c2_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  0  UR_FUNC0
+		UR_DP1000_IOMUX_C  1  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  0  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  1  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c3_pins: i2c3_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  2  UR_FUNC0
+		UR_DP1000_IOMUX_C  3  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  2  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  3  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart0_pins: uart0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  8  UR_FUNC1
+		UR_DP1000_IOMUX_A  9  UR_FUNC1
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  8  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  9  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart1_pins: uart1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_B  4  UR_FUNC0
+		UR_DP1000_IOMUX_B  5  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_B  4  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_B  5  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart2_pins: uart2_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  4  UR_FUNC0
+		UR_DP1000_IOMUX_C  5  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  4  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  5  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	spi0_pins: spi0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_D  0  UR_FUNC1
+		UR_DP1000_IOMUX_D  1  UR_FUNC1
+		UR_DP1000_IOMUX_D  2  UR_FUNC1
+		UR_DP1000_IOMUX_D  3  UR_FUNC1
+		UR_DP1000_IOMUX_D  4  UR_FUNC1
+		UR_DP1000_IOMUX_D  5  UR_FUNC1
+		UR_DP1000_IOMUX_D  6  UR_FUNC1
+		UR_DP1000_IOMUX_D  7  UR_FUNC1
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_D  0  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  1  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  2  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  3  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  4  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  5  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  6  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  7  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
 
-/ {
-
-	soc {
-		pmx0: pinmux@11081000 {
-			compatible = "ultrarisc,dp1000-pinctrl";
-			reg = <0x0 0x11081000  0x0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#pinctrl-cells = <2>;
-			pinctrl-single,register-width = <32>;
-			pinctrl-single,function-mask = <0x3ff>;
-			pinctrl-use-default;
-
-			i2c0_pins: i2c0_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			i2c1_pins: i2c1_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			i2c2_pins: i2c2_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			i2c3_pins: i2c3_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			uart0_pins: uart0_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			uart1_pins: uart1_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			uart2_pins: uart2_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			spi0_pins: spi0_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-
-			spi1_pins: spi1_pins {
-				pinctrl-pins = <
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0)
-					UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0)
-				>;
-
-				pinconf-pins = <
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF)
-					UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF)
-				>;
-			};
-		};
+	spi1_pins: spi1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  0  UR_FUNC0
+		UR_DP1000_IOMUX_A  1  UR_FUNC0
+		UR_DP1000_IOMUX_A  2  UR_FUNC0
+		UR_DP1000_IOMUX_A  3  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  0  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  1  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  2  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  3  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
 	};
 };
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts
index a74714629566..dc057cbaf59b 100644
--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts
@@ -3,10 +3,16 @@
  * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd.
  */
 
-#include "dp1000.dts"
 #include "dp1000-mo-pinctrl.dtsi"
 #include <dt-bindings/iio/temperature/thermocouple.h>
 
+/ {
+	chosen {
+		bootargs = "earlycon=sbi console=ttyS0,115200";
+		stdout-path = &uart0;
+	};
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi
new file mode 100644
index 000000000000..35429e539832
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/ur-dp1000-pinctrl.h>
+#include "dp1000.dtsi"
+
+&pmx0 {
+	i2c0_pins: i2c0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  12  UR_FUNC0
+		UR_DP1000_IOMUX_A  13  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  12  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  13  UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c1_pins: i2c1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_B  6  UR_FUNC0
+		UR_DP1000_IOMUX_B  7  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_B  6   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_B  7   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c2_pins: i2c2_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  0  UR_FUNC0
+		UR_DP1000_IOMUX_C  1  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  0   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  1   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	i2c3_pins: i2c3_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  2  UR_FUNC0
+		UR_DP1000_IOMUX_C  3  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  2   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  3   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart0_pins: uart0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  8  UR_FUNC1
+		UR_DP1000_IOMUX_A  9  UR_FUNC1
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  8   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  9   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart1_pins: uart1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_B  4  UR_FUNC0
+		UR_DP1000_IOMUX_B  5  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_B  4   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_B  5   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart2_pins: uart2_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  4  UR_FUNC0
+		UR_DP1000_IOMUX_C  5  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  4   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  5   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	uart3_pins: uart3_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_C  6  UR_FUNC0
+		UR_DP1000_IOMUX_C  7  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_C  6   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_C  7   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	spi0_pins: spi0_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_D  0  UR_FUNC1
+		UR_DP1000_IOMUX_D  1  UR_FUNC1
+		UR_DP1000_IOMUX_D  2  UR_FUNC1
+		UR_DP1000_IOMUX_D  3  UR_FUNC1
+		UR_DP1000_IOMUX_D  4  UR_FUNC1
+		UR_DP1000_IOMUX_D  5  UR_FUNC1
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_D  0   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  1   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  2   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  3   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  4   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  5   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	spi1_pins: spi1_pins {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  0  UR_FUNC0
+		UR_DP1000_IOMUX_A  1  UR_FUNC0
+		UR_DP1000_IOMUX_A  2  UR_FUNC0
+		UR_DP1000_IOMUX_A  3  UR_FUNC0
+		UR_DP1000_IOMUX_A  4  UR_FUNC0
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  0   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  1   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  2   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  3   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  4   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+
+	gpios_pin: gpios_pin {
+		pinctrl-pins = <
+		UR_DP1000_IOMUX_A  10  UR_FUNC_DEF
+		UR_DP1000_IOMUX_A  11  UR_FUNC_DEF
+		UR_DP1000_IOMUX_A  14  UR_FUNC_DEF
+		UR_DP1000_IOMUX_A  15  UR_FUNC_DEF
+
+		UR_DP1000_IOMUX_B  0   UR_FUNC_DEF
+		UR_DP1000_IOMUX_B  1   UR_FUNC_DEF
+		UR_DP1000_IOMUX_B  2   UR_FUNC_DEF
+
+		UR_DP1000_IOMUX_D  6   UR_FUNC_DEF
+		UR_DP1000_IOMUX_D  7   UR_FUNC_DEF
+		>;
+
+		pinconf-pins = <
+		UR_DP1000_IOMUX_A  10   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  11   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  14   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_A  15   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+
+		UR_DP1000_IOMUX_B  0   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_B  1   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_B  2   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+
+		UR_DP1000_IOMUX_D  6   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		UR_DP1000_IOMUX_D  7   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
+		>;
+	};
+};
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts
new file mode 100644
index 000000000000..2cbdfa2ad813
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include "dp1000-titan-pinctrl.dtsi"
+#include <dt-bindings/iio/temperature/thermocouple.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+/ {
+	chosen {
+		bootargs = "earlycon=sbi console=ttyS0,115200";
+		stdout-path = &uart0;
+	};
+
+	gpio-poweroff {
+		compatible = "gpio-poweroff";
+		gpios = <&portb 0 GPIO_ACTIVE_LOW>;
+		active-delay-ms = <100>;
+		line-name = "power-off";
+		status = "okay";
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&portb 1 GPIO_ACTIVE_LOW>;
+		active-delay-ms = <100>;
+		line-name = "reset-system";
+		status = "okay";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-wakeup {
+			label = "Wake-Up";
+			gpios = <&porta 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WAKEUP>;
+			linux,input-type = <EV_KEY>;
+			debounce-interval = <10>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+
+	rtc@68 {
+		compatible = "st,m41t11";
+		reg = <0x68>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+};
+
+&spi1 {
+	num-cs = <1>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
+
+&porta {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpios_pin>;
+
+	i2c1-mux-hog {
+		gpio-hog;
+		gpios = <5 GPIO_ACTIVE_HIGH>;
+		/* LOW: DCDC(U6) connect MCU(EC)
+		 * HIGH: DCDC(U6) connect CPU
+		 */
+		output-low;
+		line-name = "gpio-mux-dcdc";
+	};
+
+	i2c3-mux-hog {
+		gpio-hog;
+		gpios = <6 GPIO_ACTIVE_LOW>;
+		/* LOW: CPU i2c3 connect nvme
+		 * HIGH: CPU i2c3 connect pciex16
+		 */
+		output-low;
+		line-name = "gpio-mux-i2c3";
+	};
+
+	uart0-mux-hog {
+		gpio-hog;
+		gpios = <7 GPIO_ACTIVE_HIGH>;
+		/* LOW: uart_debug connect BMC
+		 * HIGH: uart_debug connect CPU
+		 */
+		output-high;
+		line-name = "gpio-mux-debug";
+	};
+};
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
similarity index 95%
rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts
rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
index bd0a40cc7fe9..5fbd51bfaffc 100644
--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
@@ -10,17 +10,12 @@
 	#size-cells = <0x02>;
 	compatible = "ultrarisc,dp1000";
 	model = "ultrarisc,dp1000";
-	
-	chosen {
-		bootargs = "earlycon=sbi console=ttyS1,115200";
-		stdout-path = &uart1;
-	};
-	
+
 	cpus {
 		#address-cells = <0x01>;
 		#size-cells = <0x00>;
 		timebase-frequency = <10000000>;
-		
+
 		cpu0: cpu@0 {
 			device_type = "cpu";
 			reg = <0x00>;
@@ -144,18 +139,18 @@
 			};
 		};
 	};
-	
+
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x00 0x80000000 0x4 0x00000000>;
 	};
-	
+
 	soc {
 		#address-cells = <0x02>;
 		#size-cells = <0x02>;
 		compatible = "simple-bus";
 		ranges;
-		
+
 		clocks {
 			compatible = "simple-bus";
 			u-boot,dm-pre-reloc;
@@ -164,13 +159,14 @@
 				clock-frequency = <62500000>;
 				#clock-cells = <0>;
 			};
+
 			csr_clk: csr_clk {
 				compatible = "fixed-clock";
 				clock-frequency = <250000000>;
 				#clock-cells = <0>;
 			};
 		};
-		
+
 		clint: clint@8000000 {
 			compatible = "riscv,clint0";
 			interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>,
@@ -183,7 +179,7 @@
 			<&cpu7_intc 0x03>, <&cpu7_intc 0x07>;
 			reg = <0x00 0x8000000 0x00 0x100000>;
 		};
-		
+
 		plic: plic@9000000 {
 			#interrupt-cells = <1>;
 			#address-cells = <0>;
@@ -202,7 +198,7 @@
 			riscv,max-priority = <0x07>;
 			riscv,ndev = <160>;
 		};
-		
+
 		uart0: serial@20300000 {
 			interrupt-parent = <0x01>;
 			interrupts = <17>;
@@ -213,7 +209,7 @@
 			reg-offset = <0x0>;
 			reg-shift = <0x02>;
 		};
-		
+
 		uart1: serial@20310000 {
 			interrupt-parent = <0x01>;
 			interrupts = <18>;
@@ -224,7 +220,7 @@
 			reg-offset = <0x0>;
 			reg-shift = <0x02>;
 		};
-		
+
 		uart2: serial@20400000 {
 			interrupt-parent = <0x01>;
 			interrupts = <25>;
@@ -235,7 +231,7 @@
 			reg-offset = <0x0>;
 			reg-shift = <0x02>;
 		};
-		
+
 		uart3: serial@20410000 {
 			interrupt-parent = <0x01>;
 			interrupts = <26>;
@@ -246,7 +242,7 @@
 			reg-offset = <0x0>;
 			reg-shift = <0x02>;
 		};
-		
+
 		spi0: spi@20320000 {
 			compatible = "baikal,bt1-ssi","snps,dw-apb-ssi";
 			status = "okay";
@@ -260,7 +256,7 @@
 			num-cs = <3>;
 			spi-max-frequency = <62500000>;
 		};
-		
+
 		spi1: spi@20420000 {
 			compatible = "baikal,bt1-ssi","snps,dw-apb-ssi";
 			status = "okay";
@@ -274,7 +270,7 @@
 			num-cs = <3>;
 			spi-max-frequency = <62500000>;
 		};
-		
+
 		i2c0: i2c@20330000{
 			compatible = "snps,designware-i2c";
 			status = "okay";
@@ -286,7 +282,7 @@
 			interrupt-parent = <0x01>;
 			interrupts = <20>;
 		};
-		
+
 		i2c1: i2c@20340000{
 			compatible = "snps,designware-i2c";
 			status = "okay";
@@ -298,7 +294,7 @@
 			interrupt-parent = <0x01>;
 			interrupts = <21>;
 		};
-		
+
 		i2c2: i2c@20430000{
 			compatible = "snps,designware-i2c";
 			status = "okay";
@@ -310,7 +306,7 @@
 			interrupt-parent = <0x01>;
 			interrupts = <28>;
 		};
-		
+
 		i2c3: i2c@20440000{
 			compatible = "snps,designware-i2c";
 			status = "okay";
@@ -322,7 +318,7 @@
 			interrupt-parent = <0x01>;
 			interrupts = <29>;
 		};
-		
+
 		wdt0: watchdog@20210000 {
 			compatible = "snps,dw-wdt";
 			status = "okay";
@@ -333,29 +329,18 @@
 			interrupts = <33>;
 			clocks = <&device_clk>;
 		};
-		
-		timer0: timer@20220000 {
-			compatible = "snps,dw-apb-timer";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0 0x20220000 0x0 0x100>;
-			clocks = <&device_clk>;
-			interrupt-parent = <0x01>;
-			interrupts = <35>;
-			status = "okay";
-		};
-		
-		timer1: timer@20230000 {
-			compatible = "snps,dw-apb-timer";
+
+		pmx0: pinmux@11081000 {
+			compatible = "ultrarisc,dp1000-pinctrl";
+			reg = <0x0 0x11081000  0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0x0 0x20230000 0x0 0x100>;
-			clocks = <&device_clk>;
-			interrupt-parent = <0x01>;
-			interrupts = <36>;
-			status = "okay";
+			#pinctrl-cells = <2>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x3ff>;
+			pinctrl-use-default;
 		};
-		
+
 		gpio: gpio@20200000 {
 			compatible = "snps,dw-apb-gpio";
       			#address-cells = <1>;
@@ -375,6 +360,7 @@
 				#interrupt-cells = <2>;
 				interrupt-parent = <0x01>;
 				interrupts = <34>;
+				gpio-ranges = <&pmx0 0 0 16>;
 			};
 
 			portb: gpio-port@1 {
@@ -383,6 +369,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <8>;
+				gpio-ranges = <&pmx0 16 0 8>;
 			};
 
 			portc: gpio-port@2 {
@@ -391,6 +378,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <8>;
+				gpio-ranges = <&pmx0 24 0 8>;
 			};
 
 			portd: gpio-port@3 {
@@ -399,9 +387,10 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <8>;
+				gpio-ranges = <&pmx0 32 0 8>;
 			};
 		};
-		
+
 		ethernet1@38000000 {
 			clocks = <&csr_clk>;
 			clock-names = "stmmaceth";
@@ -427,7 +416,7 @@
 				};
 			};
 		};
-		
+
 		dmac: dma-controller@39000000 {
 			compatible = "snps,axi-dma-1.01a";
 			#address-cells = <1>;
diff --git a/arch/riscv/configs/deepin_riscv64_desktop_defconfig b/arch/riscv/configs/deepin_riscv64_desktop_defconfig
index e568514a683c..7a8fb9876602 100644
--- a/arch/riscv/configs/deepin_riscv64_desktop_defconfig
+++ b/arch/riscv/configs/deepin_riscv64_desktop_defconfig
@@ -1175,6 +1175,8 @@ CONFIG_INPUT_JOYDEV=m
 CONFIG_INPUT_EVDEV=m
 CONFIG_KEYBOARD_ADP5588=m
 CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_GPIO_POLLED=m
 CONFIG_KEYBOARD_LM8323=m
 CONFIG_KEYBOARD_MAX7359=m
 CONFIG_KEYBOARD_OPENCORES=m
@@ -1632,8 +1634,8 @@ CONFIG_DRM_AMD_DC_SI=y
 CONFIG_DRM_NOUVEAU=m
 CONFIG_DRM_VGEM=m
 CONFIG_DRM_UDL=m
-CONFIG_DRM_SUN4I=m
 CONFIG_DRM_SMI=m
+CONFIG_DRM_SUN4I=m
 CONFIG_DRM_QXL=m
 CONFIG_DRM_VIRTIO_GPU=m
 CONFIG_DRM_BOCHS=m
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 551829884734..dcfaa3812306 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -16,8 +16,6 @@
 
 #include <asm/irq_vectors.h>
 
-#define IRQ_MATRIX_BITS		NR_VECTORS
-
 #ifndef __ASSEMBLY__
 
 #include <linux/percpu.h>
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 84cb9cda365a..16c9d11d8048 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,6 +19,8 @@
 #include <linux/smp.h>
 #include <linux/soc/andes/irq.h>
 
+#include <asm/hwcap.h>
+
 static struct irq_domain *intc_domain;
 static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
 static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG;
@@ -32,6 +34,14 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 		pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause);
 }
 
+static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs)
+{
+	unsigned long topi;
+
+	while ((topi = csr_read(CSR_TOPI)))
+		generic_handle_domain_irq(intc_domain, topi >> TOPI_IID_SHIFT);
+}
+
 /*
  * On RISC-V systems local interrupts are masked or unmasked by writing
  * the SIE (Supervisor Interrupt Enable) CSR.  As CSRs can only be written
@@ -41,12 +51,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 
 static void riscv_intc_irq_mask(struct irq_data *d)
 {
-	csr_clear(CSR_IE, BIT(d->hwirq));
+	if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG)
+		csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG));
+	else
+		csr_clear(CSR_IE, BIT(d->hwirq));
 }
 
 static void riscv_intc_irq_unmask(struct irq_data *d)
 {
-	csr_set(CSR_IE, BIT(d->hwirq));
+	if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG)
+		csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG));
+	else
+		csr_set(CSR_IE, BIT(d->hwirq));
 }
 
 static void andes_intc_irq_mask(struct irq_data *d)
@@ -133,8 +149,9 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
 	 * Only allow hwirq for which we have corresponding standard or
 	 * custom interrupt enable register.
 	 */
-	if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
-	    (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+	if (hwirq >= riscv_intc_nr_irqs &&
+	    (hwirq < riscv_intc_custom_base ||
+	     hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
 		return -EINVAL;
 
 	for (i = 0; i < nr_irqs; i++) {
@@ -158,8 +175,7 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
 	return intc_domain->fwnode;
 }
 
-static int __init riscv_intc_init_common(struct fwnode_handle *fn,
-					 struct irq_chip *chip)
+static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_chip *chip)
 {
 	int rc;
 
@@ -169,7 +185,12 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn,
 		return -ENXIO;
 	}
 
-	rc = set_handle_irq(&riscv_intc_irq);
+	if (riscv_isa_extension_available(NULL, SxAIA)) {
+		riscv_intc_nr_irqs = 64;
+		rc = set_handle_irq(&riscv_intc_aia_irq);
+	} else {
+		rc = set_handle_irq(&riscv_intc_irq);
+	}
 	if (rc) {
 		pr_err("failed to set irq handler\n");
 		return rc;
@@ -177,11 +198,11 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn,
 
 	riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
 
-	pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
-	if (riscv_intc_custom_nr_irqs) {
-		pr_info("%d custom local interrupts mapped\n",
-			riscv_intc_custom_nr_irqs);
-	}
+	pr_info("%d local interrupts mapped%s\n",
+		riscv_intc_nr_irqs,
+		riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : "");
+	if (riscv_intc_custom_nr_irqs)
+		pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs);
 
 	return 0;
 }
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index baa850875407..c728db164f83 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -3,7 +3,7 @@
  * Copyright (C) 2017 SiFive
  * Copyright (C) 2018 Christoph Hellwig
  */
-#define pr_fmt(fmt) "plic: " fmt
+#define pr_fmt(fmt) "riscv-plic: " fmt
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
@@ -67,7 +67,7 @@
 #define PLIC_QUIRK_CLAIM_REGISTER	1
 
 struct plic_priv {
-	struct device *dev;
+	struct fwnode_handle *fwnode;
 	struct cpumask lmask;
 	struct irq_domain *irqdomain;
 	void __iomem *regs;
@@ -89,7 +89,7 @@ struct plic_handler {
 	struct plic_priv	*priv;
 };
 static int plic_parent_irq __ro_after_init;
-static bool plic_cpuhp_setup_done __ro_after_init;
+static bool plic_global_setup_done __ro_after_init;
 static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
 
 static int plic_irq_set_type(struct irq_data *d, unsigned int type);
@@ -107,9 +107,11 @@ static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
 
 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
 {
-	raw_spin_lock(&handler->enable_lock);
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&handler->enable_lock, flags);
 	__plic_toggle(handler->enable_base, hwirq, enable);
-	raw_spin_unlock(&handler->enable_lock);
+	raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
 }
 
 static inline void plic_irq_toggle(const struct cpumask *mask,
@@ -249,6 +251,7 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type)
 static int plic_irq_suspend(void)
 {
 	unsigned int i, cpu;
+	unsigned long flags;
 	u32 __iomem *reg;
 	struct plic_priv *priv;
 
@@ -266,12 +269,12 @@ static int plic_irq_suspend(void)
 		if (!handler->present)
 			continue;
 
-		raw_spin_lock(&handler->enable_lock);
+		raw_spin_lock_irqsave(&handler->enable_lock, flags);
 		for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
 			reg = handler->enable_base + i * sizeof(u32);
 			handler->enable_save[i] = readl(reg);
 		}
-		raw_spin_unlock(&handler->enable_lock);
+		raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
 	}
 
 	return 0;
@@ -280,6 +283,7 @@ static int plic_irq_suspend(void)
 static void plic_irq_resume(void)
 {
 	unsigned int i, index, cpu;
+	unsigned long flags;
 	u32 __iomem *reg;
 	struct plic_priv *priv;
 
@@ -298,12 +302,12 @@ static void plic_irq_resume(void)
 		if (!handler->present)
 			continue;
 
-		raw_spin_lock(&handler->enable_lock);
+		raw_spin_lock_irqsave(&handler->enable_lock, flags);
 		for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
 			reg = handler->enable_base + i * sizeof(u32);
 			writel(handler->enable_save[i], reg);
 		}
-		raw_spin_unlock(&handler->enable_lock);
+		raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
 	}
 }
 
@@ -459,9 +463,10 @@ static void plic_handle_irq(struct irq_desc *desc)
 	while ((hwirq = plic_get_hwirq())) {
 		int err = generic_handle_domain_irq(handler->priv->irqdomain,
 						    hwirq);
-		if (unlikely(err))
-			pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
-					hwirq);
+		if (unlikely(err)) {
+			pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n",
+					    handler->priv->fwnode, hwirq);
+		}
 	}
 
 	chained_irq_exit(chip, desc);
@@ -489,7 +494,8 @@ static int plic_starting_cpu(unsigned int cpu)
 		enable_percpu_irq(plic_parent_irq,
 				  irq_get_trigger_type(plic_parent_irq));
 	else
-		pr_warn("cpu%d: parent irq not available\n", cpu);
+		pr_warn("%pfwP: cpu%d: parent irq not available\n",
+			handler->priv->fwnode, cpu);
 	plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);
 
 	return 0;
@@ -507,67 +513,109 @@ static const struct of_device_id plic_match[] = {
 	{}
 };
 
-static int plic_probe(struct platform_device *pdev)
+static int plic_parse_nr_irqs_and_contexts(struct fwnode_handle *fwnode,
+					   u32 *nr_irqs, u32 *nr_contexts)
+{
+	int rc;
+
+	/*
+	 * Currently, only OF fwnode is supported so extend this
+	 * function for ACPI support.
+	 */
+	if (!is_of_node(fwnode))
+		return -EINVAL;
+
+	rc = of_property_read_u32(to_of_node(fwnode), "riscv,ndev", nr_irqs);
+	if (rc) {
+		pr_err("%pfwP: riscv,ndev property not available\n", fwnode);
+		return rc;
+	}
+
+	*nr_contexts = of_irq_count(to_of_node(fwnode));
+	if (WARN_ON(!(*nr_contexts))) {
+		pr_err("%pfwP: no PLIC context available\n", fwnode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int plic_parse_context_parent(struct fwnode_handle *fwnode, u32 context,
+				     u32 *parent_hwirq, int *parent_cpu)
 {
-	int error = 0, nr_contexts, nr_handlers = 0, i;
-	struct device *dev = &pdev->dev;
+	struct of_phandle_args parent;
+	unsigned long hartid;
+	int rc;
+
+	/*
+	 * Currently, only OF fwnode is supported so extend this
+	 * function for ACPI support.
+	 */
+	if (!is_of_node(fwnode))
+		return -EINVAL;
+
+	rc = of_irq_parse_one(to_of_node(fwnode), context, &parent);
+	if (rc)
+		return rc;
+
+	rc = riscv_of_parent_hartid(parent.np, &hartid);
+	if (rc)
+		return rc;
+
+	*parent_hwirq = parent.args[0];
+	*parent_cpu = riscv_hartid_to_cpuid(hartid);
+	return 0;
+}
+
+static int plic_probe(struct fwnode_handle *fwnode)
+{
+	int error = 0, nr_contexts, nr_handlers = 0, cpu, i;
 	unsigned long plic_quirks = 0;
 	struct plic_handler *handler;
+	u32 nr_irqs, parent_hwirq;
 	struct plic_priv *priv;
-	bool cpuhp_setup;
-	unsigned int cpu;
-	u32 nr_irqs;
+	irq_hw_number_t hwirq;
+	void __iomem *regs;
 
-	if (is_of_node(dev->fwnode)) {
+	if (is_of_node(fwnode)) {
 		const struct of_device_id *id;
 
-		id = of_match_node(plic_match, to_of_node(dev->fwnode));
+		id = of_match_node(plic_match, to_of_node(fwnode));
 		if (id)
 			plic_quirks = (unsigned long)id->data;
+
+		regs = of_iomap(to_of_node(fwnode), 0);
+		if (!regs)
+			return -ENOMEM;
+	} else {
+		return -ENODEV;
 	}
 
-	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
+	error = plic_parse_nr_irqs_and_contexts(fwnode, &nr_irqs, &nr_contexts);
+	if (error)
+		goto fail_free_regs;
 
-	priv->dev = dev;
-	priv->plic_quirks = plic_quirks;
-
-	priv->regs = of_iomap(to_of_node(dev->fwnode), 0);
-	if (WARN_ON(!priv->regs)) {
-		error = -EIO;
-		goto out_free_priv;
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		error = -ENOMEM;
+		goto fail_free_regs;
 	}
 
-	error = -EINVAL;
-	of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", &nr_irqs);
-	if (WARN_ON(!nr_irqs))
-		goto out_iounmap;
-
+	priv->fwnode = fwnode;
+	priv->plic_quirks = plic_quirks;
 	priv->nr_irqs = nr_irqs;
+	priv->regs = regs;
 
-	priv->prio_save = bitmap_alloc(nr_irqs, GFP_KERNEL);
-	if (!priv->prio_save)
-		goto out_free_priority_reg;
-
-	nr_contexts = of_irq_count(to_of_node(dev->fwnode));
-	if (WARN_ON(!nr_contexts))
-		goto out_free_priority_reg;
-
-	error = -ENOMEM;
-	priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1,
-						&plic_irqdomain_ops, priv);
-	if (WARN_ON(!priv->irqdomain))
-		goto out_free_priority_reg;
+	priv->prio_save = bitmap_zalloc(nr_irqs, GFP_KERNEL);
+	if (!priv->prio_save) {
+		error = -ENOMEM;
+		goto fail_free_priv;
+	}
 
 	for (i = 0; i < nr_contexts; i++) {
-		struct of_phandle_args parent;
-		irq_hw_number_t hwirq;
-		int cpu;
-		unsigned long hartid;
-
-		if (of_irq_parse_one(to_of_node(dev->fwnode), i, &parent)) {
-			pr_err("failed to parse parent for context %d.\n", i);
+		error = plic_parse_context_parent(fwnode, i, &parent_hwirq, &cpu);
+		if (error) {
+			pr_warn("%pfwP: hwirq for context%d not found\n", fwnode, i);
 			continue;
 		}
 
@@ -575,7 +623,7 @@ static int plic_probe(struct platform_device *pdev)
 		 * Skip contexts other than external interrupts for our
 		 * privilege level.
 		 */
-		if (parent.args[0] != RV_IRQ_EXT) {
+		if (parent_hwirq != RV_IRQ_EXT) {
 			/* Disable S-mode enable bits if running in M-mode. */
 			if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
 				void __iomem *enable_base = priv->regs +
@@ -588,26 +636,11 @@ static int plic_probe(struct platform_device *pdev)
 			continue;
 		}
 
-		error = riscv_of_parent_hartid(parent.np, &hartid);
-		if (error < 0) {
-			pr_warn("failed to parse hart ID for context %d.\n", i);
-			continue;
-		}
-
-		cpu = riscv_hartid_to_cpuid(hartid);
 		if (cpu < 0) {
-			pr_warn("Invalid cpuid for context %d\n", i);
+			pr_warn("%pfwP: Invalid cpuid for context %d\n", fwnode, i);
 			continue;
 		}
 
-		/* Find parent domain and register chained handler */
-		if (!plic_parent_irq && irq_find_host(parent.np)) {
-			plic_parent_irq = irq_of_parse_and_map(to_of_node(dev->fwnode), i);
-			if (plic_parent_irq)
-				irq_set_chained_handler(plic_parent_irq,
-							plic_handle_irq);
-		}
-
 		/*
 		 * When running in M-mode we need to ignore the S-mode handler.
 		 * Here we assume it always comes later, but that might be a
@@ -615,7 +648,7 @@ static int plic_probe(struct platform_device *pdev)
 		 */
 		handler = per_cpu_ptr(&plic_handlers, cpu);
 		if (handler->present) {
-			pr_warn("handler already present for context %d.\n", i);
+			pr_warn("%pfwP: handler already present for context %d.\n", fwnode, i);
 			plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
 			goto done;
 		}
@@ -629,10 +662,12 @@ static int plic_probe(struct platform_device *pdev)
 			i * CONTEXT_ENABLE_SIZE;
 		handler->priv = priv;
 
-		handler->enable_save =  kcalloc(DIV_ROUND_UP(nr_irqs, 32),
-						sizeof(*handler->enable_save), GFP_KERNEL);
-		if (!handler->enable_save)
-			goto out_free_enable_reg;
+		handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32),
+					       sizeof(*handler->enable_save), GFP_KERNEL);
+		if (!handler->enable_save) {
+			error = -ENOMEM;
+			goto fail_cleanup_contexts;
+		}
 done:
 		for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
 			plic_toggle(handler, hwirq, 0);
@@ -642,52 +677,93 @@ static int plic_probe(struct platform_device *pdev)
 		nr_handlers++;
 	}
 
+	priv->irqdomain = irq_domain_add_linear(to_of_node(fwnode), nr_irqs + 1,
+						&plic_irqdomain_ops, priv);
+	if (WARN_ON(!priv->irqdomain)) {
+		error = -ENOMEM;
+		goto fail_cleanup_contexts;
+	}
+
 	/*
-	 * We can have multiple PLIC instances so setup cpuhp state
+	 * We can have multiple PLIC instances so setup global state
 	 * and register syscore operations only once after context
 	 * handlers of all online CPUs are initialized.
 	 */
-	if (!plic_cpuhp_setup_done) {
-		cpuhp_setup = true;
+	if (!plic_global_setup_done) {
+		struct irq_domain *domain;
+		bool global_setup = true;
+
 		for_each_online_cpu(cpu) {
 			handler = per_cpu_ptr(&plic_handlers, cpu);
 			if (!handler->present) {
-				cpuhp_setup = false;
+				global_setup = false;
 				break;
 			}
 		}
-		if (cpuhp_setup) {
+
+		if (global_setup) {
+			/* Find parent domain and register chained handler */
+			domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
+			if (domain)
+				plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT);
+			if (plic_parent_irq)
+				irq_set_chained_handler(plic_parent_irq, plic_handle_irq);
+
 			cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
 					  "irqchip/sifive/plic:starting",
 					  plic_starting_cpu, plic_dying_cpu);
 			register_syscore_ops(&plic_irq_syscore_ops);
-			plic_cpuhp_setup_done = true;
+			plic_global_setup_done = true;
 		}
 	}
 
-	pr_info("%pOFP: mapped %d interrupts with %d handlers for %d contexts.\n",
-		to_of_node(dev->fwnode), nr_irqs, nr_handlers, nr_contexts);
+	pr_info("%pfwP: mapped %d interrupts with %d handlers for %d contexts.\n",
+		fwnode, nr_irqs, nr_handlers, nr_contexts);
 	return 0;
 
-out_free_enable_reg:
-	for_each_cpu(cpu, cpu_present_mask) {
+fail_cleanup_contexts:
+	for (i = 0; i < nr_contexts; i++) {
+		if (plic_parse_context_parent(fwnode, i, &parent_hwirq, &cpu))
+			continue;
+		if (parent_hwirq != RV_IRQ_EXT || cpu < 0)
+			continue;
+
 		handler = per_cpu_ptr(&plic_handlers, cpu);
+		handler->present = false;
+		handler->hart_base = NULL;
+		handler->enable_base = NULL;
 		kfree(handler->enable_save);
+		handler->enable_save = NULL;
+		handler->priv = NULL;
 	}
-out_free_priority_reg:
-	kfree(priv->prio_save);
-out_iounmap:
-	iounmap(priv->regs);
-out_free_priv:
+	bitmap_free(priv->prio_save);
+fail_free_priv:
 	kfree(priv);
+fail_free_regs:
+	iounmap(regs);
 	return error;
 }
 
+static int plic_platform_probe(struct platform_device *pdev)
+{
+	return plic_probe(pdev->dev.fwnode);
+}
+
 static struct platform_driver plic_driver = {
 	.driver = {
 		.name		= "riscv-plic",
 		.of_match_table	= plic_match,
+		.suppress_bind_attrs = true,
 	},
-	.probe = plic_probe,
+	.probe = plic_platform_probe,
 };
 builtin_platform_driver(plic_driver);
+
+static int __init plic_early_probe(struct device_node *node,
+				   struct device_node *parent)
+{
+	return plic_probe(&node->fwnode);
+}
+
+IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe);
+IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe);
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 9055ce34c636..e1d60b908ac7 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -190,12 +190,6 @@ static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 		(int)data->hwirq, msg->address_hi, msg->address_lo);
 }
 
-static int ks_pcie_msi_set_affinity(struct irq_data *irq_data,
-				    const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static void ks_pcie_msi_mask(struct irq_data *data)
 {
 	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
@@ -248,7 +242,6 @@ static struct irq_chip ks_pcie_msi_irq_chip = {
 	.name = "KEYSTONE-PCI-MSI",
 	.irq_ack = ks_pcie_msi_irq_ack,
 	.irq_compose_msi_msg = ks_pcie_compose_msi_msg,
-	.irq_set_affinity = ks_pcie_msi_set_affinity,
 	.irq_mask = ks_pcie_msi_mask,
 	.irq_unmask = ks_pcie_msi_unmask,
 };
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 14adf8d75699..78b08b2f6d45 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -45,14 +45,12 @@ static struct irq_chip dw_pcie_msi_irq_chip = {
 	.irq_ack = dw_msi_ack_irq,
 	.irq_mask = dw_msi_mask_irq,
 	.irq_unmask = dw_msi_unmask_irq,
-#if defined CONFIG_SMP && defined CONFIG_PCIE_ULTRARISC
-	.irq_set_affinity = irq_chip_set_affinity_parent,
-#endif
 };
 
 static struct msi_domain_info dw_pcie_msi_domain_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		   MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX |
+		  MSI_FLAG_MULTI_PCI_MSI,
 	.chip	= &dw_pcie_msi_irq_chip,
 };
 
@@ -119,24 +117,6 @@ static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
 		(int)d->hwirq, msg->address_hi, msg->address_lo);
 }
 
-static int dw_pci_msi_set_affinity(struct irq_data *d,
-				   const struct cpumask *mask, bool force)
-{
-#ifdef CONFIG_PCIE_ULTRARISC
-	struct irq_domain *domain = d->domain;
-	struct dw_pcie_rp *pp = domain->host_data;
-	struct irq_desc *desc;
-	struct irq_data *data;
-
-	desc = irq_to_desc(pp->msi_irq[0]);
-	data = &(desc->irq_data);
-
-	if (data->chip->irq_set_affinity)
-		return data->chip->irq_set_affinity(data, mask, force);
-#endif
-	return -EINVAL;
-}
-
 static void dw_pci_bottom_mask(struct irq_data *d)
 {
 	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
@@ -192,7 +172,6 @@ static struct irq_chip dw_pci_msi_bottom_irq_chip = {
 	.name = "DWPCI-MSI",
 	.irq_ack = dw_pci_bottom_ack,
 	.irq_compose_msi_msg = dw_pci_setup_msi_msg,
-	.irq_set_affinity = dw_pci_msi_set_affinity,
 	.irq_mask = dw_pci_bottom_mask,
 	.irq_unmask = dw_pci_bottom_unmask,
 };
diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
index 9a11fc7ad7d7..73c9cd36ca90 100644
--- a/drivers/pci/controller/dwc/pcie-ultrarisc.c
+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
@@ -29,6 +29,7 @@
 
 struct ultrarisc_pcie {
 	struct dw_pcie  *pci;
+	u32 irq_mask[MAX_MSI_CTRLS];
 };
 
 static const struct of_device_id ultrarisc_pcie_of_match[];
@@ -138,6 +139,49 @@ static int ultrarisc_pcie_probe(struct platform_device *pdev)
 	return 0;
 }
 
+int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
+	struct dw_pcie *pci = ultrarisc_pcie->pci;
+	struct dw_pcie_rp *pp = &pci->pp;
+	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+	unsigned long flags;
+	int ctrl;
+
+	raw_spin_lock_irqsave(&pp->lock, flags);
+
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
+		ultrarisc_pcie->irq_mask[ctrl] = pp->irq_mask[ctrl];
+
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
+
+	return 0;
+}
+
+int ultrarisc_pcie_resume(struct platform_device *pdev)
+{
+	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
+	struct dw_pcie *pci = ultrarisc_pcie->pci;
+	struct dw_pcie_rp *pp = &pci->pp;
+	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+	unsigned long flags;
+	int ctrl;
+
+	raw_spin_lock_irqsave(&pp->lock, flags);
+
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+		pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl];
+		dw_pcie_writel_dbi(pci,
+				   PCIE_MSI_INTR0_MASK +
+				   ctrl * MSI_REG_CTRL_BLOCK_SIZE,
+				   pp->irq_mask[ctrl]);
+	}
+
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
+
+	return 0;
+}
+
 static const struct of_device_id ultrarisc_pcie_of_match[] = {
 	{
 		.compatible = "ultrarisc,dw-pcie",
@@ -152,5 +196,7 @@ static struct platform_driver ultrarisc_pcie_driver = {
 		.suppress_bind_attrs = true,
 	},
 	.probe = ultrarisc_pcie_probe,
+	.suspend = ultrarisc_pcie_suspend,
+	.resume = ultrarisc_pcie_resume,
 };
 builtin_platform_driver(ultrarisc_pcie_driver);
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index 45b97a4b14db..03fbd0b6bd2e 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -360,8 +360,8 @@ static struct irq_chip mobiveil_msi_irq_chip = {
 };
 
 static struct msi_domain_info mobiveil_msi_domain_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		   MSI_FLAG_PCI_MSIX),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX,
 	.chip	= &mobiveil_msi_irq_chip,
 };
 
@@ -378,16 +378,9 @@ static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 		(int)data->hwirq, msg->address_hi, msg->address_lo);
 }
 
-static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
-				     const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static struct irq_chip mobiveil_msi_bottom_irq_chip = {
 	.name			= "Mobiveil MSI",
 	.irq_compose_msi_msg	= mobiveil_compose_msi_msg,
-	.irq_set_affinity	= mobiveil_msi_set_affinity,
 };
 
 static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 71ecd7ddcc8a..d6fc4f1d0bea 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -1305,12 +1305,6 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
 	msg->data = data->hwirq;
 }
 
-static int advk_msi_set_affinity(struct irq_data *irq_data,
-				 const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static void advk_msi_irq_mask(struct irq_data *d)
 {
 	struct advk_pcie *pcie = d->domain->host_data;
@@ -1354,7 +1348,6 @@ static void advk_msi_top_irq_unmask(struct irq_data *d)
 static struct irq_chip advk_msi_bottom_irq_chip = {
 	.name			= "MSI",
 	.irq_compose_msi_msg	= advk_msi_irq_compose_msi_msg,
-	.irq_set_affinity	= advk_msi_set_affinity,
 	.irq_mask		= advk_msi_irq_mask,
 	.irq_unmask		= advk_msi_irq_unmask,
 };
@@ -1452,7 +1445,8 @@ static struct irq_chip advk_msi_irq_chip = {
 
 static struct msi_domain_info advk_msi_domain_info = {
 	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI |
+		  MSI_FLAG_PCI_MSIX,
 	.chip	= &advk_msi_irq_chip,
 };
 
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index da37569460b1..927ef421c4fc 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -1628,11 +1628,6 @@ static void tegra_msi_irq_unmask(struct irq_data *d)
 	}
 }
 
-static int tegra_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static void tegra_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 {
 	struct tegra_msi *msi = irq_data_get_irq_chip_data(data);
@@ -1647,7 +1642,6 @@ static struct irq_chip tegra_msi_bottom_chip = {
 	.irq_ack		= tegra_msi_irq_ack,
 	.irq_mask		= tegra_msi_irq_mask,
 	.irq_unmask		= tegra_msi_irq_unmask,
-	.irq_set_affinity 	= tegra_msi_set_affinity,
 	.irq_compose_msi_msg	= tegra_compose_msi_msg,
 };
 
@@ -1696,8 +1690,8 @@ static const struct irq_domain_ops tegra_msi_domain_ops = {
 };
 
 static struct msi_domain_info tegra_msi_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		   MSI_FLAG_PCI_MSIX),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX,
 	.chip	= &tegra_msi_top_chip,
 };
 
diff --git a/drivers/pci/controller/pcie-altera-msi.c b/drivers/pci/controller/pcie-altera-msi.c
index 6ad5427490b5..2fa2f91a5de3 100644
--- a/drivers/pci/controller/pcie-altera-msi.c
+++ b/drivers/pci/controller/pcie-altera-msi.c
@@ -81,8 +81,8 @@ static struct irq_chip altera_msi_irq_chip = {
 };
 
 static struct msi_domain_info altera_msi_domain_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		     MSI_FLAG_PCI_MSIX),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX,
 	.chip	= &altera_msi_irq_chip,
 };
 
@@ -99,16 +99,9 @@ static void altera_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 		(int)data->hwirq, msg->address_hi, msg->address_lo);
 }
 
-static int altera_msi_set_affinity(struct irq_data *irq_data,
-				   const struct cpumask *mask, bool force)
-{
-	 return -EINVAL;
-}
-
 static struct irq_chip altera_msi_bottom_irq_chip = {
 	.name			= "Altera MSI",
 	.irq_compose_msi_msg	= altera_compose_msi_msg,
-	.irq_set_affinity	= altera_msi_set_affinity,
 };
 
 static int altera_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 9bcf4c68058e..87d7c1876a6a 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -439,8 +439,8 @@ static struct irq_chip brcm_msi_irq_chip = {
 };
 
 static struct msi_domain_info brcm_msi_domain_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		   MSI_FLAG_MULTI_PCI_MSI),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI,
 	.chip	= &brcm_msi_irq_chip,
 };
 
@@ -478,12 +478,6 @@ static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 	msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
 }
 
-static int brcm_msi_set_affinity(struct irq_data *irq_data,
-				 const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static void brcm_msi_ack_irq(struct irq_data *data)
 {
 	struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
@@ -496,7 +490,6 @@ static void brcm_msi_ack_irq(struct irq_data *data)
 static struct irq_chip brcm_msi_bottom_irq_chip = {
 	.name			= "BRCM STB MSI",
 	.irq_compose_msi_msg	= brcm_msi_compose_msi_msg,
-	.irq_set_affinity	= brcm_msi_set_affinity,
 	.irq_ack                = brcm_msi_ack_irq,
 };
 
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 975b3024fb08..973415d3b21f 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -424,12 +424,6 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
 	return 0;
 }
 
-static int mtk_pcie_set_affinity(struct irq_data *data,
-				 const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static void mtk_pcie_msi_irq_mask(struct irq_data *data)
 {
 	pci_msi_mask_irq(data);
@@ -450,8 +444,9 @@ static struct irq_chip mtk_msi_irq_chip = {
 };
 
 static struct msi_domain_info mtk_msi_domain_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		   MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX |
+		  MSI_FLAG_MULTI_PCI_MSI,
 	.chip	= &mtk_msi_irq_chip,
 };
 
@@ -517,7 +512,6 @@ static struct irq_chip mtk_msi_bottom_irq_chip = {
 	.irq_mask		= mtk_msi_bottom_irq_mask,
 	.irq_unmask		= mtk_msi_bottom_irq_unmask,
 	.irq_compose_msi_msg	= mtk_compose_msi_msg,
-	.irq_set_affinity	= mtk_pcie_set_affinity,
 	.name			= "MSI",
 };
 
@@ -618,7 +612,6 @@ static struct irq_chip mtk_intx_irq_chip = {
 	.irq_mask		= mtk_intx_mask,
 	.irq_unmask		= mtk_intx_unmask,
 	.irq_eoi		= mtk_intx_eoi,
-	.irq_set_affinity	= mtk_pcie_set_affinity,
 	.name			= "INTx",
 };
 
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 48372013f26d..0b9d9548c8e1 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -407,12 +407,6 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 		(int)data->hwirq, msg->address_hi, msg->address_lo);
 }
 
-static int mtk_msi_set_affinity(struct irq_data *irq_data,
-				const struct cpumask *mask, bool force)
-{
-	 return -EINVAL;
-}
-
 static void mtk_msi_ack_irq(struct irq_data *data)
 {
 	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
@@ -424,7 +418,6 @@ static void mtk_msi_ack_irq(struct irq_data *data)
 static struct irq_chip mtk_msi_bottom_irq_chip = {
 	.name			= "MTK MSI",
 	.irq_compose_msi_msg	= mtk_compose_msi_msg,
-	.irq_set_affinity	= mtk_msi_set_affinity,
 	.irq_ack		= mtk_msi_ack_irq,
 };
 
@@ -486,8 +479,8 @@ static struct irq_chip mtk_msi_irq_chip = {
 };
 
 static struct msi_domain_info mtk_msi_domain_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		   MSI_FLAG_PCI_MSIX),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX,
 	.chip	= &mtk_msi_irq_chip,
 };
 
diff --git a/drivers/pci/controller/pcie-rcar-host.c b/drivers/pci/controller/pcie-rcar-host.c
index 77f6366e7db1..cf99dfa33469 100644
--- a/drivers/pci/controller/pcie-rcar-host.c
+++ b/drivers/pci/controller/pcie-rcar-host.c
@@ -647,11 +647,6 @@ static void rcar_msi_irq_unmask(struct irq_data *d)
 	}
 }
 
-static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 {
 	struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
@@ -667,7 +662,6 @@ static struct irq_chip rcar_msi_bottom_chip = {
 	.irq_ack		= rcar_msi_irq_ack,
 	.irq_mask		= rcar_msi_irq_mask,
 	.irq_unmask		= rcar_msi_irq_unmask,
-	.irq_set_affinity 	= rcar_msi_set_affinity,
 	.irq_compose_msi_msg	= rcar_compose_msi_msg,
 };
 
@@ -714,8 +708,8 @@ static const struct irq_domain_ops rcar_msi_domain_ops = {
 };
 
 static struct msi_domain_info rcar_msi_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		   MSI_FLAG_MULTI_PCI_MSI),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI,
 	.chip	= &rcar_msi_top_chip,
 };
 
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 5b82098f32b7..0c66815d719b 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -427,8 +427,8 @@ static struct irq_chip nwl_msi_irq_chip = {
 };
 
 static struct msi_domain_info nwl_msi_domain_info = {
-	.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		  MSI_FLAG_MULTI_PCI_MSI),
+	.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		 MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI,
 	.chip = &nwl_msi_irq_chip,
 };
 #endif
@@ -443,16 +443,9 @@ static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 	msg->data = data->hwirq;
 }
 
-static int nwl_msi_set_affinity(struct irq_data *irq_data,
-				const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static struct irq_chip nwl_irq_chip = {
 	.name = "Xilinx MSI",
 	.irq_compose_msi_msg = nwl_compose_msi_msg,
-	.irq_set_affinity = nwl_msi_set_affinity,
 };
 
 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c
index cb6e9f7b0152..0b534f73a942 100644
--- a/drivers/pci/controller/pcie-xilinx.c
+++ b/drivers/pci/controller/pcie-xilinx.c
@@ -208,11 +208,6 @@ static struct irq_chip xilinx_msi_top_chip = {
 	.irq_ack	= xilinx_msi_top_irq_ack,
 };
 
-static int xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 {
 	struct xilinx_pcie *pcie = irq_data_get_irq_chip_data(data);
@@ -225,7 +220,6 @@ static void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 
 static struct irq_chip xilinx_msi_bottom_chip = {
 	.name			= "Xilinx MSI",
-	.irq_set_affinity 	= xilinx_msi_set_affinity,
 	.irq_compose_msi_msg	= xilinx_compose_msi_msg,
 };
 
@@ -271,7 +265,8 @@ static const struct irq_domain_ops xilinx_msi_domain_ops = {
 };
 
 static struct msi_domain_info xilinx_msi_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
+	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		  MSI_FLAG_NO_AFFINITY,
 	.chip	= &xilinx_msi_top_chip,
 };
 
diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
index ad82feff0405..039c491709e5 100644
--- a/drivers/pci/controller/vmd.c
+++ b/drivers/pci/controller/vmd.c
@@ -206,22 +206,11 @@ static void vmd_irq_disable(struct irq_data *data)
 	raw_spin_unlock_irqrestore(&list_lock, flags);
 }
 
-/*
- * XXX: Stubbed until we develop acceptable way to not create conflicts with
- * other devices sharing the same vector.
- */
-static int vmd_irq_set_affinity(struct irq_data *data,
-				const struct cpumask *dest, bool force)
-{
-	return -EINVAL;
-}
-
 static struct irq_chip vmd_msi_controller = {
 	.name			= "VMD-MSI",
 	.irq_enable		= vmd_irq_enable,
 	.irq_disable		= vmd_irq_disable,
 	.irq_compose_msi_msg	= vmd_compose_msi_msg,
-	.irq_set_affinity	= vmd_irq_set_affinity,
 };
 
 static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info,
@@ -328,7 +317,7 @@ static struct msi_domain_ops vmd_msi_domain_ops = {
 
 static struct msi_domain_info vmd_msi_domain_info = {
 	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-			  MSI_FLAG_PCI_MSIX,
+			  MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX,
 	.ops		= &vmd_msi_domain_ops,
 	.chip		= &vmd_msi_controller,
 };
diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c
index 217f671fe63a..7db11142cfbe 100644
--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c
+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
-/* UltraRisc DP1000 pinctrl driver
+/* UltraRISC DP1000 pinctrl driver
  *
- * Copyright(C) 2025 UltraRisc Technology Co., Ltd.
+ * Copyright(C) 2025 UltraRISC Technology Co., Ltd.
  *
  *  Author:  wangjia <wangjia@ultrarisc.com>
  */
@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = {
 	.pins = ur_dp1000_pins,
 	.npins = ARRAY_SIZE(ur_dp1000_pins),
 	.offset = 0x2c0,
+	.num_ports = 5,
 	.ports = {
 		{"A", 16, 0x2c0, 0x310},
 		{"B", 8, 0x2c4, 0x318},
diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c
index 97c6b85e0ef3..1a1d118de148 100644
--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c
+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
-/* UltraRisc pinctrl driver
+/* UltraRISC pinctrl driver
  *
- * Copyright(C) 2025 UltraRisc Technology Co., Ltd.
+ * Copyright(C) 2025 UltraRISC Technology Co., Ltd.
  *
  *  Author:  wangjia <wangjia@ultrarisc.com>
  */
@@ -59,9 +59,8 @@ static int ur_subnode_to_pin(struct pinctrl_dev *pctldev,
 	}
 
 	pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL);
-	if (!pin_vals) {
+	if (!pin_vals)
 		return -ENOMEM;
-	}
 
 	group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL);
 	if (!group_pins) {
@@ -198,7 +197,6 @@ static int ur_dt_node_to_map(struct pinctrl_dev *pctldev,
 	struct pinctrl_map *new_map;
 	unsigned int map_num = 0, prop_count = 0;
 
-	//device_get_named_child_node(pctldev->dev, np->name);
 	if (of_property_present(np, PINMUX_PROP_NAME)) {
 		mux_present = true;
 		prop_count++;
@@ -269,7 +267,6 @@ static const struct pinctrl_ops ur_pinctrl_ops = {
 static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals)
 {
 	unsigned long flag;
-	//bool clear_mode = false;
 	void __iomem *reg;
 	u32 val;
 	const struct ur_port_desc *port;
@@ -326,6 +323,58 @@ static const struct pinmux_ops ur_pinmux_ops = {
 
 #define UR_CONF_BIT_PER_PIN	(4)
 #define UR_CONF_PIN_PER_REG	(32/UR_CONF_BIT_PER_PIN)
+
+static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data,
+				  struct ur_pin_val *pin_val, u32 pin_num)
+{
+	const struct ur_port_desc *port_desc;
+
+	for (int i = 0; i < match_data->num_ports; i++) {
+		port_desc = &match_data->ports[i];
+		if (pin_num < port_desc->npins) {
+			pin_val->port = i;
+			pin_val->pin = pin_num;
+			pin_val->conf = 0;
+			return 0;
+		}
+		pin_num -= port_desc->npins;
+	}
+	return -EINVAL;
+}
+
+static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl,
+				struct ur_pin_val *pin_vals,
+				unsigned long *config)
+{
+	enum pin_config_param param = pinconf_to_config_param(*config);
+	u32 arg = pinconf_to_config_argument(*config);
+
+	dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n",
+		__func__, __LINE__, param, arg);
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_DISABLE:
+		pin_vals->conf &= ~UR_BIAS_MASK;
+		break;
+	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+		pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP);
+		break;
+	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		pin_vals->conf |= UR_PULL_DOWN;
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		pin_vals->conf |= UR_PULL_UP;
+		break;
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
+	case PIN_CONFIG_PERSIST_STATE:
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+	return 0;
+}
+
 static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals)
 {
 	const struct ur_port_desc *port_desc;
@@ -334,8 +383,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v
 	u32 val, conf;
 
 	port_desc = &pin_ctrl->match_data->ports[pin_vals->port];
+	dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n",
+		pin_vals->port, pin_vals->pin, pin_vals->conf);
 	reg = pin_ctrl->base + port_desc->conf_offset;
-	dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg);
+	dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n",
+		(u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg);
 	reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN;
 	dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg);
 
@@ -358,7 +410,7 @@ static int ur_pin_config_get(struct pinctrl_dev *pctldev,
 			unsigned long *config)
 {
 	dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin);
-	// TODO: this is call by pinconf-generic
+
 	return -EOPNOTSUPP;
 }
 
@@ -367,22 +419,34 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev,
 			unsigned long *configs,
 			unsigned int num_configs)
 {
-	struct ur_pin_val *pin_conf;
+	struct ur_pin_val pin_val;
 	struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev);
+	int ret;
+
+	ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin);
+	if (ret < 0) {
+		dev_err(pctldev->dev, "invalid pin number %d\n", pin);
+		return ret;
+	}
+	dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n",
+		__func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin);
 
-	dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n",
-		__func__, __LINE__, pin, num_configs);
-	pin_conf = (struct ur_pin_val *)configs;
 	for (int i = 0; i < num_configs; i++) {
-		dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n",
-			i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf);
-		ur_set_pin_conf(ur_pinctrl, &pin_conf[i]);
+		ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]);
+		if (ret < 0) {
+			dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]);
+			return ret;
+		}
+
+		dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n",
+			__func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf);
+		ur_set_pin_conf(ur_pinctrl, &pin_val);
 	}
 	return 0;
 }
 
 static int ur_pin_config_group_get(struct pinctrl_dev *pctldev,
-				unsigned selector,
+				unsigned int selector,
 				unsigned long *config)
 {
 	dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n",
@@ -439,14 +503,11 @@ int ur_pinctrl_probe(struct platform_device *pdev)
 		return -ENODEV;
 
 	ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL);
-	if (!ur_pinctrl_desc) {
-		dev_err(&pdev->dev, "pinctrl desc alloc failed\n");
+	if (!ur_pinctrl_desc)
 		return -ENOMEM;
-	}
 
 	ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL);
 	if (!ur_pinctrl) {
-		dev_err(&pdev->dev, "pinctrl alloc failed\n");
 		ret = -ENOMEM;
 		goto free_pinctrl_desc;
 	}
@@ -474,7 +535,7 @@ int ur_pinctrl_probe(struct platform_device *pdev)
 	ur_pinctrl->pctl_desc = ur_pinctrl_desc;
 	raw_spin_lock_init(&ur_pinctrl->lock);
 	mutex_init(&ur_pinctrl->mutex);
-	
+
 	ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc,
 			ur_pinctrl, &ur_pinctrl->pctl_dev);
 	if (ret) {
diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h
index cdcc52fc766f..621cf4dd9002 100644
--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h
+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h
@@ -1,7 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0
-/* UltraRisc pinctrl driver
+/* SPDX-License-Identifier: GPL-2.0 */
+/* UltraRISC pinctrl driver
  *
- * Copyright(C) 2025 UltraRisc Technology Co., Ltd.
+ * Copyright(C) 2025 UltraRISC Technology Co., Ltd.
  *
  *  Author:  wangjia <wangjia@ultrarisc.com>
  */
@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data {
 	const struct pinctrl_pin_desc *pins;
 	u32 npins;
 	u32 offset;
-	//u32 conf_offset[];
+	u32 num_ports;
 	struct ur_port_desc ports[];
 };
 
diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h
index 97b49b0d724f..17f52b2ea54d 100644
--- a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h
+++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
-/* UltraRisc DP1000 pinctrl header
+/* UltraRISC DP1000 pinctrl header
  *
- * Copyright(C) 2025 UltraRisc Technology Co., Ltd.
+ *  Copyright(C) 2025 UltraRISC Technology Co., Ltd.
  *
  *  Author:  wangjia <wangjia@ultrarisc.com>
  */
@@ -9,17 +9,8 @@
 #ifndef __UR_DP1000_PINCTRL_H__
 #define __UR_DP1000_PINCTRL_H__
 
-#define UR_DP1000_IOMUX_A		0x0
-#define UR_DP1000_IOMUX_B		0x1
-#define UR_DP1000_IOMUX_C		0x2
-#define UR_DP1000_IOMUX_D		0x3
-#define UR_DP1000_IOMUX_LPC		0x4
-
-#define UR_FUNC_DEF				0
-#define UR_FUNC0			1
-#define UR_FUNC1			0x10000
-
 /**
+ * UltraRISC DP1000 IO pad configuration
  * port: 'A' 'B' 'C'
  *     Pin in the port
  * pin:
@@ -30,7 +21,15 @@
  *     UR_FUNC0: func0
  *     UR_FUNC1: func1
  */
-#define UR_DP1000_IOPAD(port, pin, func)	(port) (pin) (func)
+#define UR_DP1000_IOMUX_A		0x0
+#define UR_DP1000_IOMUX_B		0x1
+#define UR_DP1000_IOMUX_C		0x2
+#define UR_DP1000_IOMUX_D		0x3
+#define UR_DP1000_IOMUX_LPC		0x4
+
+#define UR_FUNC_DEF			0
+#define UR_FUNC0			1
+#define UR_FUNC1			0x10000
 
 /**
  * Configure pull up/down resistor of the IO pin
@@ -55,6 +54,11 @@
 #define UR_DRIVE_2		2
 #define UR_DRIVE_3		3
 
-#define UR_DP1000_BIAS(port, pin, pull, drive)		(port) (pin) (((pull)<<2) + (drive))
+/**
+ * Combine the pull-up/down resistor and drive strength
+ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN
+ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3
+ */
+#define UR_DP1000_BIAS(pull, drive)		(((pull)<<2) + (drive))
 
 #endif
diff --git a/include/linux/msi.h b/include/linux/msi.h
index cd9ff817acc2..11883c2b04db 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -562,8 +562,10 @@ enum {
 	MSI_FLAG_MSIX_CONTIGUOUS	= (1 << 19),
 	/* PCI/MSI-X vectors can be dynamically allocated/freed post MSI-X enable */
 	MSI_FLAG_PCI_MSIX_ALLOC_DYN	= (1 << 20),
+	/* PCI MSIs cannot be steered separately to CPU cores */
+	MSI_FLAG_NO_AFFINITY		= (1 << 21),
 	/* Support for PCI/IMS */
-	MSI_FLAG_PCI_IMS		= (1 << 21),
+	MSI_FLAG_PCI_IMS		= (1 << 22),
 };
 
 /**
diff --git a/kernel/irq/matrix.c b/kernel/irq/matrix.c
index 75d0ae490e29..8f222d1cccec 100644
--- a/kernel/irq/matrix.c
+++ b/kernel/irq/matrix.c
@@ -8,8 +8,6 @@
 #include <linux/cpu.h>
 #include <linux/irq.h>
 
-#define IRQ_MATRIX_SIZE	(BITS_TO_LONGS(IRQ_MATRIX_BITS))
-
 struct cpumap {
 	unsigned int		available;
 	unsigned int		allocated;
@@ -17,8 +15,8 @@ struct cpumap {
 	unsigned int		managed_allocated;
 	bool			initialized;
 	bool			online;
-	unsigned long		alloc_map[IRQ_MATRIX_SIZE];
-	unsigned long		managed_map[IRQ_MATRIX_SIZE];
+	unsigned long		*managed_map;
+	unsigned long		alloc_map[];
 };
 
 struct irq_matrix {
@@ -32,8 +30,8 @@ struct irq_matrix {
 	unsigned int		total_allocated;
 	unsigned int		online_maps;
 	struct cpumap __percpu	*maps;
-	unsigned long		scratch_map[IRQ_MATRIX_SIZE];
-	unsigned long		system_map[IRQ_MATRIX_SIZE];
+	unsigned long		*system_map;
+	unsigned long		scratch_map[];
 };
 
 #define CREATE_TRACE_POINTS
@@ -50,24 +48,32 @@ __init struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
 					   unsigned int alloc_start,
 					   unsigned int alloc_end)
 {
+	unsigned int cpu, matrix_size = BITS_TO_LONGS(matrix_bits);
 	struct irq_matrix *m;
 
-	if (matrix_bits > IRQ_MATRIX_BITS)
-		return NULL;
-
-	m = kzalloc(sizeof(*m), GFP_KERNEL);
+	m = kzalloc(struct_size(m, scratch_map, matrix_size * 2), GFP_KERNEL);
 	if (!m)
 		return NULL;
 
+	m->system_map = &m->scratch_map[matrix_size];
+
 	m->matrix_bits = matrix_bits;
 	m->alloc_start = alloc_start;
 	m->alloc_end = alloc_end;
 	m->alloc_size = alloc_end - alloc_start;
-	m->maps = alloc_percpu(*m->maps);
+	m->maps = __alloc_percpu(struct_size(m->maps, alloc_map, matrix_size * 2),
+				 __alignof__(*m->maps));
 	if (!m->maps) {
 		kfree(m);
 		return NULL;
 	}
+
+	for_each_possible_cpu(cpu) {
+		struct cpumap *cm = per_cpu_ptr(m->maps, cpu);
+
+		cm->managed_map = &cm->alloc_map[matrix_size];
+	}
+
 	return m;
 }
 
diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c
index 79b4a58ba9c3..926a7c5e695f 100644
--- a/kernel/irq/msi.c
+++ b/kernel/irq/msi.c
@@ -801,7 +801,7 @@ static void msi_domain_update_chip_ops(struct msi_domain_info *info)
 	struct irq_chip *chip = info->chip;
 
 	BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
-	if (!chip->irq_set_affinity)
+	if (!chip->irq_set_affinity && !(info->flags & MSI_FLAG_NO_AFFINITY))
 		chip->irq_set_affinity = msi_domain_set_affinity;
 }