[SKiDL Feature Request] RFC: layout-preserving KiCad schematic regeneration

[szc188]

Is your feature request related to a problem? Please describe.

This is a feature request / RFC rather than a bug report.

SKiDL's code-first circuit generation is useful, and generated KiCad schematics are a promising bridge between code and normal hardware review workflows. However, generated schematics often need manual cleanup in Eeschema before they are readable enough for debugging, review, and handoff.

In practice, firmware/debug/layout engineers often read the schematic to understand power flow, probe points, functional blocks, and fault isolation paths. A generated schematic may be electrically correct but still hard to debug if symbol placement, wire routing, labels, and grouping are poor.

The current concern is that rerunning schematic generation can overwrite manual readability improvements made in KiCad, even when the logical netlist has not changed.

Describe the solution you'd like

I would like to discuss whether SKiDL could support layout-preserving KiCad schematic regeneration.

A possible workflow:

1. Generate a .kicad_sch from SKiDL.
2. User opens it in KiCad/Eeschema and improves readability by moving symbols, rerouting wires, adjusting labels, and grouping functional blocks.
3. User reruns SKiDL generation.
4. If the logical identity is unchanged, preserve the existing schematic layout:
   • symbol position and rotation
   • label position and orientation
   • wire geometry
   • field/text placement when possible
5. Update logical fields such as value, footprint, part metadata, and generated properties.
6. If the code-generated netlist differs from the existing KiCad schematic netlist, do not silently overwrite the schematic. Instead, report a diff and require user action.

The matching identity could be something like:

RefDes + pin number + net name

or another stable internal identity if SKiDL already has a better model.

New parts could be placed in a staging area such as NEEDS_PLACEMENT. Deleted parts or changed pin-net connections could be reported as conflicts.
Ideally this could be exposed as something like:

generate_schematic(preserve_layout=True)

or as a separate reconciliation step:

existing.kicad_sch + generated canonical netlist -> merged.kicad_sch + diff report

Describe alternatives you've considered

Alternatives I have considered:

• Always regenerate the schematic from scratch. This is simple, but loses manual cleanup and makes generated schematics unpleasant for real debugging/review.
• Improve auto-placement and auto-routing heuristics only. This helps first-generation output, but still does not protect human edits.
• Treat generated SVG/PDF as the review artifact. This is not enough because engineers need an editable KiCad schematic.
• Build this as an external KiCad schematic reconciler library that SKiDL can call, rather than putting all merge logic in SKiDL core.

I am not sure whether this belongs in SKiDL core, a plugin, or an external helper library. I am opening this issue to ask about the preferred architecture and whether this workflow fits SKiDL's direction.

Additional context

This feature would make code-first hardware design feel closer to a practical workflow:

SKiDL code -> tested/generated schematic -> human-readable KiCad schematic -> PCB

rather than replacing the editable schematic with a one-time generated artifact.