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rk27load - fix indentation
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30460 a1c6a512-1295-4272-9138-f99709370657
1 parent 6d5671a commit 77a82ad

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4 files changed

+213
-210
lines changed

4 files changed

+213
-210
lines changed

‎utils/rk27utils/rk27load/stage1/main.S

+23-23
Original file line numberDiff line numberDiff line change
@@ -2,41 +2,41 @@
22
.global start
33

44
start:
5-
msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
5+
msr cpsr_c,#0xd3 /* enter supervisor mode, disable IRQ/FIQ */
66

77
pll_setup:
8-
mov r0, #0x18000000
9-
add r0, r0, #0x1c000
8+
mov r0,#0x18000000
9+
add r0,r0,#0x1c000
1010

1111
/* setup ARM core freq = 200MHz */
1212
/* AHB bus freq (HCLK) = 100MHz */
1313
/* APB bus freq (PCLK) = 50MHz */
14-
ldr r1, [r0,#0x14] /* SCU_DIVCON1 */
15-
orr r1, #9 /* ARM slow mode, HCLK:PCLK = 2:1 */
16-
str r1, [r0,#0x14]
14+
ldr r1,[r0,#0x14] /* SCU_DIVCON1 */
15+
orr r1,#9 /* ARM slow mode, HCLK:PCLK = 2:1 */
16+
str r1,[r0,#0x14]
1717

18-
ldr r1,=0x01970c70 /* (1<<24) | (1<<23) | (23<<16) | (199<<4) */
19-
str r1, [r0,#0x08]
18+
ldr r1,=0x01970c70 /* (1<<24) | (1<<23) | (23<<16) | (199<<4) */
19+
str r1,[r0,#0x08]
2020

21-
ldr r2,=0x40000
21+
ldr r2,=0x40000
2222
1:
23-
ldr r1, [r0,#0x2c] /* SCU_STATUS */
24-
tst r1, #1 /* ARM pll lock */
25-
bne 1f
26-
subs r2, #1
27-
bne 1b
23+
ldr r1,[r0,#0x2c] /* SCU_STATUS */
24+
tst r1,#1 /* ARM pll lock */
25+
bne 1f
26+
subs r2,#1
27+
bne 1b
2828
1:
29-
ldr r1, [r0,#0x14] /* SCU_DIVCON1 */
30-
bic r1, #5 /* leave ARM slow mode, ARMclk:HCLK = 2:1 */
31-
str r1, [r0,#0x14]
29+
ldr r1,[r0,#0x14] /* SCU_DIVCON1 */
30+
bic r1,#5 /* leave ARM slow mode, ARMclk:HCLK = 2:1 */
31+
str r1,[r0,#0x14]
3232

3333
sdram_config:
34-
add r0, r0, #0x94000 /* SDRAM base */
34+
add r0,r0, #0x94000 /* SDRAM base */
3535

36-
mov r1, #1
37-
str r1, [r0,#0x10c] /* MCSDR_BASIC Round-robin, SDRAM width 16bits */
36+
mov r1,#1
37+
str r1,[r0,#0x10c] /* MCSDR_BASIC Round-robin, SDRAM width 16bits */
3838

39-
add r1, #0x10
40-
str r1, [r0,#0x108] /* MCSDR_ADDCFG 12 bits row/9 bits col addr */
39+
add r1,#0x10
40+
str r1,[r0,#0x108] /* MCSDR_ADDCFG 12 bits row/9 bits col addr */
4141

42-
mov pc, lr /* we are done, return to bootrom code */
42+
mov pc,lr /* we are done, return to bootrom code */

‎utils/rk27utils/rk27load/stage2/crt0.S

+47-46
Original file line numberDiff line numberDiff line change
@@ -1,55 +1,56 @@
1-
//
2-
// startup code
3-
//
4-
//
1+
/*
2+
* startup code
3+
*
4+
*/
55

6-
#define PSR_MODE 0x0000001f
7-
#define PSR_USR_MODE 0x00000010
8-
#define PSR_IRQ_MODE 0x00000012
9-
#define PSR_SVC_MODE 0x00000013
6+
#define PSR_MODE 0x0000001f
7+
#define PSR_USR_MODE 0x00000010
8+
#define PSR_IRQ_MODE 0x00000012
9+
#define PSR_SVC_MODE 0x00000013
1010

11-
#define PSR_INT_MASK 0x000000c0
12-
#define PSR_FIQ_DIS 0x00000040
13-
#define PSR_IRQ_DIS 0x00000080
11+
#define PSR_INT_MASK 0x000000c0
12+
#define PSR_FIQ_DIS 0x00000040
13+
#define PSR_IRQ_DIS 0x00000080
1414

1515
.section .init.text,"ax",%progbits
1616
.global start
1717
.extern _interrupt_disable
1818

19-
// -----------------------------------------------------
20-
// startup code (setup stacks, branch to main)
21-
// -----------------------------------------------------
19+
/* -----------------------------------------------------
20+
* startup code (setup stacks, branch to main)
21+
* -----------------------------------------------------
22+
*/
2223
start:
23-
// setup IRQ stack
24-
mov r0, #(PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
25-
msr cpsr, r0
26-
ldr sp,=irqstackend
27-
28-
// setup SVC stack
29-
mov r0, #(PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
30-
msr cpsr, r0
31-
ldr sp,=stackend
32-
33-
// disbale interrupts
34-
mrs r0, cpsr
35-
orr r0, r0, #0xc0
36-
msr cpsr_c, r0
37-
38-
// remap
39-
mov r0, #0x18000000
40-
add r0, r0, #0x1C000
41-
ldr r1,=0xdeadbeef
42-
str r1, [r0, #4]
43-
44-
// relocate itself
45-
ldr r0,=_relocstart
46-
ldr r1,=_relocend
47-
ldr r2,=0x0
24+
/* setup IRQ stack */
25+
mov r0,#(PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
26+
msr cpsr,r0
27+
ldr sp,=irqstackend
28+
29+
/* setup SVC stack */
30+
mov r0,#(PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
31+
msr cpsr,r0
32+
ldr sp,=stackend
33+
34+
/* disbale interrupts */
35+
mrs r0,cpsr
36+
orr r0,r0,#0xc0
37+
msr cpsr_c, r0
38+
39+
/* remap */
40+
mov r0,#0x18000000
41+
add r0,r0,#0x1C000
42+
ldr r1,=0xdeadbeef
43+
str r1,[r0,#4]
44+
45+
/* relocate itself */
46+
ldr r0,=_relocstart
47+
ldr r1,=_relocend
48+
ldr r2,=0x0
4849
1:
49-
cmp r1,r0
50-
ldrhi r3,[r0],#4
51-
strhi r3,[r2],#4
52-
bhi 1b
53-
54-
// continue running in SVC (supervisor mode)
55-
ldr pc,=0x0
50+
cmp r1,r0
51+
ldrhi r3,[r0],#4
52+
strhi r3,[r2],#4
53+
bhi 1b
54+
55+
/* continue running in SVC (supervisor mode) */
56+
ldr pc,=0x0

‎utils/rk27utils/rk27load/stage2/irq.S

+71-72
Original file line numberDiff line numberDiff line change
@@ -1,103 +1,102 @@
1-
.section .text
2-
.align 4
1+
.section .text
2+
.align 4
33

4-
.global irq_handler
5-
#define BUFF_ADDR 0x60800000
4+
.global irq_handler
5+
#define BUFF_ADDR 0x60800000
66

77
irq_handler:
8-
stmfd sp!, {r0-r7, ip, lr}
8+
stmfd sp!,{r0-r7,ip,lr}
99

10-
// get interrupt number
11-
mov r4, #0x18000000
12-
add r4, r4, #0x80000
13-
ldr r5, [r4, #0x104]
14-
and r5, r5, #0x1f
15-
cmp r5, #0x10 // UDC interrupt
10+
/* get interrupt number */
11+
mov r4,#0x18000000
12+
add r4,r4,#0x80000
13+
ldr r5,[r4,#0x104]
14+
and r5,r5,#0x1f
15+
cmp r5,#0x10 /* UDC interrupt */
1616

17-
bleq udc_irq
17+
bleq udc_irq
1818

19-
// clear pending interrupt
20-
mov r3, #1
21-
mov r2, r3, LSL r5
22-
str r2, [r4, #0x118]
19+
/* clear pending interrupt */
20+
mov r3,#1
21+
mov r2,r3,LSL r5
22+
str r2,[r4,#0x118]
2323

24-
ldmfd sp!, {r0-r7, ip, lr}
25-
subs pc, lr, #4
24+
ldmfd sp!,{r0-r7,ip,lr}
25+
subs pc,lr,#4
2626

2727
udc_irq:
28-
stmfd sp!, {r4-r8, lr}
28+
stmfd sp!,{r4-r8,lr}
2929

30-
// handle usb interrupt
31-
ldr r4,=0x180A0000
32-
ldr r5, [r4, #0x18] // UDC_INTFLAG
30+
/* handle usb interrupt */
31+
ldr r4,=0x180A0000
32+
ldr r5,[r4,#0x18] /* UDC_INTFLAG */
3333

34-
// ep0 in intr
35-
tst r5, #0x04
36-
beq bulk_recv_intr
34+
/* ep0 in intr */
35+
tst r5,#0x04
36+
beq bulk_recv_intr
37+
ep0:
38+
ldr r5,[r4,#0x40]
39+
mov r5,r5,lsr #10
40+
mov r5,r5,lsl #10 /* clear lower 10 bits in TX0STAT */
41+
str r5,[r4,#0x40]
3742

38-
// write_reg32(UDC_TX0STAT, read_reg32(UDC_TX0STAT) & ~0x7FF);
39-
ldr r5, [r4, #0x40]
40-
mov r5, r5, lsr #10
41-
mov r5, r5, lsl #10 // clear clower 10 bits
42-
str r5, [r4, #0x40]
43+
/* set buffer addres in UDC_DMA0LM_OADDR */
44+
mov r5,#0x60000000
45+
str r5,[r4, #0x3c]
4346

44-
// write_reg32(UDC_DMA0LM_OADDR, (uint32_t)(state.ctrlep_data));
45-
mov r5, #0x60000000
46-
str r5, [r4, #0x3c]
47+
/* write DMA_START in UDC_DMA0CTLO */
48+
mov r5,#1
49+
str r5,[r4,#0x38]
4750

48-
// write_reg32(UDC_DMA0CTLO, read_reg32(UDC_DMA0CTLO) | ENP_DMA_START);
49-
mov r5, #1
50-
str r5, [r4, #0x38]
51+
ldmfd sp!,{r4-r8,pc}
5152

52-
ldmfd sp!, {r4-r8, pc}
53-
54-
// bulk out interrupt
53+
/* bulk out interrupt */
5554
bulk_recv_intr:
56-
tst r5, #0x100
57-
ldmeqfd sp!, {r4-r8, pc}
55+
tst r5,#0x100
56+
ldmeqfd sp!,{r4-r8,pc}
5857

59-
// read UDC_RX1STAT
60-
ldr r5, [r4, #0x54]
61-
mov r5, r5, lsl #21
62-
mov r5, r5, lsr #21 // r5 = length
58+
/* read UDC_RX1STAT */
59+
ldr r5,[r4,#0x54]
60+
mov r5,r5,lsl #21
61+
mov r5,r5,lsr #21 /* r5 = length */
6362

64-
ldr r6,=usb_sz
65-
ldr r6, [r6]
66-
ldr r7, [r6] // r7 = total_code_length expected
63+
ldr r6,=usb_sz
64+
ldr r6,[r6]
65+
ldr r7,[r6] /* r7 = total_code_length expected */
6766

68-
subs r7, r7, r5
69-
bne usb_bulk_out1_recv
67+
subs r7,r7,r5
68+
bne usb_bulk_out1_recv
7069

71-
// copy from buff to the begining of the ram
72-
ldr r0,=BUFF_ADDR
73-
ldr r1,[r0,#-4] // size
70+
/* copy from buff to the begining of the ram */
71+
ldr r0,=BUFF_ADDR
72+
ldr r1,[r0,#-4] /* size */
7473

75-
ldr r1,=0x800000 // buffer size
74+
ldr r1,=0x800000 /* buffer size */
7675

77-
add r1,r1,r0 // end address
78-
ldr r2,=0x60000000 // destination
76+
add r1,r1,r0 /* end address */
77+
ldr r2,=0x60000000 /* destination */
7978
1:
80-
cmp r1,r0
81-
ldrhi r3,[r0],#4
82-
strhi r3,[r2],#4
83-
bhi 1b
79+
cmp r1,r0
80+
ldrhi r3,[r0],#4
81+
strhi r3,[r2],#4
82+
bhi 1b
8483

85-
// execute user code
86-
ldr r0,=0x60000000
87-
bx r0 // jump to 0x60000000
84+
/* execute user code */
85+
ldr r0,=0x60000000
86+
bx r0 /* jump to 0x60000000 */
8887

8988
usb_bulk_out1_recv:
90-
str r7, [r6] // size = size - received
89+
str r7,[r6] /* size = size - received */
9190

92-
ldr r6,=usb_write_addr
93-
ldr r7, [r6]
91+
ldr r6,=usb_write_addr
92+
ldr r7,[r6]
9493

95-
add r7, r7, r5
96-
str r7, [r6] // usb_write_addr += length
94+
add r7,r7,r5
95+
str r7,[r6] /* usb_write_addr += length */
9796

98-
str r7, [r4, #0x60] // DMA1LM_OADDR = usb_write_addr
97+
str r7,[r4,#0x60] /* DMA1LM_OADDR = usb_write_addr */
9998

100-
mov r5, #1
101-
str r5, [r4, #0x5c] // DMA1_CTL0 = ENP_DMA_START
99+
mov r5,#1
100+
str r5,[r4,#0x5c] /* DMA1_CTL0 = ENP_DMA_START */
102101

103-
ldmfd sp!, {r4-r8, pc}
102+
ldmfd sp!,{r4-r8,pc}

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