[RISC-V] Eliminate unnecessary add instruction in array indirection

[fuad1502]

RISC-V supports the following addressing mode: [reg] & [reg + imm].

genCreateAddrMode already supports constant determination, however, it's currently only enabled for XARCH.

Additionally, I disabled scale extraction for RISC-V.

Before patch:

slli           a1, a1, 2
addi           a1, a1, 16
add            t6, a0, a1
lw             a0, 0(t6)

After patch applied:

slli           a1, a1, 2
add            a2, a0, a1
lw             a0, 16(a2)

See related discussion here: #112917

Part of #84834, cc @dotnet/samsung

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[risc-vv]

RISC-V Release-CLR-VF2: 9463 / 9539 (99.20%)

=======================
      passed: 9463
      failed: 59
     skipped: 106
      killed: 17
------------------------
  TOTAL libs: 9645
 TOTAL tests: 9645
   REAL time: 2h 7min 36s 603ms
=======================

Release-CLR-VF2.md, Release-CLR-VF2.xml, testclr_output.tar.gz

Build information and commands

GIT: d440f302599a871438c1b29761ec39c7b763dd0d
CI: a8426a46d8575dfcb3b5fec0d7d0b7a7c118d690
REPO: fuad1502/runtime
BRANCH: riscv-jit-opt/index-addr-opt
CONFIG: Release
LIB_CONFIG: Release

RISC-V Release-CLR-QEMU: 9463 / 9539 (99.20%)

=======================
      passed: 9463
      failed: 59
     skipped: 106
      killed: 17
------------------------
  TOTAL libs: 9645
 TOTAL tests: 9645
   REAL time: 2h 46min 10s 569ms
=======================

Release-CLR-QEMU.md, Release-CLR-QEMU.xml, testclr_output.tar.gz

Build information and commands

GIT: d440f302599a871438c1b29761ec39c7b763dd0d
CI: a8426a46d8575dfcb3b5fec0d7d0b7a7c118d690
REPO: fuad1502/runtime
BRANCH: riscv-jit-opt/index-addr-opt
CONFIG: Release
LIB_CONFIG: Release

RISC-V Release-FX-VF2: 398096 / 441821 (90.10%)

=======================
      passed: 398096
      failed: 160
     skipped: 1413
      killed: 43565
------------------------
  TOTAL libs: 258
 TOTAL tests: 443234
   REAL time: 2h 44min 46s 617ms
=======================

Release-FX-VF2.md, Release-FX-VF2.xml, testfx_output.tar.gz

Build information and commands

GIT: d440f302599a871438c1b29761ec39c7b763dd0d
CI: a8426a46d8575dfcb3b5fec0d7d0b7a7c118d690
REPO: fuad1502/runtime
BRANCH: riscv-jit-opt/index-addr-opt
CONFIG: Release
LIB_CONFIG: Release

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[jakobbotsch]

This ifdef looks unnecessary to me. jitIsScaleIndexMul always returns false for RISCV64.

[fuad1502]

Ah yes. Removed in 219a018

[jakobbotsch]

Can you please share the jitdump of the IR node that this helps with? It does not look right to me that you need to enable x64-enabled-only paths for RISCV64. That probably means the change should be made elsewhere, given that the cases are handled just fine for ARM64 with more general address modes.

[jakobbotsch]

This ifdef also looks unnecessary.

[fuad1502]

Updated in 219a018

[risc-vv]

219a018 is being scheduled for building and testing

GIT: 219a0180e8b9e2558988b0a044e5fc2e5f8e9c9c
REPO: dotnet/runtime
BRANCH: main