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JIT: Fix illegal instruction encoding for float->float casts #112217

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merged 2 commits into from
Feb 14, 2025
Merged

JIT: Fix illegal instruction encoding for float->float casts #112217

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5582d1e
fix illegal instruction encoding for floating->floating casts
saucecontrol Feb 6, 2025
fecb223
remove path-based trigger for jitstress-isas-avx512 pipeline
saucecontrol Feb 6, 2025
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14 changes: 0 additions & 14 deletions eng/pipelines/coreclr/jitstress-isas-avx512.yml
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Original file line number Diff line number Diff line change
@@ -1,20 +1,6 @@
# This pipeline only runs on GitHub PRs, not on merges.
trigger: none

# Only run on specific changes to the JIT directory that are likely to affect AVX-512.
pr:
branches:
include:
- main
paths:
include:
- src/coreclr/jit/hwintrinsiccodegenxarch.cpp
- src/coreclr/jit/hwintrinsiclistxarch.h
- src/coreclr/jit/hwintrinsicxarch.cpp
- src/coreclr/jit/instrsxarch.h
- src/coreclr/jit/emitxarch.cpp
- src/coreclr/jit/emitxarch.h

schedules:
- cron: "30 19 * * 6"
displayName: Sat at 11:30 AM (UTC-8:00)
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13 changes: 9 additions & 4 deletions src/coreclr/jit/codegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7234,11 +7234,16 @@ void CodeGen::genFloatToFloatCast(GenTree* treeNode)
assert(varTypeIsFloating(srcType) && varTypeIsFloating(dstType));

genConsumeOperands(treeNode->AsOp());
if (srcType == dstType && (op1->isUsedFromReg() && (targetReg == op1->GetRegNum())))
if (srcType == dstType)
{
// source and destinations types are the same and also reside in the same register.
// we just need to consume and produce the reg in this case.
;
if (op1->isUsedFromReg())
{
GetEmitter()->emitIns_Mov(INS_movaps, EA_16BYTE, targetReg, op1->GetRegNum(), /* canSkip */ true);
}
else
{
inst_RV_TT(ins_Move_Extend(dstType, /* srcInReg */ false), emitTypeSize(dstType), targetReg, op1);
}
}
else
{
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4 changes: 0 additions & 4 deletions src/coreclr/jit/instr.cpp
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Expand Up @@ -2477,8 +2477,6 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from)
return INS_cvttss2si32;
case TYP_LONG:
return INS_cvttss2si64;
case TYP_FLOAT:
return ins_Move_Extend(TYP_FLOAT, false);
case TYP_DOUBLE:
return INS_cvtss2sd;
case TYP_ULONG:
Expand All @@ -2499,8 +2497,6 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from)
return INS_cvttsd2si64;
case TYP_FLOAT:
return INS_cvtsd2ss;
case TYP_DOUBLE:
return ins_Move_Extend(TYP_DOUBLE, false);
case TYP_ULONG:
return INS_vcvttsd2usi64;
case TYP_UINT:
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