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[RISC-V] Eliminate unnecessary add instruction in array indirection #112978

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16 changes: 12 additions & 4 deletions src/coreclr/jit/codegencommon.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1119,6 +1119,11 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,
[reg1 + reg2]
[reg1 + reg2 * natural-scale]

The following indirections are valid address modes on riscv64:

[reg]
[reg + icon]

*/

/* All indirect address modes require the address to be an addition */
Expand Down Expand Up @@ -1269,7 +1274,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,

switch (op1->gtOper)
{
#ifdef TARGET_XARCH
#if defined(TARGET_XARCH) || defined(TARGET_RISCV64)
// TODO-ARM-CQ: For now we don't try to create a scaled index.
case GT_ADD:

Expand All @@ -1291,7 +1296,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,
}
}
break;
#endif // TARGET_XARCH
#endif // TARGET_XARCH || TARGET_RISCV64

case GT_MUL:

Expand Down Expand Up @@ -1347,7 +1352,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,
noway_assert(op2);
switch (op2->gtOper)
{
#ifdef TARGET_XARCH
#if defined(TARGET_XARCH) || defined(TARGET_RISCV64)
// TODO-ARM64-CQ, TODO-ARM-CQ: For now we only handle MUL and LSH because
// arm doesn't support both scale and offset at the same. Offset is handled
// at the emitter as a peephole optimization.
Expand All @@ -1370,7 +1375,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,
}
}
break;
#endif // TARGET_XARCH
#endif // TARGET_XARCH || TARGET_RISCV64

case GT_MUL:

Expand Down Expand Up @@ -1428,6 +1433,9 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,
#endif

FOUND_AM:
#ifdef TARGET_RISCV64
assert(mul == 0 || mul == 1);
#endif

if (rv2)
{
Expand Down