Error of missing module and re-definition

[AyaseErii]

Hello, I am trying to run the design of caravel-OpenFPGA-EF but I cannot synthesize the design, and it shows the error message below:

13. Executing Verilog-2005 frontend: /openlane/designs/user_project_wrapper/src/sub_module/user_project_wrapper.v
/openlane/designs/user_project_wrapper/src/sub_module/user_project_wrapper.v:31: ERROR: Re-definition of module `\user_project_wrapper'!
child process exited abnormally

I realized the user_project_wrapper module has been redefined in the /sub_module/user_project_wrapper.v so I just remove the file, and ran the OpenLane again, but the error come out as following:

39.1. Analyzing design hierarchy..
ERROR: Module `\sky130_fd_sc_hd__ebufn_4' referenced in module `\user_project_wrapper' in cell `\FPGA2SOC_OUT_31_DEMUX_LA' is not part of the design.

I put the design .v files in the user_project_wrapper as shown the screenshots

OpenLane example files can work perfectly. I have been stuck due to this error for a long time but I still cannot find out what is wrong. Could anyone point me to the right direction to solve this issue? I will appreciate it!

Thanks!