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fernvale-clockgate.h
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#ifndef __FV_CLOCKGATE_H__
#define __FV_CLOCKGATE_H__
// Clock gates are modifiable only via _SET and _CLEAR methods.
// Don't try writing to the clockgate register itself!
// control set 0
#define CLKGATE_SYS_CTL0 (0xA0010000 + 0x0300)
#define CLKGATE_SYS_CTL0_SET (0xA0010000 + 0x0310) // turns the block off
#define CLKGATE_SYS_CTL0_CLR (0xA0010000 + 0x0320) // turns the block on
#define CLKGATE_CTL0_LCD 0x0001
#define CLKGATE_CTL0_RESIZER 0x0002
#define CLKGATE_CTL0_ROTDMA 0x0004
#define CLKGATE_CTL0_CAM_BCLK 0x0008
#define CLKGATE_CTL0_PAD2CAM 0x0010
#define CLKGATE_CTL0_G2D 0x0020
#define CLKGATE_CTL0_MM_COLOR 0x0040
#define CLKGATE_CTL0_SLCD 0x0080
#define CLKGATE_CTL0_MD2G_26M 0x0100
#define CLKGATE_CTL0_BT_26M 0x0200
#define CLKGATE_CTL0_CAM_48M 0x0400
#define CLKGATE_CTL0_DMA2SFC 0x0800
#define CLKGATE_CTL0_2GDMA2SFC 0x1000
#define CLKGATE_CTL0_BT_BUS 0x2000
#define CLKGATE_CTL0_BT_ARM7 0x8000
// control set 1
#define CLKGATE_SYS_CTL1 (0xA0010000 + 0x0304)
#define CLKGATE_SYS_CTL1_SET (0xA0010000 + 0x0314)
#define CLKGATE_SYS_CTL2_CLR (0xA0010000 + 0x0328)
#define CLKGATE_CTL1_SEJ 0x0001
#define CLKGATE_CTL1_DMA 0x0002
#define CLKGATE_CTL1_USB 0x0004
#define CLKGATE_CTL1_MSDC 0x0008
#define CLKGATE_CTL1_SIM 0x0010
#define CLKGATE_CTL1_SIM2 0x0020
#define CLKGATE_CTL1_I2C 0x0040
#define CLKGATE_CTL1_SPI 0x0080
#define CLKGATE_CTL1_OSTIMER 0x0100
#define CLKGATE_CTL1_HIF1 0x0200
#define CLKGATE_CTL1_UART1 0x2000
#define CLKGATE_CTL1_UART2 0x4000
// control set 2
#define CLKGATE_SYS_CTL2 (0xA0010000 + 0x0308)
#define CLKGATE_SYS_CTL2_SET (0xA0010000 + 0x0318)
#define CLKGATE_SYS_CTL1_CLR (0xA0010000 + 0x0324)
#define CLKGATE_CTL2_PWM 0x0001
#define CLKGATE_CTL2_BTIF 0x0002
#define CLKGATE_CTL2_GPT 0x0004
#define CLKGATE_CTL2_AUXADC 0x0008
#define CLKGATE_CTL2_LZMA 0x0010
#define CLKGATE_CTL2_ROM 0x0020
#define CLKGATE_CTL2_EFUSE 0x0040
#define CLKGATE_CTL2_SW_LPM 0x0080
#define CLKGATE_CTL2_NFI 0x0200
#define CLKGATE_CTL2_MSDC2 0x0400
#define CLKGATE_CTL2_SFC 0x0800
#define CLKGATE_CTL2_SPI_NAND 0x1000
#define CLKGATE_CTL2_FM_F26M 0x2000
#define CLKGATE_CTL2_FM_BCLK 0x4000
/* Audio */
#define CLKGATE_AUDIO_CG_CTL0 (0x82C00000+0x0000)
#define CLKGATE_AUDIO_CG_CTL2 (0x82C00000+0x0008)
#define CLKGATE_AUDIO_CG_CTL4 (0x82C00000+0x0030)
#define CLKGATE_AUDIO_CG_CTL0_SET (0x82C00000+0x0010)
#define CLKGATE_AUDIO_CG_CTL2_SET (0x82C00000+0x0018)
#define CLKGATE_AUDIO_CG_CTL4_SET (0x82C00000+0x0034)
#define CLKGATE_AUDIO_CG_CTL0_CLR (0x82C00000+0x0020)
#define CLKGATE_AUDIO_CG_CTL2_CLR (0x82C00000+0x0028)
#define CLKGATE_AUDIO_CG_CTL4_CLR (0x82C00000+0x0038)
#define AUDIO_CG_CTL0_GCC 0x0002
#define AUDIO_CG_CTL0_IRDMA 0x0040
#define AUDIO_CG_CTL0_RXBUF 0x0100
#define AUDIO_CG_CTL0_TXBUF 0x0200
#define AUDIO_CG_CTL0_IRDBG 0x2000
#define AUDIO_CG_CTL0_AHB2DSPIO 0x8000
#define AUDIO_CG_CTL2_APC_PRE 0x0020
#define AUDIO_CG_CTL2_VAFE 0x0100
#define AUDIO_CG_CTL2_BFE 0x0200
#define AUDIO_CG_CTL4_APC 0x0020
#define AUDIO_CG_CTL4_VAFE 0x0100
#define AUDIO_CG_CTL4_BFE 0x0200
/* Analog */
#define CLKGATE_ANALOG_CLK_CTL0 (0xA0730000+0x0008)
#define CLKGATE_ANALOG_CLK_SET0 (0xA0730000+0x000C)
#define CLKGATE_ANALOG_CLK_CLR0 (0xA0730000+0x0010)
#define CLKGATE_ANALOG_CTL0_PWM2 0x0002
#define CLKGATE_ANALOG_CTL0_PWM3 0x0001
#define CLKGATE_ANALOG_CTL0_AUXADC_BCLK 0x0004
#define CLKGATE_ANALOG_CTL0_TP_BCLK 0x0008
#define CLKGATE_ANALOG_CTL0_PMU_F26M 0x0010
/* Multimedia (?) */
#define CLKGATE_MULTIMEDIA_CG_CTL CLKGATE_SYS_CTL0
#define CLKGATE_MULTIMEDIA_CG_SET CLKGATE_SYS_CTL0_SET
#define CLKGATE_MULTIMEDIA_CG_CLR CLKGATE_SYS_CTL0_CLR
#define MULTIMEDIA_CG_CTL_G2D CLKGATE_CTL0_SW_G2D
#define MULTIMEDIA_CG_CTL_LCD CLKGATE_CTL0_SW_LCD
#define MULTIMEDIA_CG_CTL_MM_COLOR CLKGATE_CTL0_SW_MM_COLOR
/* GSM Modem */
#define CLKGATE_MODEMGSM_CG_CTL2 (0x83000000+0x0008)
#define CLKGATE_MODEMGSM_CG_CTL4 (0x83000000+0x0088)
#define CLKGATE_MODEMGSM_CG_SET2 (0x83000000+0x0028)
#define CLKGATE_MODEMGSM_CG_SET4 (0x83000000+0x00A8)
#define CLKGATE_MODEMGSM_CG_CLR2 (0x83000000+0x0018)
#define CLKGATE_MODEMGSM_CG_CLR4 (0x83000000+0x0098)
#define MODEMGSM_CG_CTL2_TDMA 0x0001
#define MODEMGSM_CG_CTL2_BSI_T 0x0004
#define MODEMGSM_CG_CTL2_BPI_T 0x0008
#define MODEMGSM_CG_CTL2_DIV 0x0800
#define MODEMGSM_CG_CTL2_FCS 0x1000
#define MODEMGSM_CG_CTL2_GCU 0x2000
#define MODEMGSM_CG_CTL4_BSI 0x0004
#define MODEMGSM_CG_CTL4_BPI 0x0008
#endif /* __FV_CLOCKGATE_H__ */