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| 1 | +#ifndef __FV_USB_H__ |
| 2 | +#define __FV_USB_H__ |
| 3 | + |
| 4 | +#define USB_CTRL_ADDR 0xa0900000 |
| 5 | + |
| 6 | +#define USB_CTRL_FADDR (USB_CTRL_ADDR + 0x00) |
| 7 | + |
| 8 | +#define USB_CTRL_POWER (USB_CTRL_ADDR + 0x01) |
| 9 | +#define USB_CTRL_POWER_SUSPENAB (1 << 0) |
| 10 | +#define USB_CTRL_POWER_SUSPMODE (1 << 1) |
| 11 | +#define USB_CTRL_POWER_RESUME (1 << 2) |
| 12 | +#define USB_CTRL_POWER_RESET (1 << 3) |
| 13 | +#define USB_CTRL_POWER_SWRSTENAB (1 << 4) |
| 14 | +#define USB_CTRL_POWER_ISOUPDATE (1 << 7) |
| 15 | + |
| 16 | +#define USB_CTRL_INTRIN (USB_CTRL_ADDR + 0x02) |
| 17 | +#define USB_CTRL_INTRIN_EP0 (1 << 0) |
| 18 | +#define USB_CTRL_INTRIN_EP1_IN (1 << 1) |
| 19 | +#define USB_CTRL_INTRIN_EP2_IN (1 << 2) |
| 20 | +#define USB_CTRL_INTRIN_EP3_IN (1 << 3) |
| 21 | +#define USB_CTRL_INTRIN_EP4_IN (1 << 4) |
| 22 | + |
| 23 | +#define USB_CTRL_INTROUT (USB_CTRL_ADDR + 0x04) |
| 24 | +#define USB_CTRL_INTROUT_EP1_OUT (1 << 1) |
| 25 | +#define USB_CTRL_INTROUT_EP2_OUT (1 << 2) |
| 26 | + |
| 27 | +#define USB_CTRL_INTRUSB (USB_CTRL_ADDR + 0x06) |
| 28 | +#define USB_CTRL_INTRUSB_SUSPEND (1 << 0) |
| 29 | +#define USB_CTRL_INTRUSB_RESUME (1 << 1) |
| 30 | +#define USB_CTRL_INTRUSB_RESET (1 << 2) |
| 31 | +#define USB_CTRL_INTRUSB_SOF (1 << 3) |
| 32 | +#define USB_CTRL_INTRUSB_POWERDWN (1 << 4) |
| 33 | + |
| 34 | +/* IN interrupt enable */ |
| 35 | +#define USB_CTRL_INTRINE (USB_CTRL_ADDR + 0x07) |
| 36 | +#define USB_CTRL_INTRINE_EP0_ENABLE (1 << 0) |
| 37 | +#define USB_CTRL_INTRINE_EP1_IN_ENABLE (1 << 1) |
| 38 | +#define USB_CTRL_INTRINE_EP2_IN_ENABLE (1 << 2) |
| 39 | +#define USB_CTRL_INTRINE_EP3_IN_ENABLE (1 << 3) |
| 40 | +#define USB_CTRL_INTRINE_EP4_IN_ENABLE (1 << 4) |
| 41 | + |
| 42 | +#define USB_CTRL_INTROUTE (USB_CTRL_ADDR + 0x09) |
| 43 | +#define USB_CTRL_INTROUTE_EP1_OUT_ENABLE (1 << 1) |
| 44 | +#define USB_CTRL_INTROUTE_EP2_OUT_ENABLE (1 << 2) |
| 45 | + |
| 46 | +#define USB_CTRL_INTRUSBE (USB_CTRL_ADDR + 0x0b) |
| 47 | +#define USB_CTRL_INTRUSBE_SUSPEND_ENABLE (1 << 0) |
| 48 | +#define USB_CTRL_INTRUSBE_RESUME_ENABLE (1 << 1) |
| 49 | +#define USB_CTRL_INTRUSBE_RESET_ENABLE (1 << 2) |
| 50 | +#define USB_CTRL_INTRUSBE_SOF_ENABLE (1 << 3) |
| 51 | +#define USB_CTRL_INTRUSBE_POWERDWN_ENABLE (1 << 4) |
| 52 | + |
| 53 | +#define USB_CTRL_FRAME_COUNT1 (USB_CTRL_ADDR + 0x0c) |
| 54 | +#define USB_CTRL_FRAME_COUNT2 (USB_CTRL_ADDR + 0x0d) |
| 55 | + |
| 56 | +#define USB_CTRL_INDEX (USB_CTRL_ADDR + 0x0e) |
| 57 | +#define USB_CTRL_RSTCTRL (USB_CTRL_ADDR + 0x0f) |
| 58 | + |
| 59 | +#define USB_CTRL_EP_INMAXP (USB_CTRL_ADDR + 0x10) |
| 60 | + |
| 61 | +#define USB_CTRL_EP0_CSR (USB_CTRL_ADDR + 0x11) |
| 62 | +#define USB_CTRL_EP0_CSR_OUTPKTRDY (1 << 0) |
| 63 | +#define USB_CTRL_EP0_CSR_INPKTRDY (1 << 1) |
| 64 | +#define USB_CTRL_EP0_CSR_SENTSTALL (1 << 2) |
| 65 | +#define USB_CTRL_EP0_CSR_DATAEND (1 << 3) |
| 66 | +#define USB_CTRL_EP0_CSR_SETUPEND (1 << 4) |
| 67 | +#define USB_CTRL_EP0_CSR_SENDSTALL (1 << 5) |
| 68 | +#define USB_CTRL_EP0_CSR_SOUTPKTRDY (1 << 6) |
| 69 | +#define USB_CTRL_EP0_CSR_SSETUPEND (1 << 7) |
| 70 | + |
| 71 | +#define USB_CTRL_EP_INCSR1 (USB_CTRL_ADDR + 0x11) |
| 72 | +#define USB_CTRL_EP_INCSR1_INPKTRDY (1 << 0) |
| 73 | +#define USB_CTRL_EP_INCSR1_FIFONOTEMPTY (1 << 1) |
| 74 | +#define USB_CTRL_EP_INCSR1_UNDERRUN (1 << 2) |
| 75 | +#define USB_CTRL_EP_INCSR1_FLUSHFIFO (1 << 3) |
| 76 | +#define USB_CTRL_EP_INCSR1_SENDSTALL (1 << 4) |
| 77 | +#define USB_CTRL_EP_INCSR1_SENTSTALL (1 << 5) |
| 78 | +#define USB_CTRL_EP_INCSR1_CLRDATATOG (1 << 6) |
| 79 | +#define USB_CTRL_EP_INCSR1_ABORTPKT_ENABLE (1 << 7) |
| 80 | + |
| 81 | +#define USB_CTRL_EP_INCSR2 (USB_CTRL_ADDR + 0x12) |
| 82 | +#define USB_CTRL_EP_INCSR2_FRCDATATOG (1 << 3) |
| 83 | +#define USB_CTRL_EP_INCSR2_DMAENAB (1 << 4) |
| 84 | +#define USB_CTRL_EP_INCSR2_MODE (1 << 5) |
| 85 | +#define USB_CTRL_EP_INCSR2_ISO (1 << 6) |
| 86 | +#define USB_CTRL_EP_INCSR2_AUTOSET (1 << 7) |
| 87 | + |
| 88 | +#define USB_CTRL_EP_OUTMAXP (USB_CTRL_ADDR + 0x13) |
| 89 | + |
| 90 | +#define USB_CTRL_EP_OUTCSR1 (USB_CTRL_ADDR + 0x14) |
| 91 | +#define USB_CTRL_EP_OUTCSR1_RXPKTRDY (1 << 0) |
| 92 | +#define USB_CTRL_EP_OUTCSR1_FIFOFULL (1 << 1) |
| 93 | +#define USB_CTRL_EP_OUTCSR1_OVERRUN (1 << 2) |
| 94 | +#define USB_CTRL_EP_OUTCSR1_DATAERROR (1 << 3) |
| 95 | +#define USB_CTRL_EP_OUTCSR1_FLUSHFIFO (1 << 4) |
| 96 | +#define USB_CTRL_EP_OUTCSR1_SENDSTALL (1 << 5) |
| 97 | +#define USB_CTRL_EP_OUTCSR1_SENTSTALL (1 << 6) |
| 98 | +#define USB_CTRL_EP_OUTCSR1_CLRDTATOG (1 << 7) |
| 99 | + |
| 100 | +#define USB_CTRL_EP_OUTCSR2 (USB_CTRL_ADDR + 0x15) |
| 101 | +#define USB_CTRL_EP_OUTCSR2_DMAMODE (1 << 4) |
| 102 | +#define USB_CTRL_EP_OUTCSR2_DMAENAB (1 << 5) |
| 103 | +#define USB_CTRL_EP_OUTCSR2_ISO (1 << 6) |
| 104 | +#define USB_CTRL_EP_OUTCSR2_AUTOCLEAR (1 << 7) |
| 105 | + |
| 106 | +#define USB_CTRL_EP0_COUNT (USB_CTRL_ADDR + 0x16) |
| 107 | + |
| 108 | +#define USB_CTRL_EP_COUNT1 (USB_CTRL_ADDR + 0x16) |
| 109 | + |
| 110 | +#define USB_CTRL_EP_COUNT2 (USB_CTRL_ADDR + 0x17) |
| 111 | + |
| 112 | +#define USB_CTRL_EP0_FIFO_DB0 (USB_CTRL_ADDR + 0x20) |
| 113 | +#define USB_CTRL_EP0_FIFO_DB1 (USB_CTRL_ADDR + 0x21) |
| 114 | +#define USB_CTRL_EP0_FIFO_DB2 (USB_CTRL_ADDR + 0x22) |
| 115 | +#define USB_CTRL_EP0_FIFO_DB3 (USB_CTRL_ADDR + 0x23) |
| 116 | + |
| 117 | +#define USB_CTRL_EP1_FIFO_DB0 (USB_CTRL_ADDR + 0x24) |
| 118 | +#define USB_CTRL_EP1_FIFO_DB1 (USB_CTRL_ADDR + 0x25) |
| 119 | +#define USB_CTRL_EP1_FIFO_DB2 (USB_CTRL_ADDR + 0x26) |
| 120 | +#define USB_CTRL_EP1_FIFO_DB3 (USB_CTRL_ADDR + 0x27) |
| 121 | + |
| 122 | +#define USB_CTRL_EP2_FIFO_DB0 (USB_CTRL_ADDR + 0x28) |
| 123 | +#define USB_CTRL_EP2_FIFO_DB1 (USB_CTRL_ADDR + 0x29) |
| 124 | +#define USB_CTRL_EP2_FIFO_DB2 (USB_CTRL_ADDR + 0x2a) |
| 125 | +#define USB_CTRL_EP2_FIFO_DB3 (USB_CTRL_ADDR + 0x2b) |
| 126 | + |
| 127 | +#define USB_CTRL_EP3_FIFO_DB0 (USB_CTRL_ADDR + 0x2c) |
| 128 | +#define USB_CTRL_EP3_FIFO_DB1 (USB_CTRL_ADDR + 0x2d) |
| 129 | +#define USB_CTRL_EP3_FIFO_DB2 (USB_CTRL_ADDR + 0x2e) |
| 130 | +#define USB_CTRL_EP3_FIFO_DB3 (USB_CTRL_ADDR + 0x2f) |
| 131 | + |
| 132 | +#define USB_CTRL_EP4_FIFO_DB0 (USB_CTRL_ADDR + 0x30) |
| 133 | +#define USB_CTRL_EP4_FIFO_DB1 (USB_CTRL_ADDR + 0x31) |
| 134 | +#define USB_CTRL_EP4_FIFO_DB2 (USB_CTRL_ADDR + 0x32) |
| 135 | +#define USB_CTRL_EP4_FIFO_DB3 (USB_CTRL_ADDR + 0x33) |
| 136 | + |
| 137 | +#define USB_CTRL_CON (USB_CTRL_ADDR + 0x240) |
| 138 | +/* Enable 1.5k pullup on D+ pin */ |
| 139 | +#define USB_CTRL_CON_DPPULLUP (1 << 0) |
| 140 | +/* Enable 1.5k pullup on D- pin */ |
| 141 | +#define USB_CTRL_CON_DNPULLUP (1 << 1) |
| 142 | +/* Don't issue a DMA request when a null packet is received */ |
| 143 | +#define USB_CTRL_CON_NULLPKT_FIX (1 << 5) |
| 144 | + |
| 145 | +#endif /* __FV_USB_H__ */ |
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