Latency Insensitive Design Webinar

This repository will host slides and support code for the webinar "Latency Insensitive Design: Theoretical and Practical Considerations".

Webinar abstract

This webinar will explore Latency Insenstive Design, a design paradigm for FPGAs and ASICs aiming to tackle issues associated with modern, larger dies (long distance interconnect delays), as well as digital designs with growing levels of complexity (synchronization, high coupling). We will explain various approaches and give infrastructure and system design examples, focusing particularly on the case of AXI4-Stream.

• History of LID and theoretical aspects
• AXI4-Stream protocol rules and waveforms
• AXI4-Stream infrastructure: skid buffers, FIFOs, parallelism converters, gearboxes, crossbars, NoCs
• System design using datapath examples
• Code examples in SystemVerilog