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Commit bd610b2

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author
ferhatyaman
committed
with branch but does not work
1 parent 9d8c8e4 commit bd610b2

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2 files changed

+55
-5
lines changed

2 files changed

+55
-5
lines changed

Architecture.py

Lines changed: 53 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -229,8 +229,10 @@ def issue(self):
229229
else:
230230
return
231231
elif next_inst.op == 'BGE':
232-
# TODO: Branch Prediction Yapman lazım
233-
pass
232+
if self.RS.is_available(next_inst.op):
233+
inst_id, inst = self.IQ.dequeue()
234+
else:
235+
return
234236
else:
235237
if self.RS.is_available(next_inst.op):
236238
inst_id, inst = self.IQ.dequeue()
@@ -248,9 +250,7 @@ def issue(self):
248250

249251
# Case of Branch
250252
# Branch Prediction
251-
if inst.op.startswith('B'):
252-
pass
253-
elif inst.op == 'LD':
253+
if inst.op == 'LD':
254254
if Instruction.is_operand_reg(inst.s1):
255255
if self.RF.is_available(inst.s1):
256256
rob_s1 = self.ROB.getby_reg(inst.s1)
@@ -267,6 +267,52 @@ def issue(self):
267267
else:
268268
rs.vj = int(inst.s1)
269269
rs.qj = ''
270+
elif inst.op == 'BGE':
271+
if Instruction.is_operand_reg(inst.d):
272+
if not self.RF[inst.d].busy:
273+
rob_d = self.ROB.getby_reg(inst.d)
274+
if rob_d is not None:
275+
if rob_d.ready:
276+
rs.vj = rob_d.value
277+
rs.qj = ''
278+
else:
279+
rs.qj = rob_d.name
280+
else:
281+
rs.vj = self.RF[inst.d].value
282+
rs.qj = ''
283+
else:
284+
rob_d = self.ROB.getby_reg(inst.d)
285+
if rob_d.name == self.RF[inst.d].reorder:
286+
rs.qj = rob_d.name
287+
else:
288+
rs.vj = self.RF[inst.d].value
289+
rs.qj = ''
290+
else:
291+
rs.vj = int(inst.d)
292+
rs.qj = ''
293+
294+
if Instruction.is_operand_reg(inst.s1):
295+
if not self.RF[inst.s1].busy:
296+
rob_s1 = self.ROB.getby_reg(inst.s1)
297+
if rob_s1 is not None:
298+
if rob_s1.ready:
299+
rs.vk = rob_s1.value
300+
rs.qk = ''
301+
else:
302+
rs.qk = rob_s1.name
303+
else:
304+
rs.vk = self.RF[inst.s1].value
305+
rs.qk = ''
306+
else:
307+
rob_s1 = self.ROB.getby_reg(inst.s1)
308+
if rob_s1.name == self.RF[inst.s1].reorder:
309+
rs.qk = rob_s1.name
310+
else:
311+
rs.vk = self.RF[inst.s1].value
312+
rs.qk = ''
313+
else:
314+
rs.vk = int(inst.s1)
315+
rs.qk = ''
270316
else:
271317
if Instruction.is_operand_reg(inst.s1):
272318
if not self.RF[inst.s1].busy:
@@ -346,6 +392,8 @@ def commit(self):
346392
self.ROB.update_head()
347393
if self.ROB.getby_reg(reg.name) is None:
348394
reg.busy = False
395+
else:
396+
reg.busy = True
349397

350398
def update_clock(self):
351399
self.cycle += 1

Entry.py

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,8 @@ def execute(self):
6666
return [self.dest, self.vj * self.vk]
6767
if self.op == 'DIV':
6868
return [self.dest, self.vj / self.vk]
69+
if self.op == 'BGE':
70+
return [self.dest, 1 if self.vj >= self.vk else 0]
6971
else:
7072
self.counter -= 1
7173
return

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