diff --git a/open-logic/4.0.0/en_cl_fix.core b/open-logic/4.0.0/en_cl_fix.core new file mode 100644 index 0000000..665960c --- /dev/null +++ b/open-logic/4.0.0/en_cl_fix.core @@ -0,0 +1,24 @@ +CAPI=2: + +name : open-logic:open-logic:en_cl_fix:2.2.1 +description : stable release (downloaded from GitHub); see https://github.com/enclustra/en_cl_fix/blob/main/README.md + +filesets: + rtl: + files: + - hdl/en_cl_fix_private_pkg.vhd + - hdl/en_cl_fix_pkg.vhd + file_type : vhdlSource-2008 + logical_name : olo + +targets: + default: + filesets : + - rtl + +provider: + name : github + user : open-logic + repo : en_cl_fix + version : open-logic-2.2.1 + \ No newline at end of file diff --git a/open-logic/4.0.0/olo_axi.core b/open-logic/4.0.0/olo_axi.core new file mode 100644 index 0000000..db885a8 --- /dev/null +++ b/open-logic/4.0.0/olo_axi.core @@ -0,0 +1,29 @@ +CAPI=2: + +name : "open-logic:open-logic:axi:4.0.0" +description : "stable release (downloaded from GitHub); AXI related modules see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#axi" + +filesets: + rtl: + files: + - "src/axi/vhdl/olo_axi_master_simple.vhd" + - "src/axi/vhdl/olo_axi_pl_stage.vhd" + - "src/axi/vhdl/olo_axi_master_full.vhd" + - "src/axi/vhdl/olo_axi_lite_slave.vhd" + - "src/axi/vhdl/olo_axi_pkg_protocol.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.0.0" + + +targets: + default: + filesets : + - "rtl" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.0.0 + \ No newline at end of file diff --git a/open-logic/4.0.0/olo_base.core b/open-logic/4.0.0/olo_base.core new file mode 100644 index 0000000..6a4dee3 --- /dev/null +++ b/open-logic/4.0.0/olo_base.core @@ -0,0 +1,69 @@ +CAPI=2: + +name : "open-logic:open-logic:base:4.0.0" +description : "stable release (downloaded from GitHub); Basic Circuitry (e.g. FIFOs, CDCs, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#base" + +filesets: + rtl: + files: + - "src/base/vhdl/olo_base_crc.vhd" + - "src/base/vhdl/olo_base_cc_n2xn.vhd" + - "src/base/vhdl/olo_base_arb_rr.vhd" + - "src/base/vhdl/olo_base_cc_simple.vhd" + - "src/base/vhdl/olo_base_ram_sdp.vhd" + - "src/base/vhdl/olo_base_delay_cfg.vhd" + - "src/base/vhdl/olo_base_decode_firstbit.vhd" + - "src/base/vhdl/olo_base_ram_tdp.vhd" + - "src/base/vhdl/olo_base_strobe_gen.vhd" + - "src/base/vhdl/olo_base_wconv_n2m.vhd" + - "src/base/vhdl/olo_base_wconv_n2xn.vhd" + - "src/base/vhdl/olo_base_fifo_async.vhd" + - "src/base/vhdl/olo_base_arb_prio.vhd" + - "src/base/vhdl/olo_base_cc_reset.vhd" + - "src/base/vhdl/olo_base_delay.vhd" + - "src/base/vhdl/olo_base_prbs.vhd" + - "src/base/vhdl/olo_base_tdm_mux.vhd" + - "src/base/vhdl/olo_base_cc_handshake.vhd" + - "src/base/vhdl/olo_base_pkg_string.vhd" + - "src/base/vhdl/olo_base_pkg_array.vhd" + - "src/base/vhdl/olo_base_flowctrl_handler.vhd" + - "src/base/vhdl/olo_base_dyn_sft.vhd" + - "src/base/vhdl/olo_base_strobe_div.vhd" + - "src/base/vhdl/olo_base_ram_sp.vhd" + - "src/base/vhdl/olo_base_fifo_sync.vhd" + - "src/base/vhdl/olo_base_cc_pulse.vhd" + - "src/base/vhdl/olo_base_pkg_logic.vhd" + - "src/base/vhdl/olo_base_cam.vhd" + - "src/base/vhdl/olo_base_pkg_attribute.vhd" + - "src/base/vhdl/olo_base_cc_status.vhd" + - "src/base/vhdl/olo_base_reset_gen.vhd" + - "src/base/vhdl/olo_base_pkg_math.vhd" + - "src/base/vhdl/olo_base_wconv_xn2n.vhd" + - "src/base/vhdl/olo_base_fifo_packet.vhd" + - "src/base/vhdl/olo_base_pl_stage.vhd" + - "src/base/vhdl/olo_base_cc_bits.vhd" + - "src/base/vhdl/olo_base_cc_xn2n.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + + scoped_constraints: + files: + - "src/base/tcl/olo_base_cc_simple.tcl" : {copyto: "base/olo_base_cc_simple.tcl"} + - "src/base/tcl/olo_base_reset_gen.tcl" : {copyto: "base/olo_base_reset_gen.tcl"} + - "src/base/tcl/olo_base_cc_reset.tcl" : {copyto: "base/olo_base_cc_reset.tcl"} + - "src/base/tcl/olo_base_cc_bits.tcl" : {copyto: "base/olo_base_cc_bits.tcl"} + - "src/base/tcl/olo_base_constraints_amd.tcl" : {copyto: "base/olo_base_constraints_amd.tcl", file_type: "tclSource"} + file_type: "user" + + +targets: + default: + filesets : + - "rtl" + - "tool_vivado? (scoped_constraints)" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.0.0 + \ No newline at end of file diff --git a/open-logic/4.0.0/olo_fix.core b/open-logic/4.0.0/olo_fix.core new file mode 100644 index 0000000..527a9d7 --- /dev/null +++ b/open-logic/4.0.0/olo_fix.core @@ -0,0 +1,43 @@ +CAPI=2: + +name : "open-logic:open-logic:fix:4.0.0" +description : "stable release (downloaded from GitHub); Fixed point mathematics see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#fix" + +filesets: + rtl: + files: + - "src/fix/vhdl/olo_fix_abs.vhd" + - "src/fix/vhdl/olo_fix_round.vhd" + - "src/fix/vhdl/olo_fix_limit.vhd" + - "src/fix/vhdl/olo_fix_sim_stimuli.vhd" + - "src/fix/vhdl/olo_fix_resize.vhd" + - "src/fix/vhdl/olo_fix_to_real.vhd" + - "src/fix/vhdl/olo_fix_pkg.vhd" + - "src/fix/vhdl/olo_fix_add.vhd" + - "src/fix/vhdl/olo_fix_private_optional_reg.vhd" + - "src/fix/vhdl/olo_fix_compare.vhd" + - "src/fix/vhdl/olo_fix_saturate.vhd" + - "src/fix/vhdl/olo_fix_sim_from_real.vhd" + - "src/fix/vhdl/olo_fix_sub.vhd" + - "src/fix/vhdl/olo_fix_mult.vhd" + - "src/fix/vhdl/olo_fix_addsub.vhd" + - "src/fix/vhdl/olo_fix_neg.vhd" + - "src/fix/vhdl/olo_fix_from_real.vhd" + - "src/fix/vhdl/olo_fix_sim_checker.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.0.0" + - "^open-logic:open-logic:en_cl_fix:2.2.1" + + +targets: + default: + filesets : + - "rtl" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.0.0 + \ No newline at end of file diff --git a/open-logic/4.0.0/olo_fix_tutorial.core b/open-logic/4.0.0/olo_fix_tutorial.core new file mode 100644 index 0000000..264d6d8 --- /dev/null +++ b/open-logic/4.0.0/olo_fix_tutorial.core @@ -0,0 +1,36 @@ +CAPI=2: +name : open-logic:tutorials:olo_fix_tutorial:4.0.0 +description : stable release (downloaded from GitHub); olo_fix tutorial for open-logic, targetting Zybo Z7-10 board + +filesets: + + zybo_z7: + files: + - doc/tutorials/OloFixTutorial/Files/timing.xdc : {file_type : xdc} + + rtl: + files: + - doc/tutorials/OloFixTutorial/Files/controller_olo_fix.vhd : {file_type : vhdlSource-2008} + - doc/tutorials/OloFixTutorial/Files/fix_formats_pkg.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:fix" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (olo_fix_tutorial_controller)"] + + zybo_z7: + default_tool: vivado + description : Digilent Zybo Z7-10 SoC Kit + filesets : [rtl, zybo_z7] + tools: + vivado: + part : xc7z010clg400-1 + toplevel : olo_fix_tutorial_controller + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.0.0 diff --git a/open-logic/4.0.0/olo_intf.core b/open-logic/4.0.0/olo_intf.core new file mode 100644 index 0000000..aab0e91 --- /dev/null +++ b/open-logic/4.0.0/olo_intf.core @@ -0,0 +1,39 @@ +CAPI=2: + +name : "open-logic:open-logic:intf:4.0.0" +description : "stable release (downloaded from GitHub); Interfaces (e.g. I2C, synchronizer, SPI, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#intf" + +filesets: + rtl: + files: + - "src/intf/vhdl/olo_intf_spi_slave.vhd" + - "src/intf/vhdl/olo_intf_i2c_master.vhd" + - "src/intf/vhdl/olo_intf_debounce.vhd" + - "src/intf/vhdl/olo_intf_clk_meas.vhd" + - "src/intf/vhdl/olo_intf_spi_master.vhd" + - "src/intf/vhdl/olo_intf_sync.vhd" + - "src/intf/vhdl/olo_intf_uart.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.0.0" + + scoped_constraints: + files: + - "src/intf/tcl/olo_intf_spi_master.tcl" : {copyto: "intf/olo_intf_spi_master.tcl"} + - "src/intf/tcl/olo_intf_sync.tcl" : {copyto: "intf/olo_intf_sync.tcl"} + - "src/intf/tcl/olo_intf_constraints_amd.tcl" : {copyto: "intf/olo_intf_constraints_amd.tcl", file_type: "tclSource"} + file_type: "user" + + +targets: + default: + filesets : + - "rtl" + - "tool_vivado? (scoped_constraints)" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.0.0 + \ No newline at end of file diff --git a/open-logic/4.0.0/olo_quartus_tutorial.core b/open-logic/4.0.0/olo_quartus_tutorial.core new file mode 100644 index 0000000..e7a9769 --- /dev/null +++ b/open-logic/4.0.0/olo_quartus_tutorial.core @@ -0,0 +1,38 @@ +CAPI=2: +name : open-logic:tutorials:quartus_tutorial:4.0.0 +description : stable release (downloaded from GitHub); quartus tutorial for open-logic, targetting DE0-CV board + +filesets: + + de0_cv: + files: + - doc/tutorials/QuartusTutorial/Files/timing.sdc : {file_type : SDC} + - doc/tutorials/QuartusTutorial/Files/pinout.tcl : {file_type : tclSource} + + rtl: + files: + - doc/tutorials/QuartusTutorial/Files/quartus_tutorial.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:base" + - "open-logic:open-logic:intf" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (quartus_tutorial)"] + + de0_cv: + default_tool : quartus + filesets : [rtl, de0_cv] + tools: + quartus: + family : Cyclone V + device : 5CEBA4F23C7 + board_device_index : 2 + toplevel: quartus_tutorial + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.0.0 diff --git a/open-logic/4.0.0/olo_vivado_tutorial.core b/open-logic/4.0.0/olo_vivado_tutorial.core new file mode 100644 index 0000000..7411032 --- /dev/null +++ b/open-logic/4.0.0/olo_vivado_tutorial.core @@ -0,0 +1,36 @@ +CAPI=2: +name : open-logic:tutorials:vivado_tutorial:4.0.0 +description : stable release (downloaded from GitHub); vivado tutorial for open-logic, targetting Zybo Z7-10 board + +filesets: + + zybo_z7: + files: + - doc/tutorials/VivadoTutorial/Files/pinout.xdc : {file_type : xdc} + + rtl: + files: + - doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:base" + - "open-logic:open-logic:intf" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (vivado_tutorial)"] + + zybo_z7: + default_tool: vivado + description : Digilent Zybo Z7-10 SoC Kit + filesets : [rtl, zybo_z7] + tools: + vivado: + part : xc7z010clg400-1 + toplevel : vivado_tutorial + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.0.0 diff --git a/open-logic/4.1.0/en_cl_fix.core b/open-logic/4.1.0/en_cl_fix.core new file mode 100644 index 0000000..2889bfe --- /dev/null +++ b/open-logic/4.1.0/en_cl_fix.core @@ -0,0 +1,27 @@ +CAPI=2: + +name : open-logic:open-logic:en_cl_fix:2.3.1 +description : stable release (downloaded from GitHub); see https://github.com/enclustra/en_cl_fix/blob/main/README.md + +filesets: + rtl: + files: + - hdl/en_cl_fix_private_pkg.vhd + - hdl/en_cl_fix_saturate.vhd + - hdl/en_cl_fix_round.vhd + - hdl/en_cl_fix_resize.vhd + - hdl/en_cl_fix_pkg.vhd + file_type : vhdlSource-2008 + logical_name : olo + +targets: + default: + filesets : + - rtl + +provider: + name : github + user : open-logic + repo : en_cl_fix + version : open-logic-2.3.1 + \ No newline at end of file diff --git a/open-logic/4.1.0/olo_axi.core b/open-logic/4.1.0/olo_axi.core new file mode 100644 index 0000000..3633f7d --- /dev/null +++ b/open-logic/4.1.0/olo_axi.core @@ -0,0 +1,29 @@ +CAPI=2: + +name : "open-logic:open-logic:axi:4.1.0" +description : "stable release (downloaded from GitHub); AXI related modules see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#axi" + +filesets: + rtl: + files: + - "src/axi/vhdl/olo_axi_master_simple.vhd" + - "src/axi/vhdl/olo_axi_pl_stage.vhd" + - "src/axi/vhdl/olo_axi_master_full.vhd" + - "src/axi/vhdl/olo_axi_lite_slave.vhd" + - "src/axi/vhdl/olo_axi_pkg_protocol.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.1.0" + + +targets: + default: + filesets : + - "rtl" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.1.0 + \ No newline at end of file diff --git a/open-logic/4.1.0/olo_base.core b/open-logic/4.1.0/olo_base.core new file mode 100644 index 0000000..bda0660 --- /dev/null +++ b/open-logic/4.1.0/olo_base.core @@ -0,0 +1,73 @@ +CAPI=2: + +name : "open-logic:open-logic:base:4.1.0" +description : "stable release (downloaded from GitHub); Basic Circuitry (e.g. FIFOs, CDCs, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#base" + +filesets: + rtl: + files: + - "src/base/vhdl/olo_base_crc.vhd" + - "src/base/vhdl/olo_base_cc_n2xn.vhd" + - "src/base/vhdl/olo_base_arb_rr.vhd" + - "src/base/vhdl/olo_base_cc_simple.vhd" + - "src/base/vhdl/olo_base_ram_sdp.vhd" + - "src/base/vhdl/olo_base_delay_cfg.vhd" + - "src/base/vhdl/olo_base_decode_firstbit.vhd" + - "src/base/vhdl/olo_base_arb_wrr.vhd" + - "src/base/vhdl/olo_base_ram_tdp.vhd" + - "src/base/vhdl/olo_base_strobe_gen.vhd" + - "src/base/vhdl/olo_base_wconv_n2m.vhd" + - "src/base/vhdl/olo_base_wconv_n2xn.vhd" + - "src/base/vhdl/olo_base_fifo_async.vhd" + - "src/base/vhdl/olo_base_arb_prio.vhd" + - "src/base/vhdl/olo_base_cc_reset.vhd" + - "src/base/vhdl/olo_base_delay.vhd" + - "src/base/vhdl/olo_base_prbs.vhd" + - "src/base/vhdl/olo_base_tdm_mux.vhd" + - "src/base/vhdl/olo_base_cc_handshake.vhd" + - "src/base/vhdl/olo_base_pkg_string.vhd" + - "src/base/vhdl/olo_base_pkg_array.vhd" + - "src/base/vhdl/olo_base_flowctrl_handler.vhd" + - "src/base/vhdl/olo_base_dyn_sft.vhd" + - "src/base/vhdl/olo_base_crc_append.vhd" + - "src/base/vhdl/olo_base_strobe_div.vhd" + - "src/base/vhdl/olo_base_ram_sp.vhd" + - "src/base/vhdl/olo_base_fifo_sync.vhd" + - "src/base/vhdl/olo_base_cc_pulse.vhd" + - "src/base/vhdl/olo_base_pkg_logic.vhd" + - "src/base/vhdl/olo_base_crc_check.vhd" + - "src/base/vhdl/olo_base_cam.vhd" + - "src/base/vhdl/olo_base_pkg_attribute.vhd" + - "src/base/vhdl/olo_base_cc_status.vhd" + - "src/base/vhdl/olo_base_reset_gen.vhd" + - "src/base/vhdl/olo_base_pkg_math.vhd" + - "src/base/vhdl/olo_base_wconv_xn2n.vhd" + - "src/base/vhdl/olo_base_fifo_packet.vhd" + - "src/base/vhdl/olo_base_pl_stage.vhd" + - "src/base/vhdl/olo_base_cc_bits.vhd" + - "src/base/vhdl/olo_base_cc_xn2n.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + + scoped_constraints: + files: + - "src/base/tcl/olo_base_cc_simple.tcl" : {copyto: "base/olo_base_cc_simple.tcl"} + - "src/base/tcl/olo_base_reset_gen.tcl" : {copyto: "base/olo_base_reset_gen.tcl"} + - "src/base/tcl/olo_base_ram_sdp.tcl" : {copyto: "base/olo_base_ram_sdp.tcl"} + - "src/base/tcl/olo_base_cc_reset.tcl" : {copyto: "base/olo_base_cc_reset.tcl"} + - "src/base/tcl/olo_base_cc_bits.tcl" : {copyto: "base/olo_base_cc_bits.tcl"} + - "src/base/tcl/olo_base_constraints_amd.tcl" : {copyto: "base/olo_base_constraints_amd.tcl", file_type: "tclSource"} + file_type: "user" + + +targets: + default: + filesets : + - "rtl" + - "tool_vivado? (scoped_constraints)" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.1.0 + \ No newline at end of file diff --git a/open-logic/4.1.0/olo_fix.core b/open-logic/4.1.0/olo_fix.core new file mode 100644 index 0000000..3c289db --- /dev/null +++ b/open-logic/4.1.0/olo_fix.core @@ -0,0 +1,43 @@ +CAPI=2: + +name : "open-logic:open-logic:fix:4.1.0" +description : "stable release (downloaded from GitHub); Fixed point mathematics see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#fix" + +filesets: + rtl: + files: + - "src/fix/vhdl/olo_fix_abs.vhd" + - "src/fix/vhdl/olo_fix_round.vhd" + - "src/fix/vhdl/olo_fix_limit.vhd" + - "src/fix/vhdl/olo_fix_sim_stimuli.vhd" + - "src/fix/vhdl/olo_fix_resize.vhd" + - "src/fix/vhdl/olo_fix_to_real.vhd" + - "src/fix/vhdl/olo_fix_pkg.vhd" + - "src/fix/vhdl/olo_fix_add.vhd" + - "src/fix/vhdl/olo_fix_private_optional_reg.vhd" + - "src/fix/vhdl/olo_fix_compare.vhd" + - "src/fix/vhdl/olo_fix_saturate.vhd" + - "src/fix/vhdl/olo_fix_sim_from_real.vhd" + - "src/fix/vhdl/olo_fix_sub.vhd" + - "src/fix/vhdl/olo_fix_mult.vhd" + - "src/fix/vhdl/olo_fix_addsub.vhd" + - "src/fix/vhdl/olo_fix_neg.vhd" + - "src/fix/vhdl/olo_fix_from_real.vhd" + - "src/fix/vhdl/olo_fix_sim_checker.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.1.0" + - "^open-logic:open-logic:en_cl_fix:2.3.1" + + +targets: + default: + filesets : + - "rtl" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.1.0 + \ No newline at end of file diff --git a/open-logic/4.1.0/olo_fix_tutorial.core b/open-logic/4.1.0/olo_fix_tutorial.core new file mode 100644 index 0000000..36eef88 --- /dev/null +++ b/open-logic/4.1.0/olo_fix_tutorial.core @@ -0,0 +1,36 @@ +CAPI=2: +name : open-logic:tutorials:olo_fix_tutorial:4.1.0 +description : stable release (downloaded from GitHub); olo_fix tutorial for open-logic, targetting Zybo Z7-10 board + +filesets: + + zybo_z7: + files: + - doc/tutorials/OloFixTutorial/Files/timing.xdc : {file_type : xdc} + + rtl: + files: + - doc/tutorials/OloFixTutorial/Files/controller_olo_fix.vhd : {file_type : vhdlSource-2008} + - doc/tutorials/OloFixTutorial/Files/fix_formats_pkg.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:fix" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (olo_fix_tutorial_controller)"] + + zybo_z7: + default_tool: vivado + description : Digilent Zybo Z7-10 SoC Kit + filesets : [rtl, zybo_z7] + tools: + vivado: + part : xc7z010clg400-1 + toplevel : olo_fix_tutorial_controller + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.1.0 diff --git a/open-logic/4.1.0/olo_intf.core b/open-logic/4.1.0/olo_intf.core new file mode 100644 index 0000000..0fb4ceb --- /dev/null +++ b/open-logic/4.1.0/olo_intf.core @@ -0,0 +1,39 @@ +CAPI=2: + +name : "open-logic:open-logic:intf:4.1.0" +description : "stable release (downloaded from GitHub); Interfaces (e.g. I2C, synchronizer, SPI, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#intf" + +filesets: + rtl: + files: + - "src/intf/vhdl/olo_intf_spi_slave.vhd" + - "src/intf/vhdl/olo_intf_i2c_master.vhd" + - "src/intf/vhdl/olo_intf_debounce.vhd" + - "src/intf/vhdl/olo_intf_clk_meas.vhd" + - "src/intf/vhdl/olo_intf_spi_master.vhd" + - "src/intf/vhdl/olo_intf_sync.vhd" + - "src/intf/vhdl/olo_intf_uart.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.1.0" + + scoped_constraints: + files: + - "src/intf/tcl/olo_intf_spi_master.tcl" : {copyto: "intf/olo_intf_spi_master.tcl"} + - "src/intf/tcl/olo_intf_sync.tcl" : {copyto: "intf/olo_intf_sync.tcl"} + - "src/intf/tcl/olo_intf_constraints_amd.tcl" : {copyto: "intf/olo_intf_constraints_amd.tcl", file_type: "tclSource"} + file_type: "user" + + +targets: + default: + filesets : + - "rtl" + - "tool_vivado? (scoped_constraints)" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.1.0 + \ No newline at end of file diff --git a/open-logic/4.1.0/olo_quartus_tutorial.core b/open-logic/4.1.0/olo_quartus_tutorial.core new file mode 100644 index 0000000..532527a --- /dev/null +++ b/open-logic/4.1.0/olo_quartus_tutorial.core @@ -0,0 +1,38 @@ +CAPI=2: +name : open-logic:tutorials:quartus_tutorial:4.1.0 +description : stable release (downloaded from GitHub); quartus tutorial for open-logic, targetting DE0-CV board + +filesets: + + de0_cv: + files: + - doc/tutorials/QuartusTutorial/Files/timing.sdc : {file_type : SDC} + - doc/tutorials/QuartusTutorial/Files/pinout.tcl : {file_type : tclSource} + + rtl: + files: + - doc/tutorials/QuartusTutorial/Files/quartus_tutorial.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:base" + - "open-logic:open-logic:intf" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (quartus_tutorial)"] + + de0_cv: + default_tool : quartus + filesets : [rtl, de0_cv] + tools: + quartus: + family : Cyclone V + device : 5CEBA4F23C7 + board_device_index : 2 + toplevel: quartus_tutorial + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.1.0 diff --git a/open-logic/4.1.0/olo_vivado_tutorial.core b/open-logic/4.1.0/olo_vivado_tutorial.core new file mode 100644 index 0000000..6048271 --- /dev/null +++ b/open-logic/4.1.0/olo_vivado_tutorial.core @@ -0,0 +1,36 @@ +CAPI=2: +name : open-logic:tutorials:vivado_tutorial:4.1.0 +description : stable release (downloaded from GitHub); vivado tutorial for open-logic, targetting Zybo Z7-10 board + +filesets: + + zybo_z7: + files: + - doc/tutorials/VivadoTutorial/Files/pinout.xdc : {file_type : xdc} + + rtl: + files: + - doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:base" + - "open-logic:open-logic:intf" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (vivado_tutorial)"] + + zybo_z7: + default_tool: vivado + description : Digilent Zybo Z7-10 SoC Kit + filesets : [rtl, zybo_z7] + tools: + vivado: + part : xc7z010clg400-1 + toplevel : vivado_tutorial + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.1.0 diff --git a/open-logic/4.2.0/en_cl_fix.core b/open-logic/4.2.0/en_cl_fix.core new file mode 100644 index 0000000..ce2b50a --- /dev/null +++ b/open-logic/4.2.0/en_cl_fix.core @@ -0,0 +1,27 @@ +CAPI=2: + +name : open-logic:open-logic:en_cl_fix:2.3.2 +description : stable release (downloaded from GitHub); see https://github.com/enclustra/en_cl_fix/blob/main/README.md + +filesets: + rtl: + files: + - hdl/en_cl_fix_private_pkg.vhd + - hdl/en_cl_fix_saturate.vhd + - hdl/en_cl_fix_round.vhd + - hdl/en_cl_fix_resize.vhd + - hdl/en_cl_fix_pkg.vhd + file_type : vhdlSource-2008 + logical_name : olo + +targets: + default: + filesets : + - rtl + +provider: + name : github + user : open-logic + repo : en_cl_fix + version : open-logic-2.3.2 + \ No newline at end of file diff --git a/open-logic/4.2.0/olo_axi.core b/open-logic/4.2.0/olo_axi.core new file mode 100644 index 0000000..cf2672b --- /dev/null +++ b/open-logic/4.2.0/olo_axi.core @@ -0,0 +1,29 @@ +CAPI=2: + +name : "open-logic:open-logic:axi:4.2.0" +description : "stable release (downloaded from GitHub); AXI related modules see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#axi" + +filesets: + rtl: + files: + - "src/axi/vhdl/olo_axi_master_simple.vhd" + - "src/axi/vhdl/olo_axi_pl_stage.vhd" + - "src/axi/vhdl/olo_axi_master_full.vhd" + - "src/axi/vhdl/olo_axi_lite_slave.vhd" + - "src/axi/vhdl/olo_axi_pkg_protocol.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.2.0" + + +targets: + default: + filesets : + - "rtl" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.2.0 + \ No newline at end of file diff --git a/open-logic/4.2.0/olo_base.core b/open-logic/4.2.0/olo_base.core new file mode 100644 index 0000000..d9cf937 --- /dev/null +++ b/open-logic/4.2.0/olo_base.core @@ -0,0 +1,74 @@ +CAPI=2: + +name : "open-logic:open-logic:base:4.2.0" +description : "stable release (downloaded from GitHub); Basic Circuitry (e.g. FIFOs, CDCs, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#base" + +filesets: + rtl: + files: + - "src/base/vhdl/olo_base_crc.vhd" + - "src/base/vhdl/olo_base_cc_n2xn.vhd" + - "src/base/vhdl/olo_base_arb_rr.vhd" + - "src/base/vhdl/olo_base_cc_simple.vhd" + - "src/base/vhdl/olo_base_ram_sdp.vhd" + - "src/base/vhdl/olo_base_delay_cfg.vhd" + - "src/base/vhdl/olo_base_decode_firstbit.vhd" + - "src/base/vhdl/olo_base_arb_wrr.vhd" + - "src/base/vhdl/olo_base_ram_tdp.vhd" + - "src/base/vhdl/olo_base_strobe_gen.vhd" + - "src/base/vhdl/olo_base_wconv_n2m.vhd" + - "src/base/vhdl/olo_base_wconv_n2xn.vhd" + - "src/base/vhdl/olo_base_fifo_async.vhd" + - "src/base/vhdl/olo_base_arb_prio.vhd" + - "src/base/vhdl/olo_base_cc_reset.vhd" + - "src/base/vhdl/olo_base_delay.vhd" + - "src/base/vhdl/olo_base_prbs.vhd" + - "src/base/vhdl/olo_base_tdm_mux.vhd" + - "src/base/vhdl/olo_base_cc_handshake.vhd" + - "src/base/vhdl/olo_base_rate_limit.vhd" + - "src/base/vhdl/olo_base_pkg_string.vhd" + - "src/base/vhdl/olo_base_pkg_array.vhd" + - "src/base/vhdl/olo_base_flowctrl_handler.vhd" + - "src/base/vhdl/olo_base_dyn_sft.vhd" + - "src/base/vhdl/olo_base_crc_append.vhd" + - "src/base/vhdl/olo_base_strobe_div.vhd" + - "src/base/vhdl/olo_base_ram_sp.vhd" + - "src/base/vhdl/olo_base_fifo_sync.vhd" + - "src/base/vhdl/olo_base_cc_pulse.vhd" + - "src/base/vhdl/olo_base_pkg_logic.vhd" + - "src/base/vhdl/olo_base_crc_check.vhd" + - "src/base/vhdl/olo_base_cam.vhd" + - "src/base/vhdl/olo_base_pkg_attribute.vhd" + - "src/base/vhdl/olo_base_cc_status.vhd" + - "src/base/vhdl/olo_base_reset_gen.vhd" + - "src/base/vhdl/olo_base_pkg_math.vhd" + - "src/base/vhdl/olo_base_wconv_xn2n.vhd" + - "src/base/vhdl/olo_base_fifo_packet.vhd" + - "src/base/vhdl/olo_base_pl_stage.vhd" + - "src/base/vhdl/olo_base_cc_bits.vhd" + - "src/base/vhdl/olo_base_cc_xn2n.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + + scoped_constraints: + files: + - "src/base/tcl/olo_base_cc_simple.tcl" : {copyto: "base/olo_base_cc_simple.tcl"} + - "src/base/tcl/olo_base_reset_gen.tcl" : {copyto: "base/olo_base_reset_gen.tcl"} + - "src/base/tcl/olo_base_ram_sdp.tcl" : {copyto: "base/olo_base_ram_sdp.tcl"} + - "src/base/tcl/olo_base_cc_reset.tcl" : {copyto: "base/olo_base_cc_reset.tcl"} + - "src/base/tcl/olo_base_cc_bits.tcl" : {copyto: "base/olo_base_cc_bits.tcl"} + - "src/base/tcl/olo_base_constraints_amd.tcl" : {copyto: "base/olo_base_constraints_amd.tcl", file_type: "tclSource"} + file_type: "user" + + +targets: + default: + filesets : + - "rtl" + - "tool_vivado? (scoped_constraints)" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.2.0 + \ No newline at end of file diff --git a/open-logic/4.2.0/olo_fix.core b/open-logic/4.2.0/olo_fix.core new file mode 100644 index 0000000..ae1935c --- /dev/null +++ b/open-logic/4.2.0/olo_fix.core @@ -0,0 +1,43 @@ +CAPI=2: + +name : "open-logic:open-logic:fix:4.2.0" +description : "stable release (downloaded from GitHub); Fixed point mathematics see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#fix" + +filesets: + rtl: + files: + - "src/fix/vhdl/olo_fix_abs.vhd" + - "src/fix/vhdl/olo_fix_round.vhd" + - "src/fix/vhdl/olo_fix_limit.vhd" + - "src/fix/vhdl/olo_fix_sim_stimuli.vhd" + - "src/fix/vhdl/olo_fix_resize.vhd" + - "src/fix/vhdl/olo_fix_to_real.vhd" + - "src/fix/vhdl/olo_fix_pkg.vhd" + - "src/fix/vhdl/olo_fix_add.vhd" + - "src/fix/vhdl/olo_fix_private_optional_reg.vhd" + - "src/fix/vhdl/olo_fix_compare.vhd" + - "src/fix/vhdl/olo_fix_saturate.vhd" + - "src/fix/vhdl/olo_fix_sim_from_real.vhd" + - "src/fix/vhdl/olo_fix_sub.vhd" + - "src/fix/vhdl/olo_fix_mult.vhd" + - "src/fix/vhdl/olo_fix_addsub.vhd" + - "src/fix/vhdl/olo_fix_neg.vhd" + - "src/fix/vhdl/olo_fix_from_real.vhd" + - "src/fix/vhdl/olo_fix_sim_checker.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.2.0" + - "^open-logic:open-logic:en_cl_fix:2.3.2" + + +targets: + default: + filesets : + - "rtl" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.2.0 + \ No newline at end of file diff --git a/open-logic/4.2.0/olo_fix_tutorial.core b/open-logic/4.2.0/olo_fix_tutorial.core new file mode 100644 index 0000000..6c67474 --- /dev/null +++ b/open-logic/4.2.0/olo_fix_tutorial.core @@ -0,0 +1,36 @@ +CAPI=2: +name : open-logic:tutorials:olo_fix_tutorial:4.2.0 +description : stable release (downloaded from GitHub); olo_fix tutorial for open-logic, targetting Zybo Z7-10 board + +filesets: + + zybo_z7: + files: + - doc/tutorials/OloFixTutorial/Files/timing.xdc : {file_type : xdc} + + rtl: + files: + - doc/tutorials/OloFixTutorial/Files/controller_olo_fix.vhd : {file_type : vhdlSource-2008} + - doc/tutorials/OloFixTutorial/Files/fix_formats_pkg.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:fix" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (olo_fix_tutorial_controller)"] + + zybo_z7: + default_tool: vivado + description : Digilent Zybo Z7-10 SoC Kit + filesets : [rtl, zybo_z7] + tools: + vivado: + part : xc7z010clg400-1 + toplevel : olo_fix_tutorial_controller + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.2.0 diff --git a/open-logic/4.2.0/olo_intf.core b/open-logic/4.2.0/olo_intf.core new file mode 100644 index 0000000..1f169f7 --- /dev/null +++ b/open-logic/4.2.0/olo_intf.core @@ -0,0 +1,39 @@ +CAPI=2: + +name : "open-logic:open-logic:intf:4.2.0" +description : "stable release (downloaded from GitHub); Interfaces (e.g. I2C, synchronizer, SPI, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#intf" + +filesets: + rtl: + files: + - "src/intf/vhdl/olo_intf_spi_slave.vhd" + - "src/intf/vhdl/olo_intf_i2c_master.vhd" + - "src/intf/vhdl/olo_intf_debounce.vhd" + - "src/intf/vhdl/olo_intf_clk_meas.vhd" + - "src/intf/vhdl/olo_intf_spi_master.vhd" + - "src/intf/vhdl/olo_intf_sync.vhd" + - "src/intf/vhdl/olo_intf_uart.vhd" + file_type : "vhdlSource-2008" + logical_name : "olo" + depend : + - "^open-logic:open-logic:base:4.2.0" + + scoped_constraints: + files: + - "src/intf/tcl/olo_intf_spi_master.tcl" : {copyto: "intf/olo_intf_spi_master.tcl"} + - "src/intf/tcl/olo_intf_sync.tcl" : {copyto: "intf/olo_intf_sync.tcl"} + - "src/intf/tcl/olo_intf_constraints_amd.tcl" : {copyto: "intf/olo_intf_constraints_amd.tcl", file_type: "tclSource"} + file_type: "user" + + +targets: + default: + filesets : + - "rtl" + - "tool_vivado? (scoped_constraints)" +provider: + name : github + user : open-logic + repo : open-logic + version : 4.2.0 + \ No newline at end of file diff --git a/open-logic/4.2.0/olo_quartus_tutorial.core b/open-logic/4.2.0/olo_quartus_tutorial.core new file mode 100644 index 0000000..426d015 --- /dev/null +++ b/open-logic/4.2.0/olo_quartus_tutorial.core @@ -0,0 +1,38 @@ +CAPI=2: +name : open-logic:tutorials:quartus_tutorial:4.2.0 +description : stable release (downloaded from GitHub); quartus tutorial for open-logic, targetting DE0-CV board + +filesets: + + de0_cv: + files: + - doc/tutorials/QuartusTutorial/Files/timing.sdc : {file_type : SDC} + - doc/tutorials/QuartusTutorial/Files/pinout.tcl : {file_type : tclSource} + + rtl: + files: + - doc/tutorials/QuartusTutorial/Files/quartus_tutorial.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:base" + - "open-logic:open-logic:intf" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (quartus_tutorial)"] + + de0_cv: + default_tool : quartus + filesets : [rtl, de0_cv] + tools: + quartus: + family : Cyclone V + device : 5CEBA4F23C7 + board_device_index : 2 + toplevel: quartus_tutorial + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.2.0 diff --git a/open-logic/4.2.0/olo_vivado_tutorial.core b/open-logic/4.2.0/olo_vivado_tutorial.core new file mode 100644 index 0000000..77f6b2a --- /dev/null +++ b/open-logic/4.2.0/olo_vivado_tutorial.core @@ -0,0 +1,36 @@ +CAPI=2: +name : open-logic:tutorials:vivado_tutorial:4.2.0 +description : stable release (downloaded from GitHub); vivado tutorial for open-logic, targetting Zybo Z7-10 board + +filesets: + + zybo_z7: + files: + - doc/tutorials/VivadoTutorial/Files/pinout.xdc : {file_type : xdc} + + rtl: + files: + - doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource-2008} + depend : + - "open-logic:open-logic:base" + - "open-logic:open-logic:intf" + +targets: + default: &default + filesets : [rtl] + toplevel: ["is_toplevel? (vivado_tutorial)"] + + zybo_z7: + default_tool: vivado + description : Digilent Zybo Z7-10 SoC Kit + filesets : [rtl, zybo_z7] + tools: + vivado: + part : xc7z010clg400-1 + toplevel : vivado_tutorial + +provider: + name : github + user : open-logic + repo : open-logic + version : 4.2.0