Skip to content

Commit a0caa6d

Browse files
committed
CI/modules-zstd: Add calls to verilog simulation targets
Signed-off-by: Pawel Czarnecki <[email protected]>
1 parent 2e1604f commit a0caa6d

File tree

1 file changed

+10
-0
lines changed

1 file changed

+10
-0
lines changed

.github/workflows/modules-zstd.yml

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,16 @@ jobs:
7575
bazel run -c opt $target -- --logtostderr;
7676
done
7777
78+
- name: Build and run verilog simulation of the ZSTD module components (opt)
79+
if: ${{ !cancelled() }}
80+
run: |
81+
for target in $(bazel query 'filter(".*_cocotb_test$", kind(rule, //xls/modules/zstd/...))');
82+
do
83+
echo "running $target";
84+
bazel run -c opt $target;
85+
find sim_build ! -name "*.fst" -type f -exec rm -f {} +;
86+
done
87+
7888
- name: Build ZSTD place and route targets (opt)
7989
if: ${{ !cancelled() }}
8090
run: |

0 commit comments

Comments
 (0)