66import os
77import re
88from pprint import pprint
9- from hdlparse .minilexer import MiniLexer
9+ from typing import List , Optional
10+ from .minilexer import MiniLexer
1011
1112"""VHDL documentation parser"""
1213
@@ -171,20 +172,48 @@ def __init__(self, name, desc=None):
171172 self .kind = 'unknown'
172173 self .desc = desc
173174
175+ def remove_outer_parenthesis (s : Optional [str ]):
176+ if s :
177+ n = 1
178+ while n :
179+ s , n = re .subn (r'\([^()]*\)' , '' , s .strip ()) # remove non-nested/flat balanced parts
180+ return s
181+
182+ class VhdlParameterType :
183+ """Parameter type definition
184+
185+ Args:
186+ name (str): Name of the type
187+ direction(str): "to" or "downto"
188+ r_bound (str): A simple expression based on digits or variable names
189+ l_bound (str): A simple expression based on digits or variable names
190+ arange (str): Original array range string
191+ """
192+
193+ def __init__ (self , name , direction = "" , r_bound = "" , l_bound = "" , arange = "" ):
194+ self .name = name
195+ self .direction = direction .lower ().strip ()
196+ self .r_bound = r_bound .strip ()
197+ self .l_bound = l_bound .strip ()
198+ self .arange = arange
199+
200+ def __repr__ (self ):
201+ return f"VhdlParameterType('{ self .name } ','{ self .arange } ')"
202+
174203
175204class VhdlParameter :
176205 """Parameter to subprograms, ports, and generics
177206
178207 Args:
179208 name (str): Name of the object
180- mode (str): Direction mode for the parameter
181- data_type (str ): Type name for the parameter
182- default_value (str): Default value of the parameter
183- desc (str): Description from object metacomments
184- param_desc (str): Description of the parameter
209+ mode (optional str): Direction mode for the parameter
210+ data_type (optional VhdlParameterType ): Type name for the parameter
211+ default_value (optional str): Default value of the parameter
212+ desc (optional str): Description from object metacomments
213+ param_desc (optional str): Description of the parameter
185214 """
186215
187- def __init__ (self , name , mode = None , data_type = None , default_value = None , desc = None , param_desc = None ):
216+ def __init__ (self , name , mode : Optional [ str ] = None , data_type : Optional [ VhdlParameterType ] = None , default_value : Optional [ str ] = None , desc : Optional [ str ] = None , param_desc : Optional [ str ] = None ):
188217 self .name = name
189218 self .mode = mode
190219 self .data_type = data_type
@@ -210,28 +239,6 @@ def __repr__(self):
210239 return f"VhdlParameter('{ self .name } ', '{ self .mode } ', '{ self .data_type .name + self .data_type .arange } ')"
211240
212241
213- class VhdlParameterType :
214- """Parameter type definition
215-
216- Args:
217- name (str): Name of the type
218- direction(str): "to" or "downto"
219- r_bound (str): A simple expression based on digits or variable names
220- l_bound (str): A simple expression based on digits or variable names
221- arange (str): Original array range string
222- """
223-
224- def __init__ (self , name , direction = "" , r_bound = "" , l_bound = "" , arange = "" ):
225- self .name = name
226- self .direction = direction .strip ()
227- self .r_bound = r_bound .strip ()
228- self .l_bound = l_bound .strip ()
229- self .arange = arange
230-
231- def __repr__ (self ):
232- return f"VhdlParameterType('{ self .name } ','{ self .arange } ')"
233-
234-
235242class VhdlPackage (VhdlObject ):
236243 """Package declaration
237244
@@ -357,7 +364,7 @@ class VhdlEntity(VhdlObject):
357364 desc (str, optional): Description from object metacomments
358365 """
359366
360- def __init__ (self , name , ports , generics = None , sections = None , desc = None ):
367+ def __init__ (self , name : str , ports : List [ VhdlParameter ] , generics : List [ VhdlParameter ] = [] , sections : List [ str ] = [] , desc : Optional [ str ] = None ):
361368 VhdlObject .__init__ (self , name , desc )
362369 self .kind = 'entity'
363370 self .generics = generics if generics is not None else []
@@ -602,7 +609,7 @@ def parse_vhdl(text):
602609 saved_type = groups [0 ]
603610
604611 elif action in (
605- 'array_type' , 'file_type' , 'access_type' , 'record_type' , 'range_type' , 'enum_type' , 'incomplete_type' ):
612+ 'array_type' , 'file_type' , 'access_type' , 'record_type' , 'range_type' , 'enum_type' , 'incomplete_type' ):
606613 vobj = VhdlType (saved_type , cur_package , action , metacomments )
607614 objects .append (vobj )
608615 kind = None
@@ -684,7 +691,7 @@ def is_vhdl(fname):
684691 Returns:
685692 True when file has a VHDL extension.
686693 """
687- return os .path .splitext (fname )[1 ].lower () in ('.vhdl' , '.vhd' )
694+ return os .path .splitext (fname )[- 1 ].lower () in ('.vhdl' , '.vhd' )
688695
689696
690697class VhdlExtractor :
@@ -721,7 +728,11 @@ def extract_objects(self, fname, type_filter=None):
721728 self ._register_array_types (objects )
722729
723730 if type_filter :
724- objects = [o for o in objects if isinstance (o , type_filter )]
731+ if not isinstance (type_filter , list ):
732+ type_filter = [type_filter ]
733+ objects = [
734+ o for o in objects if any (map (lambda clz : isinstance (o , clz ), type_filter ))
735+ ]
725736
726737 return objects
727738
@@ -750,11 +761,7 @@ def is_array(self, data_type):
750761 Returns:
751762 True if ``data_type`` is a known array type.
752763 """
753-
754- # Split off any brackets
755- data_type = data_type .split ('[' )[0 ].strip ()
756-
757- return data_type .lower () in self .array_types
764+ return data_type .name .lower () in self .array_types
758765
759766 def _add_array_types (self , type_defs ):
760767 """Add array data types to internal registry
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