Update README.md

Author: hgoli02

README.md

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 # Computer Architecture Project
-Phase 1 single cycle Datapath
-![alt text](https://s24.picofile.com/file/8450352692/Screenshot_2022_05_23_233935.jpg)
-
-
-in phase 2 we added cache and simulated memory delays (found in doc)
+Phase 3 pipeline MIPS
+![alt text](https://s24.picofile.com/file/8451453684/Visio_pipe.png)
 
 
-![alt text](https://s24.picofile.com/file/8451453684/Visio_pipe.png)
+Phase 1 single cycle MIPS
+![alt text](https://s24.picofile.com/file/8450352692/Screenshot_2022_05_23_233935.jpg)