Skip to content

Commit 7137af8

Browse files
sys-igcigcbot
sys-igc
authored and
igcbot
committed
[Autobackout][FunctionalRegression]Revert of change: b668c76: Improve register estimation for CodeScheduling
- Fix the incorrect estimation of the initial register pressure - Support more special cases for code with various casts in the CodeScheduling's RegisterPressureTracker
1 parent 18a4200 commit 7137af8

File tree

4 files changed

+51
-185
lines changed

4 files changed

+51
-185
lines changed

‎IGC/Compiler/CISACodeGen/CodeScheduling.cpp

Lines changed: 51 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -459,9 +459,7 @@ class RegisterPressureTracker {
459459
if (!I)
460460
return V;
461461

462-
bool IsAddrSpaceCast = isa<AddrSpaceCastInst>(I);
463-
464-
if (isNoOpInst(I, CTX) || IsAddrSpaceCast) {
462+
if (isNoOpInst(I, CTX)) {
465463
return getRealOp(I->getOperand(0));
466464
}
467465
return V;
@@ -570,10 +568,7 @@ class RegisterPressureTracker {
570568
}
571569

572570
int32_t estimateOrUpdateImpl(Instruction *I, bool Update) {
573-
auto *Intr = dyn_cast<GenIntrinsicInst>(I);
574-
bool IsNoOpIntr = Intr && (Intr->getIntrinsicID() == GenISAIntrinsic::GenISA_ptr_to_pair);
575-
576-
if (IGCLLVM::isDebugOrPseudoInst(*I) || I->isLifetimeStartOrEnd() || isNoOpInst(I, CTX) || IsNoOpIntr) {
571+
if (IGCLLVM::isDebugOrPseudoInst(*I) || I->isLifetimeStartOrEnd() || isNoOpInst(I, CTX)) {
577572
// NoOp instructions do not change register pressure
578573
if (Update)
579574
PrintDumpLevel(VerbosityLevel::High, "NoOp instruction: " << getName(I) << "\n");
@@ -998,20 +993,8 @@ class BBScheduler {
998993

999994
int32_t MaxOriginalRegpressure = 0;
1000995
bool OriginalScheduleCanHaveSpills = false;
1001-
1002-
PrintDump("Original schedule: " << BBName << "\n");
1003996
for (auto &I : *BB) {
1004-
std::string Info;
1005-
if (isa<PHINode>(&I)) {
1006-
// PHIs are already included in the initial regpressure
1007-
Info = formatDebugInfo(RPT.getCurrentPressure(), 0, "Phi", getVectorShuffleString(&I, VSA, RCA));
1008-
} else {
1009-
int32_t Estimate = RPT.update(&I);
1010-
Info = formatDebugInfo(RPT.getCurrentPressure(), Estimate, "OG", getVectorShuffleString(&I, VSA, RCA));
1011-
}
1012-
PrintDump(Info);
1013-
PrintInstructionDump(&I);
1014-
997+
RPT.update(&I);
1015998
MaxOriginalRegpressure = std::max(MaxOriginalRegpressure, RPT.getCurrentPressure());
1016999
if (RPT.isRegpressureCritical()) {
10171000
OriginalScheduleCanHaveSpills = true;
@@ -1219,45 +1202,6 @@ class BBScheduler {
12191202
SchedulingConfig &C;
12201203
llvm::raw_ostream *LogStream;
12211204

1222-
// Helper function to format debug information string
1223-
static std::string formatDebugInfo(int32_t CurrentPressure, int32_t Estimate, const std::string Type,
1224-
const std::string AddString = "") {
1225-
const int ESTIMATION_NUMBERS_WIDTH = 12;
1226-
const int INFO_WIDTH = 20;
1227-
std::string Info = std::to_string(CurrentPressure) + ", " + std::to_string(Estimate);
1228-
Info.resize(ESTIMATION_NUMBERS_WIDTH, ' ');
1229-
Info = "(" + Info + ") " + Type + ": ";
1230-
Info.resize(INFO_WIDTH, ' ');
1231-
1232-
if (!AddString.empty()) {
1233-
Info += AddString;
1234-
}
1235-
1236-
return Info;
1237-
}
1238-
1239-
// Helper function to get vector shuffle string
1240-
static std::string getVectorShuffleString(Instruction *I, VectorShuffleAnalysis *VSA, RematChainsAnalysis *RCA) {
1241-
auto *DT = VSA->getDestVector(I);
1242-
auto *V2SP = VSA->getVectorToScalarsPattern(I);
1243-
auto *RCP = RCA->getRematChainPattern(I);
1244-
1245-
std::string VS_String = " ";
1246-
if (RCP) {
1247-
VS_String = "REM ";
1248-
} else if (DT && DT->isNoOp()) {
1249-
VS_String = "NOP ";
1250-
} else if (DT && DT->isVectorShuffle()) {
1251-
VS_String = "VS ";
1252-
} else if (DT && !DT->isVectorShuffle()) {
1253-
VS_String = "SCA ";
1254-
} else if (V2SP) {
1255-
VS_String = "V2S ";
1256-
}
1257-
1258-
return VS_String;
1259-
}
1260-
12611205
class InstructionNode {
12621206
public:
12631207
InstructionNode(Instruction *I, uint32_t N) : I(I), OriginalPosition(N) {
@@ -1278,9 +1222,8 @@ class BBScheduler {
12781222

12791223
void print(llvm::raw_ostream &LogStream) {
12801224
if (IGC_IS_FLAG_ENABLED(DumpCodeScheduling)) {
1281-
const int INFO_WIDTH = 16;
1282-
std::string Info = "#" + std::to_string(OriginalPosition) + ", MW: " + std::to_string(MaxWeight) + " ";
1283-
Info.resize(INFO_WIDTH, ' ');
1225+
std::string Info = "Node #" + std::to_string(OriginalPosition) + ", MW: " + std::to_string(MaxWeight) + " ";
1226+
Info.resize(23, ' ');
12841227
LogStream << Info;
12851228
I->print(LogStream);
12861229
LogStream << "\n";
@@ -2392,8 +2335,31 @@ class BBScheduler {
23922335
}
23932336
}
23942337

2395-
std::string Info = formatDebugInfo(
2396-
RT.getCurrentPressure(), RT.estimate(Node->I), "Im", getVectorShuffleString(Node->I, VSA, RCA));
2338+
std::string Info = std::to_string(RT.getCurrentPressure()) + ", " + std::to_string(RT.estimate(Node->I));
2339+
Info.resize(11, ' ');
2340+
Info = "(" + Info + ") Im: ";
2341+
Info.resize(20, ' ');
2342+
2343+
auto *V2SP = VSA->getVectorToScalarsPattern(Node->I);
2344+
auto *RCP = RCA->getRematChainPattern(Node->I);
2345+
2346+
if (RCP) {
2347+
VS_String = "REM";
2348+
}
2349+
if (DT && DT->isVectorShuffle()) {
2350+
VS_String = "VS ";
2351+
}
2352+
if (DT && !DT->isVectorShuffle()) {
2353+
VS_String = "SCA";
2354+
}
2355+
if (DT && DT->isNoOp()) {
2356+
VS_String = "NOP";
2357+
}
2358+
if (V2SP) {
2359+
VS_String = "V2S";
2360+
}
2361+
2362+
Info += VS_String + " ";
23972363

23982364
PrintDump(Info);
23992365
Node->print(*LogStream);
@@ -2510,11 +2476,27 @@ class BBScheduler {
25102476
AllInstructionsScheduledByRP = false;
25112477
}
25122478

2513-
std::string ChoosingMode = ChooseByRP ? "RP" : "MW";
2514-
ChoosingMode += CanClone ? "*" : "";
2515-
std::string Info = formatDebugInfo(RT.getCurrentPressure(), RT.estimate(Node->I),
2516-
ChoosingMode,
2517-
getVectorShuffleString(Node->I, VSA, RCA));
2479+
// Dump the info
2480+
std::string Info = std::to_string(RT.getCurrentPressure()) + ", " + std::to_string(RT.estimate(Node->I));
2481+
Info.resize(11, ' ');
2482+
Info = "(" + Info + ") " + (ChooseByRP ? "RP" : "MW") + ": ";
2483+
Info.resize(20, ' ');
2484+
2485+
auto *DT = VSA->getDestVector(Node->I);
2486+
2487+
std::string VS_String = " ";
2488+
if (DT && DT->isVectorShuffle()) {
2489+
VS_String = "VS ";
2490+
}
2491+
if (DT && !DT->isVectorShuffle()) {
2492+
VS_String = "SCA";
2493+
}
2494+
if (DT && DT->isNoOp()) {
2495+
VS_String = "NOP";
2496+
}
2497+
2498+
Info += VS_String + (CanClone ? " * " : " ");
2499+
25182500
PrintDump(Info);
25192501
Node->print(*LogStream);
25202502

‎IGC/Compiler/tests/CodeScheduling/reg-est-ptrtopair.ll

Lines changed: 0 additions & 107 deletions
This file was deleted.

‎IGC/Compiler/tests/CodeScheduling/reg-est-vector-cases-simd16.ll

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -113,8 +113,6 @@ entry:
113113

114114
define spir_kernel void @vector_shuffle(ptr addrspace(1) %A) {
115115
; CHECK: Function vector_shuffle
116-
; CHECK: Greedy MW attempt
117-
118116
; CHECK: {{([0-9]+,[ ]*[0-9]+[ ]*).*[ ]*}} [[BASE_ADDR:%.*]] = ptrtoint ptr addrspace(1) [[A:%.*]] to i64
119117

120118
; (6, 512 ) MW: Node #1, MW: 3000 %load2d = call <16 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v16i16(i64 %base_addr, i32 127, i32 1023, i32 127, i32 0, i32 0, i32 16, i32 16, i32 16, i32 2, i1 false, i1 false, i32 4)
@@ -209,7 +207,6 @@ entry:
209207

210208
define spir_kernel void @coalesced_scalars(ptr addrspace(1) %0) {
211209
; CHECK: Function coalesced_scalars
212-
; CHECK: Greedy MW attempt
213210

214211
; the IE instructions are marked as SCA. First IE adds regpressure
215212
; then the last usage of the scalar (fadd) kills the hanging values
@@ -306,7 +303,6 @@ define spir_kernel void @coalesced_scalars(ptr addrspace(1) %0) {
306303

307304
define spir_kernel void @vector_to_scalars_pattern(ptr addrspace(1) %A) {
308305
; CHECK: Function vector_to_scalars_pattern
309-
; CHECK: Greedy MW attempt
310306

311307
; DPAS increases regpressure
312308
; CHECK: {{([0-9]+,[ ]*512[ ]*).*[ ]*}} [[DPAS:%.*]] = call <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32(<8 x float> zeroinitializer, <8 x i16> undef, <8 x i32> zeroinitializer, i32 1, i32 1, i32 1, i32 1, i1 false)

‎IGC/Compiler/tests/CodeScheduling/reg-est-vector-cases-simd32.ll

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@
1919
define spir_kernel void @vector_shuffle_no_op(ptr addrspace(1) %A) {
2020
; CHECK: Function vector_shuffle_no_op
2121
; CHECK: Greedy MW attempt
22-
2322
; CHECK: {{([0-9]+,[ ]*[0-9]+[ ]*).*[ ]*}} [[BASE_ADDR:%.*]] = ptrtoint ptr addrspace(1) [[A:%.*]] to i64
2423

2524
; (6, 512 ) MW: Node #1, MW: 3000 %load2d = call <8 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v8i16(i64 %base_addr, i32 127, i32 1023, i32 127, i32 0, i32 0, i32 16, i32 16, i32 16, i32 2, i1 false, i1 false, i32 4)
@@ -82,8 +81,6 @@ entry:
8281

8382
define spir_kernel void @vector_shuffle(ptr addrspace(1) %A) {
8483
; CHECK: Function vector_shuffle
85-
; CHECK: Greedy MW attempt
86-
8784
; CHECK: {{([0-9]+,[ ]*[0-9]+[ ]*).*[ ]*}} [[BASE_ADDR:%.*]] = ptrtoint ptr addrspace(1) [[A:%.*]] to i64
8885

8986
; (6, 512 ) MW: Node #1, MW: 3000 %load2d = call <8 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v8i16(i64 %base_addr, i32 127, i32 1023, i32 127, i32 0, i32 0, i32 16, i32 16, i32 16, i32 2, i1 false, i1 false, i32 4)
@@ -146,7 +143,6 @@ entry:
146143

147144
define spir_kernel void @coalesced_scalars(ptr addrspace(1) %0) {
148145
; CHECK: Function coalesced_scalars
149-
; CHECK: Greedy MW attempt
150146

151147
; the IE instructions are marked as SCA. First IE adds regpressure
152148
; then the last usage of the scalar (fadd) kills the hanging values
@@ -211,7 +207,6 @@ define spir_kernel void @coalesced_scalars(ptr addrspace(1) %0) {
211207

212208
define spir_kernel void @vector_to_scalars_pattern(ptr addrspace(1) %A) {
213209
; CHECK: Function vector_to_scalars_pattern
214-
; CHECK: Greedy MW attempt
215210

216211
; DPAS increases regpressure
217212
; CHECK: {{([0-9]+,[ ]*512[ ]*).*[ ]*}} [[DPAS:%.*]] = call <4 x float> @llvm.genx.GenISA.sub.group.dpas.v4f32.v4f32.v4i16.v4i32(<4 x float> zeroinitializer, <4 x i16> undef, <4 x i32> zeroinitializer, i32 1, i32 1, i32 1, i32 1, i1 false)

0 commit comments

Comments
 (0)