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Merge branch 'intel:sycl' into UR_docker_TEST
2 parents 9e58b0d + 8f7d08c commit a4463ee

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‎.github/CODEOWNERS

+2
Original file line numberDiff line numberDiff line change
@@ -202,9 +202,11 @@ llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h @intel/dpcpp-san
202202
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h @intel/dpcpp-sanitizers-review
203203
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerOptions.h @intel/dpcpp-sanitizers-review
204204
llvm/include/llvm/Transforms/Instrumentation/MemorySanitizer.h @intel/dpcpp-sanitizers-review
205+
llvm/include/llvm/Transforms/Instrumentation/SPIRVSanitizerCommonUtils.h @intel/dpcpp-sanitizers-review
205206
llvm/include/llvm/Transforms/Instrumentation/ThreadSanitizer.h @intel/dpcpp-sanitizers-review
206207
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp @intel/dpcpp-sanitizers-review
207208
llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @intel/dpcpp-sanitizers-review
209+
llvm/lib/Transforms/Instrumentation/SPIRVSanitizerCommonUtils.cpp @intel/dpcpp-sanitizers-review
208210
llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp @intel/dpcpp-sanitizers-review
209211
llvm/test/Instrumentation/AddressSanitizer/ @intel/dpcpp-sanitizers-review
210212
llvm/test/Instrumentation/MemorySanitizer/ @intel/dpcpp-sanitizers-review

‎.github/workflows/sycl-ur-perf-benchmarking.yml

+2-2
Original file line numberDiff line numberDiff line change
@@ -114,8 +114,8 @@ jobs:
114114
strategy:
115115
matrix:
116116
include:
117-
- ref: ${{ inputs.commit_hash != '' && inputs.commit_hash || format('refs/pull/{0}/head', inputs.pr_no) }}
118-
save_name: ${{ inputs.commit_hash != '' && format('Commit{0}', inputs.commit_hash) || format('PR{0}', inputs.pr_no) }}
117+
- ref: ${{ inputs.commit_hash != '' && inputs.commit_hash || inputs.pr_no != '' && format('refs/pull/{0}/head', inputs.pr_no) || github.ref }}
118+
save_name: ${{ inputs.commit_hash != '' && format('Commit{0}', inputs.commit_hash) || inputs.pr_no != '' && format('PR{0}', inputs.pr_no) || 'Baseline' }}
119119
# Set default values if not specified:
120120
runner: ${{ inputs.runner || '["PVC_PERF"]' }}
121121
backend: ${{ inputs.backend || 'level_zero:gpu' }}

‎.github/workflows/sycl-windows-precommit.yml

+2-20
Original file line numberDiff line numberDiff line change
@@ -82,30 +82,12 @@ jobs:
8282
include:
8383
- name: Intel GEN12 Graphics with Level Zero
8484
runner: '["Windows","gen12"]'
85-
uses: ./.github/workflows/sycl-windows-run-tests.yml
86-
with:
87-
name: ${{ matrix.name }}
88-
runner: ${{ matrix.runner }}
89-
sycl_toolchain_archive: ${{ needs.build.outputs.artifact_archive_name }}
90-
e2e_testing_mode: run-only
91-
e2e_binaries_artifact: sycl_windows_e2ebin
92-
93-
run_full_e2e_tests:
94-
needs: build
95-
# Continue if build was successful.
96-
if: |
97-
always()
98-
&& !cancelled()
99-
&& needs.build.outputs.build_conclusion == 'success'
100-
strategy:
101-
fail-fast: false
102-
matrix:
103-
include:
10485
- name: Intel Battlemage Graphics with Level Zero
10586
runner: '["Windows","bmg"]'
10687
uses: ./.github/workflows/sycl-windows-run-tests.yml
10788
with:
10889
name: ${{ matrix.name }}
10990
runner: ${{ matrix.runner }}
11091
sycl_toolchain_archive: ${{ needs.build.outputs.artifact_archive_name }}
111-
e2e_testing_mode: full
92+
e2e_testing_mode: run-only
93+
e2e_binaries_artifact: sycl_windows_e2ebin

‎.github/workflows/sycl-windows-run-tests.yml

+2-2
Original file line numberDiff line numberDiff line change
@@ -209,12 +209,12 @@ jobs:
209209
rm e2econf_files.txt
210210
211211
- name: Pack E2E test binaries
212-
if: ${{ always() && inputs.tests_selector == 'e2e' && inputs.e2e_testing_mode == 'build-only' }}
212+
if: ${{ always() && !cancelled() && inputs.tests_selector == 'e2e' && inputs.e2e_testing_mode == 'build-only' }}
213213
shell: bash
214214
run: |
215215
tar -czf e2e_bin.tar.gz -C build-e2e .
216216
- name: Upload E2E test binaries
217-
if: ${{ always() && inputs.tests_selector == 'e2e' && inputs.e2e_testing_mode == 'build-only' }}
217+
if: ${{ always() && !cancelled() && inputs.tests_selector == 'e2e' && inputs.e2e_testing_mode == 'build-only' }}
218218
uses: actions/upload-artifact@v4
219219
with:
220220
name: ${{ inputs.e2e_binaries_artifact }}

‎clang/include/clang/AST/RecordLayout.h

+4-3
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,9 @@ class ASTRecordLayout {
7575
// performance or backwards compatibility preserving (e.g. AIX-ABI).
7676
CharUnits PreferredAlignment;
7777

78-
// UnadjustedAlignment - Maximum of the alignments of the record members in
79-
// characters.
78+
// UnadjustedAlignment - Alignment of record in characters before alignment
79+
// adjustments. Maximum of the alignments of the record members and base
80+
// classes in characters.
8081
CharUnits UnadjustedAlignment;
8182

8283
/// RequiredAlignment - The required alignment of the object. In the MS-ABI
@@ -186,7 +187,7 @@ class ASTRecordLayout {
186187
CharUnits getPreferredAlignment() const { return PreferredAlignment; }
187188

188189
/// getUnadjustedAlignment - Get the record alignment in characters, before
189-
/// alignment adjustement.
190+
/// alignment adjustment.
190191
CharUnits getUnadjustedAlignment() const { return UnadjustedAlignment; }
191192

192193
/// getSize - Get the record size in characters.

‎clang/include/clang/Basic/CodeGenOptions.def

+5
Original file line numberDiff line numberDiff line change
@@ -480,6 +480,11 @@ CODEGENOPT(DisableSYCLEarlyOpts, 1, 0)
480480
/// which do not contain "user" code.
481481
CODEGENOPT(OptimizeSYCLFramework, 1, 0)
482482

483+
/// Whether to use alloca address space for `sret` arguments.
484+
/// TODO: This option can be removed once a fix goes in that can
485+
/// work with the community changes for using the alloca address space.
486+
CODEGENOPT(UseAllocaASForSrets, 1, 0)
487+
483488
/// Turn on fp64 partial emulation for kernels with only fp64 conversion
484489
/// operations and no fp64 computation operations (requires Intel GPU backend
485490
/// supporting fp64 partial emulation)

‎clang/include/clang/Driver/Options.td

+14-4
Original file line numberDiff line numberDiff line change
@@ -7145,10 +7145,13 @@ defm sycl_force_inline_kernel_lambda
71457145
NegFlag<SetFalse, [], [ClangOption, CLOption], "Disallow">,
71467146
BothFlags<[], [ClangOption, CLOption, CC1Option], " force inline "
71477147
"SYCL kernels lambda in entry point">>;
7148-
def fsycl_help_EQ : Joined<["-"], "fsycl-help=">, Flags<[NoXarchOption]>,
7149-
HelpText<"Emit help information from the related offline compilation tool. "
7150-
"Valid values: all, fpga, gen, x86_64.">,
7151-
Values<"all,fpga,gen,x86_64">;
7148+
def fsycl_help_EQ
7149+
: Joined<["-"], "fsycl-help=">,
7150+
Flags<[NoXarchOption]>,
7151+
HelpText<
7152+
"Emit help information from the related offline compilation tool. "
7153+
"Valid values: all, gen, x86_64.">,
7154+
Values<"all,gen,x86_64">;
71527155
def fsycl_help : Flag<["-"], "fsycl-help">, Alias<fsycl_help_EQ>,
71537156
Flags<[NoXarchOption]>, AliasArgs<["all"]>,
71547157
HelpText<"Emit help information from all of the offline compilation tools">;
@@ -8827,6 +8830,13 @@ def fsycl_is_native_cpu : Flag<["-"], "fsycl-is-native-cpu">,
88278830
HelpText<"Perform device compilation for Native CPU.">,
88288831
Visibility<[CC1Option]>,
88298832
MarshallingInfoFlag<LangOpts<"SYCLIsNativeCPU">>;
8833+
// TODO: This option can be removed once a fix goes in that can
8834+
// work with the community changes for using the alloca address space.
8835+
defm offload_use_alloca_addrspace_for_srets : BoolFOption<"offload-use-alloca-addrspace-for-srets",
8836+
CodeGenOpts<"UseAllocaASForSrets">,
8837+
DefaultTrue,
8838+
PosFlag<SetTrue, [], [CC1Option], "Use alloca address space for sret arguments for offloading targets">,
8839+
NegFlag<SetFalse>>;
88308840

88318841
} // let Visibility = [CC1Option]
88328842

‎clang/include/clang/Driver/Types.def

-6
Original file line numberDiff line numberDiff line change
@@ -125,12 +125,6 @@ TYPE("tempfiletable", Tempfiletable,INVALID, "table", phases
125125
TYPE("tempAOCOfilelist", TempAOCOfilelist, INVALID, "txt", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
126126
TYPE("archive", Archive, INVALID, "a", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
127127
TYPE("wholearchive", WholeArchive, INVALID, "a", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
128-
TYPE("fpga_aocx", FPGA_AOCX, INVALID, "aocx", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
129-
TYPE("fpga_aocr", FPGA_AOCR, INVALID, "aocr", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
130-
TYPE("fpga_aocr_emu", FPGA_AOCR_EMU, INVALID, "aocr", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
131-
TYPE("fpga_aoco", FPGA_AOCO, INVALID, "aoco", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
132-
TYPE("fpga_dep", FPGA_Dependencies, INVALID, "d", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
133-
TYPE("fpga_dep_list", FPGA_Dependencies_List, INVALID, "txt", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
134128
TYPE("host_dep_image", Host_Dependencies_Image, INVALID, "out", phases::Compile, phases::Backend, phases::Assemble, phases::Link)
135129
TYPE("api-information", API_INFO, INVALID, "json", phases::Precompile)
136130
TYPE("dx-container", DX_CONTAINER, INVALID, "dxo", phases::Compile, phases::Backend)

‎clang/include/clang/Driver/Types.h

-3
Original file line numberDiff line numberDiff line change
@@ -89,9 +89,6 @@ namespace types {
8989
/// isHIP - Is this a HIP input.
9090
bool isHIP(ID Id);
9191

92-
/// isFPGA - Is this FPGA input.
93-
bool isFPGA(ID Id);
94-
9592
/// isArchive - Is this an archive input.
9693
bool isArchive(ID Id);
9794

‎clang/lib/AST/RecordLayoutBuilder.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -1302,6 +1302,7 @@ ItaniumRecordLayoutBuilder::LayoutBase(const BaseSubobjectInfo *Base) {
13021302
setSize(std::max(getSize(), Offset + Layout.getSize()));
13031303

13041304
// Remember max struct/class alignment.
1305+
UnadjustedAlignment = std::max(UnadjustedAlignment, BaseAlign);
13051306
UpdateAlignment(BaseAlign, UnpackedAlignTo, PreferredBaseAlign);
13061307

13071308
return Offset;

‎clang/lib/Basic/Targets/NativeCPU.cpp

+7-45
Original file line numberDiff line numberDiff line change
@@ -60,50 +60,12 @@ NativeCPUTargetInfo::NativeCPUTargetInfo(const llvm::Triple &,
6060
}());
6161
if (HostTriple.getArch() != llvm::Triple::UnknownArch) {
6262
HostTarget = AllocateTarget(HostTriple, Opts);
63-
64-
// Copy properties from host target.
65-
BoolWidth = HostTarget->getBoolWidth();
66-
BoolAlign = HostTarget->getBoolAlign();
67-
IntWidth = HostTarget->getIntWidth();
68-
IntAlign = HostTarget->getIntAlign();
69-
HalfWidth = HostTarget->getHalfWidth();
70-
HalfAlign = HostTarget->getHalfAlign();
71-
FloatWidth = HostTarget->getFloatWidth();
72-
FloatAlign = HostTarget->getFloatAlign();
73-
DoubleWidth = HostTarget->getDoubleWidth();
74-
DoubleAlign = HostTarget->getDoubleAlign();
75-
LongWidth = HostTarget->getLongWidth();
76-
LongAlign = HostTarget->getLongAlign();
77-
LongLongWidth = HostTarget->getLongLongWidth();
78-
LongLongAlign = HostTarget->getLongLongAlign();
79-
PointerWidth = HostTarget->getPointerWidth(LangAS::Default);
80-
PointerAlign = HostTarget->getPointerAlign(LangAS::Default);
81-
MinGlobalAlign = HostTarget->getMinGlobalAlign(/*TypeSize=*/0,
82-
/*HasNonWeakDef=*/true);
83-
NewAlign = HostTarget->getNewAlign();
84-
DefaultAlignForAttributeAligned =
85-
HostTarget->getDefaultAlignForAttributeAligned();
86-
SizeType = HostTarget->getSizeType();
87-
PtrDiffType = HostTarget->getPtrDiffType(LangAS::Default);
88-
IntMaxType = HostTarget->getIntMaxType();
89-
WCharType = HostTarget->getWCharType();
90-
WIntType = HostTarget->getWIntType();
91-
Char16Type = HostTarget->getChar16Type();
92-
Char32Type = HostTarget->getChar32Type();
93-
Int64Type = HostTarget->getInt64Type();
94-
SigAtomicType = HostTarget->getSigAtomicType();
95-
ProcessIDType = HostTarget->getProcessIDType();
96-
97-
UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
98-
UseZeroLengthBitfieldAlignment =
99-
HostTarget->useZeroLengthBitfieldAlignment();
100-
UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
101-
ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
102-
103-
// This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
104-
// we need those macros to be identical on host and device, because (among
105-
// other things) they affect which standard library classes are defined,
106-
// and we need all classes to be defined on both the host and device.
107-
MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
63+
copyAuxTarget(&*HostTarget);
10864
}
10965
}
66+
67+
void NativeCPUTargetInfo::setAuxTarget(const TargetInfo *Aux) {
68+
assert(Aux && "Cannot invoke setAuxTarget without a valid auxiliary target!");
69+
copyAuxTarget(Aux);
70+
getTargetOpts() = Aux->getTargetOpts();
71+
}

‎clang/lib/Basic/Targets/NativeCPU.h

+2
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,8 @@ class LLVM_LIBRARY_VISIBILITY NativeCPUTargetInfo final : public TargetInfo {
5757
}
5858

5959
protected:
60+
void setAuxTarget(const TargetInfo *Aux) override;
61+
6062
ArrayRef<const char *> getGCCRegNames() const override { return {}; }
6163

6264
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {

‎clang/lib/CodeGen/ABIInfoImpl.cpp

+23-7
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,16 @@ ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
2121
// Records with non-trivial destructors/copy-constructors should not be
2222
// passed by value.
2323
if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
24-
return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace(),
24+
return getNaturalAlignIndirect(Ty,
25+
getCodeGenOpts().UseAllocaASForSrets
26+
? getDataLayout().getAllocaAddrSpace()
27+
: CGT.getTargetAddressSpace(Ty),
2528
RAA == CGCXXABI::RAA_DirectInMemory);
2629

27-
return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace());
30+
return getNaturalAlignIndirect(Ty,
31+
getCodeGenOpts().UseAllocaASForSrets
32+
? getDataLayout().getAllocaAddrSpace()
33+
: CGT.getTargetAddressSpace(Ty));
2834
}
2935

3036
// Treat an enum type as its underlying type.
@@ -37,7 +43,10 @@ ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
3743
Context.getTypeSize(Context.getTargetInfo().hasInt128Type()
3844
? Context.Int128Ty
3945
: Context.LongLongTy))
40-
return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace());
46+
return getNaturalAlignIndirect(Ty,
47+
getCodeGenOpts().UseAllocaASForSrets
48+
? getDataLayout().getAllocaAddrSpace()
49+
: CGT.getTargetAddressSpace(Ty));
4150

4251
return (isPromotableIntegerTypeForABI(Ty)
4352
? ABIArgInfo::getExtend(Ty, CGT.ConvertType(Ty))
@@ -49,7 +58,10 @@ ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
4958
return ABIArgInfo::getIgnore();
5059

5160
if (isAggregateTypeForABI(RetTy))
52-
return getNaturalAlignIndirect(RetTy, getDataLayout().getAllocaAddrSpace());
61+
return getNaturalAlignIndirect(RetTy,
62+
getCodeGenOpts().UseAllocaASForSrets
63+
? getDataLayout().getAllocaAddrSpace()
64+
: CGT.getTargetAddressSpace(RetTy));
5365

5466
// Treat an enum type as its underlying type.
5567
if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
@@ -61,7 +73,9 @@ ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
6173
? getContext().Int128Ty
6274
: getContext().LongLongTy))
6375
return getNaturalAlignIndirect(RetTy,
64-
getDataLayout().getAllocaAddrSpace());
76+
getCodeGenOpts().UseAllocaASForSrets
77+
? getDataLayout().getAllocaAddrSpace()
78+
: CGT.getTargetAddressSpace(RetTy));
6579

6680
return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
6781
: ABIArgInfo::getDirect());
@@ -122,14 +136,16 @@ CGCXXABI::RecordArgABI CodeGen::getRecordArgABI(QualType T, CGCXXABI &CXXABI) {
122136
}
123137

124138
bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
125-
const ABIInfo &Info) {
139+
const ABIInfo &Info, CodeGenTypes &CGT) {
126140
QualType Ty = FI.getReturnType();
127141

128142
if (const auto *RT = Ty->getAs<RecordType>())
129143
if (!isa<CXXRecordDecl>(RT->getDecl()) &&
130144
!RT->getDecl()->canPassInRegisters()) {
131145
FI.getReturnInfo() = Info.getNaturalAlignIndirect(
132-
Ty, Info.getDataLayout().getAllocaAddrSpace());
146+
Ty, Info.getCodeGenOpts().UseAllocaASForSrets
147+
? Info.getDataLayout().getAllocaAddrSpace()
148+
: CGT.getTargetAddressSpace(Ty));
133149
return true;
134150
}
135151

‎clang/lib/CodeGen/ABIInfoImpl.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, CGCXXABI &CXXABI);
4646
CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI &CXXABI);
4747

4848
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
49-
const ABIInfo &Info);
49+
const ABIInfo &Info, CodeGenTypes &CGT);
5050

5151
/// Pass transparent unions as if they were the type of the first element. Sema
5252
/// should ensure that all elements of the union have the same "machine type".

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