DPC++ daily 2023-06-14

sycl-nightly/20230614

[CI] Another attempt to fix lint task (#9885)

DPC++ daily 2023-06-13

[CI] Enable HIP/CUDA/ESIMD plugins in nightly build (#9850)

That is needed so that we could use the resulting image to test PRs that
only touch SYCL End-to-End tests

DPC++ daily 2023-06-12

[SYCL] Enhance device code split call graph analysis (#8589)

This patch introduces significant changes to how device code split
detects functions and global variables which should be included into a
cloned module.

There are two main changes done to that:
1. analysis algorithm now traces uses of global variables to allow
adding all globals into every split module
2. analysis algorithm now traces indirect calls, trying to define a list
of all functions which are potentially called indirectly to avoid the
need to disabled device code split completely in presence of indirect
calls

Both things are implemented through new `DependencyGraph` entity, which
replaces `CallGraph` entity we used.
Instead of calls, that new graph is built over _uses_ of functions and
variables to understand which functions and global variables are used by
which functions and global variables.

The most tricky part here is indirect calls: we can't understand which
exact function is being called by an indirect call. However, we can
compile a list of _potentially_-called function by comparing function
signatures with signature of an indirect call.

On top of that, ESIMD handling is refactored by this patch:
- outlined ESIMD-specific handling into a separate function
- created new ESIMD-specific device code split helper

New ESIMD-specific device code split helper is needed, because we should
use different rules for ESIMD and non-ESIMD parts of a module when
splitting it to two. For ESIMD part we want to grab all ESIMD-functions
even if they were not considered as entry points in the original module.
For non-ESIMD part we **don't want** to grab _any_ ESIMD-functions, even
if they are referenced/used by non-ESIMD functions.

Both of those special rules come from `invoke_simd` feature support:
non-ESIMD kernel can indirectly reference a ESIMD function. Since those
different kind of functions require different processing, we have to
completely separate them before processing step. Non-ESIMD module could
be incomplete as a result of such split, but it will be merged back with
ESIMD module after ESIMD lowering. That merge step is required for
`invoke_simd` functionality.

---------

Co-authored-by: Cai, Justin <justin.cai@intel.com>

DPC++ daily 2023-06-10

[SYCL] Add LIT `sycl-intelfpga-annotated-field` (#9467)

#### 1. Some FPGA-backend optimization looks for `@llvm.ptr.annotation`
in the kernel entry and matches it with an argument by identifying
specific IR pattern as follows (this use model is for the need of
attaching a property to a kernel argument)
```
%addr_a = alloca ...
store %arg_a,  %addr_a             ; (1)  store an argument to a local address
...
%0 = load %addr_a                  ; (2)  load the argument from the local address
...
%annotated_ptr = @llvm.ptr.annotation(%ptr, ...)
store %0, %annotated_ptr           ; (3) store the argument get from (2) into an annotated pointer,
                                   ; this store corresponds to annotated field initialization
```
This PR adds a new LIT test `sycl-intelfpga-annotated-field.cpp`
targeting FPGA backend to ensure this dependency won't break.

#### 2. Add lit test `sycl-intelfpga-field.cpp` to check that proper IR
is generated for kernel field initialization, including 3 cases:
 -  initialize pointer field with a global pointer
 -  initialize a float field
 -  initialize a BitInt field
  
#### 3. The new lit tests also check the kernel lambda is not inlined
for FPGA by checking the existence of `call
@MangledNameOfCallOperator(...)` at the end of the kernel entry

#### Note: the new lit tests are temporary for FPGA-backend as this use
model will be replaced by
[CompileTimeProperties](https://intel.github.io/llvm-docs/design/CompileTimeProperties.html).

DPC++ daily 2023-06-09

[SYCL][Test E2E] Add stype to L0 structs (#9801)

device_has_aspect_atomic64_level_zero.cpp
interop-level-zero-interop-task-mem-buffer.cpp
level_zero_uuid.cpp

were missing to set L0 stype for a properties struct,
which would genereate an error in L0 validation layer when
enabled with ZE_DEBUG=6.

Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>

DPC++ daily 2023-06-08

[SYCL][Test E2E] Fix errors in determining aspects/sg sizes (#9690)

* If sycl-ls failed, the error message referenced an undefined variable
* If either the aspects or sub-group sizes were unable to be determined,
  we were later referencing undefined set variables (`lit_config.error`
  doesn't exit immediately).
* Error messages weren't printing stderr

DPC++ daily 2023-06-07

[CI] Generate test matrix on self-hosted runner (#9773)

Github's ubuntu-* runners could take multiple hours to allocate in our
organization. Switch to our self-hosted cuda runner that is sitting idle
because we perform CUDA testing in AWS.

DPC++ daily 2023-06-06

sycl-nightly/20230606

[NFC] Productize clang-offload-extract: clean up code for command lin…

DPC++ daily 2023-06-05

sycl-nightly/20230605

[SYCL] Add missing SYCL 2020 image is_property_of specializations (#9…

DPC++ daily 2023-06-03

[SYCL] Rename win_proxy_loader to pi_win_proxy_loader (#9724)

Co-authored-by: Dale <stewart.t.dale@intel.com>