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0.2.1

  • New Components:
    • Added an integer DotProduct component (#243).
    • Added a ResettableEntries capability allowing us to initialize memories (#253).
    • Added a new value type, SignMagnitudeValue, to use in testing (#232) and potentially for components.
  • Added constraint generation to random() for FixedPointValuePopulator and FloatingPointValuePopulator which allows for generating random values in those types constrained by a fixed range, inclusive or exclusive (gte, gt, lt, lte), and in the case of FloatingPointValue, normal or subnormal numbers in that range (#232).
  • Improved SystemVerilog output:
    • Improved default Module definition and instance naming throughout (#227).
    • Improved output of SystemVerilog internal signal names throughout (#237, #244).
  • Added FixedPointValue and FloatingPointValue operators including negation, and comparison.
    • For FixedPointValue this is a deprecating change as previous operators returned LogicValue and their future operators will return bool (#232). For now, bool return methods are provided for transitioning: .ltBool, .lteBool, .gtBool, and .gteBool. They will be deprecated in the future for operator <, operator <=, operator > and operator >=, respectively.
  • Added dynamic sign extension capability to ReductionTree (#246).
  • Bug fixes:
    • Fixed bug (#239) denormals-as-zero (DAZ) support when computing effective subtraction in floating point addition.
    • Fixed build failure (#240) in MultiplyAccumulate.
  • Updates for current ROHD version 0.6.6 (https://github.com/intel/rohd/releases/tag/v0.6.6) compatibility:
    • Updated FIFO to return the LogicType instead of just Logic (#254), leveraging ROHD 0.6.6's addTypedInput and addTypedOutput capabilities.
    • Fixed use of deprecated Port (#231), which is now Logic.port in ROHD.
    • Updated implementations of Interface classes to add the required clone() method (#245)
  • Improved internal code documentation to use more references of types (#223).

0.2.0

  • Added extensive variable-width floating-point support:
    • Added support classes FloatingPointLogic and FloatingPointValue (#97), (#110), (#131), (#156), (#175), (#134).
    • Added FloatingPointAdder abstract component API with implementations FloatingPointSinglePathAdder and FloatingPointDualPathAdder (#106), with pipelining (#126), (#182).
    • Added explicit J-Bit option for FloatingPointValue and FloatingPointLogic (#193) as well as in the FloatingPointAdderSinglePath and FloatingPointAdderDualPath. This allows for unnormalized floating-point representation by storing the leading '1' or j-bit in the mantissa.
    • Modified FloatingPointValue and FloatingPointLogic to support denormal-as-zero (DAZ) and flush-to-zero (FTZ) (#212). Implemented in FloatingPointAdderSinglePath and FloatingPointAdderDualPath.
    • Added FloatingPointConverter component (#123), (#161) to convert between different widths of FloatingPointLogic.
    • Added FloatingPointMultipler base API with FloatingPointMultiplierSimple implementation component (#152), (#160).
    • Added square root components for floating-point (#188).
  • Added fixed-point support classes FixedPointLogic and FixedPointValue (#99), (#132), (#167), (#172), (#208).
  • Added StaticOrRuntimeParameter configuration class which provides API support for configuration of a hardware feature within a component using a single parameter for either static configuration with a bool or dynamic configuration with a Logic signal (#214).
  • Added AXI4 interface with functional model (#159).
  • Added Control Status Register capabilities (#151), (#205), (#197).
  • Added Sum and Counter components (#89) which are fully-featured capabilities to track counters with multiple inputs and various options to handle overflow.
  • Added Serializer and Deserializer components (#92) which handle marshalling and unmarshalling of data onto wider or narrower interfaces.
  • Added ReductionTree module and ReductionTreeGenerator component (#155), (#180), (#204) which allow generalized reduction operations of arbitrary radix with pipelining.
  • Added Extrema component (#93).
  • Added clock gating componentry (#96), (#111).
  • Added fast RecursiveModulePriorityEncoder (#178) to complement ParallelPrefixPriorityEncoder.
  • Added OnesComplementAdder component (#85).
  • Added CompoundAdder and CarrySelectOnesComplement adder components (#98), (#178).
  • Added extensive integer multiplication support:
    • Added multiplier componentry such as parameterizable Booth-encoders, different kinds of sign extension on a partial-product array, delay-driven Wallace tree compression, and selection of differnt kinds for final adders (#85).
      • Added special visualization of partial-product arrays for debug (#102), (#107).
      • Added support for pipelining (#118), (#137), (#138).
      • Added support for rectangular multiplication and multiple kinds of sign extension (#154).
    • Added components CompressionTreeMultiplier and CompressionTreeMultiplyAccumulate supporting signed and unsigned operands, both statically and logically controlled, rectangular multiplication, Booth encoding with radices 2,4,8, and 16, delay-driven Wallace tree, and configurable final adder, all with exhaustive narrow-width testing (#144).
    • Added wrapper class NativeMultiplier (#125).
  • Added integer MultiCycleDivider (#87), (#117), (#129), (#141).
  • Added Parallel Prefix Tree components: adding ParallelPrefixAdder, ParallelPrefixEncoder, ParallelPrefixIncr, ParallelPrefixDecr and ParallelPrefixOrScan (#77), fixing Issue (#12). The types of prefix trees supported are Kogge-Stone, Sklansky, Brent-Kung, and Ripple.
  • Added Ready-Valid Bus Functional Model (#69).
  • Added HammingEccTramsitter and HammingEccReceiver componentry with SECC/SEDDED/SECDED, and SEDDEDTED (#74).
  • Added BinaryToGray and GrayToBinary conversion components (#54).
  • Added EdgeDetector component (#75).
  • Added Serial Peripheral Interface componentry and functional modeling (#148).
  • Added Find-Nth component (#187).
  • Modified ShiftRegister component to support async reset and different stage reset values (#105).
  • Modified tree form of OneHotToBinary to add error generation (#211).
  • Fixed bugs in FifoChecker sampling at clock edges that caused failures. (#70).
  • Updated ApbTracker for configurable widths and data (#71).
  • Breaking: ParityTransmitter deprecates parity for code,checkError for error and originalData for data.
  • Fixed memory model for read-after-write or read on non-zero latency (#72).
  • Fixed bug in SparseMemoryStorage (#195).
  • Improved MemoryStorage read (#176).
  • Added online schematic generation in the web generator application using yoWASP (WebAssembly form of the yosys logic synthesis tool) and d3schematics graphics (SVG) generation (#84).
  • Modified code to be compatible with ROHD 0.6.0 (#150).
  • Modified code to be lint-compatible with Dart 3.8 (#202).
  • Updated flutter to version 3.27.0 (#212).
  • Added flutter to devcontainer (#79).
  • Fixed documentation linting to be compatible with Dart 3.3.0 and above (#80).

0.1.0

  • The first formally versioned release of ROHD-HCL.