Preparing to release v0.6.8 (#645)

Author: mkorbel1

CHANGELOG.md

@@ -1,3 +1,9 @@
+## 0.6.8
+
+- Fixed a bug where constant assignments or tie-offs could be lost in certain rare scenarios in generated outputs (<https://github.com/intel/rohd/pull/643>).
+- Fixed a bug where an unnamed connection between an output and inOut could be incorrectly pruned during SystemVerilog generation, causing confusing error messages (<https://github.com/intel/rohd/pull/644>).
+- Fixed typos in various documentation, comments, tutorials, etc. (<https://github.com/intel/rohd/pull/642>).
+
 ## 0.6.7
 
 - Significantly improved and simplified generated outputs (including SystemVerilog) by reducing unnecessary signal slicing and swizzling operations and leaving unconnected ports on module instantiations empty (<https://github.com/intel/rohd/pull/638>).

README.md

@@ -69,5 +69,5 @@ ROHD is under active development.  If you're interested in contributing, have fe
 
 ----------------
 
-Copyright (C) 2021-2025 Intel Corporation  
+Copyright (C) 2021-2026 Intel Corporation  
 SPDX-License-Identifier: BSD-3-Clause

lib/src/utilities/config.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2022-2025 Intel Corporation
+// Copyright (C) 2022-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // config.dart
@@ -10,5 +10,5 @@
 /// A utility for ROHD configuration file.
 class Config {
   /// The version of the ROHD framework.
-  static const String version = '0.6.7';
+  static const String version = '0.6.8';
 }

pubspec.yaml

@@ -1,5 +1,5 @@
 name: rohd
-version: 0.6.7
+version: 0.6.8
 description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware.
 homepage: https://intel.github.io/rohd-website
 repository: https://github.com/intel/rohd