Preparing to release v0.6.2 (#560)

Author: mkorbel1

CHANGELOG.md

@@ -1,3 +1,9 @@
+## 0.6.2
+
+- Changed addition syntax for generated SystemVerilog to be prettier, while remaining lint-clean (<https://github.com/intel/rohd/issues/444>).
+- Fixed a problem where end-of-simulation actions were not executed if an exception occurred during simulation (<https://github.com/intel/rohd/pull/558>).
+- Fixed a bug where end-of-simulation actions were not cleared by `Simulator.reset` (<https://github.com/intel/rohd/issues/556>).
+
 ## 0.6.1
 
 - Added `Logic.named` and broadened API for `clone` to make duplicating and naming signals more convenient and succinct (<https://github.com/intel/rohd/pull/550>).

lib/src/simulator.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2024 Intel Corporation
+// Copyright (C) 2021-2025 Intel Corporation
 // Copyright (C) 2024 Adam Rose
 // SPDX-License-Identifier: BSD-3-Clause
 //

lib/src/utilities/config.dart

@@ -10,5 +10,5 @@
 /// A utility for ROHD configuration file.
 class Config {
   /// The version of the ROHD framework.
-  static const String version = '0.6.1';
+  static const String version = '0.6.2';
 }

pubspec.yaml

@@ -1,5 +1,5 @@
 name: rohd
-version: 0.6.1
+version: 0.6.2
 description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware.
 homepage: https://intel.github.io/rohd-website
 repository: https://github.com/intel/rohd