diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..73488eb
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+preproc.manifest
diff --git a/README.md b/README.md
index ef077a8..fee6aab 100644
--- a/README.md
+++ b/README.md
@@ -69,14 +69,7 @@ versions of this tool, and new code should avoid using them.
 If possible, consider configuring your editor to "fold" all code
 between the PPSTART and PPSTOP comments out of your visual field.
 
-In VIM, the simplest way to fold generated code out of your way
-is with the following commands, suitable for adding to your
-`.vimrc` file:
-
-    set foldmarker=PPSTART,PPSTOP
-    set foldmethod=marker
-
-Or, a more complicated way:
+In VIM, you could add the following to your .vimrc file:
 
     autocmd BufWinEnter,Syntax *.v,*.sv syn region ppoutput
       \ start="\/\*PPSTART\*" end="\*PPSTOP\*" fold contains=TOP keepend
@@ -108,8 +101,10 @@ Quick links:
 
 *   [AUTOINC](#Macro_AUTOINC)
 *   [AUTOINTERFACE](#Macro_AUTOINTERFACE)
+*   [AUTONC](#Macro_AUTONC)
 *   [AUTONET](#Macro_AUTONET)
 *   [AUTOTOSTRING](#Macro_AUTOTOSTRING)
+*   [CONFIG](#Macro_CONFIG)
 *   [EXEC](#Macro_EXEC)
 *   [FIXEDPOINT](#Macro_FIXEDPOINT)
 *   [FOREACH](#Macro_FOREACH)
@@ -224,6 +219,21 @@ The above example might expand to something like this:
 
     endmodule
 
+Additional options:
+
+* `--style=<style>` can be used to override the default styling.  ie. `--style=v3`
+
+* `--sort` can be used to force the interface lines to be sorted alphanumerically.
+
+### AUTONC {#Macro_AUTONC}
+
+AUTONC can be used to declare specific nets as no-connects.
+
+The body of this macro is a list of signal names or regular expressions to
+indicate which nets to flag as no-connects.  Signals that match and
+would otherwise be undriven or unloaded are tied off.
+
+
 ### AUTONET {#Macro_AUTONET}
 
 Usage:
@@ -257,6 +267,9 @@ drivers, multiple drivers, or zero load.  Note that verilogpp does not
 fully parse verilog, so AUTONET's warnings are only accurate in designs
 that only contain expansions of INST macros.
 
+If the "--skipif" option is supplied, all signals marked as interfaces
+will be omitted from the net declarations.
+
 If the "--cb" option is supplied, verilogpp will create appropriate clocking
 blocks.  verilogpp's ideas of appropriate clocking blocks are:
 
@@ -355,6 +368,30 @@ Expands to this output file:
     /*PPSTOP*/
 
 
+### CONFIG {#Macro_CONFIG}
+
+The CONFIG macro can be used to set verilogpp configuration settings
+within a source file.  The contents of the CONFIG macro are a list
+of key=value attributes, one per line.
+
+Currently, only one attribute is supported:
+
+* "SUBPATH=<path>"
+
+This attribute can be supplied multiple times, to specific multiple subpaths.
+This subpath specifies an additional path component to be searched for files
+referred to by INST and FORINST macros.  The search is performed by iterating
+through each INCDIR path, and then looking for the file in each SUBPATH
+beneath each INCDIR path.
+
+Example:
+
+    /**CONFIG
+       SUBPATH=generated/ip/directory
+       SUBPATH=another/very/long/path/we/dont/want/to/type/over/and/over/again
+    **/
+
+
 ### EXEC {#Macro_EXEC}
 
 
@@ -690,13 +727,14 @@ of localparam declarations.
 
 ### INST {#Macro_INST}
 
-    /**INST <path> <instance>
+    /**INST <path> <instance> [<options>]
     <specifications> **/
 
 Where:
 
 * "path" is the path to the module to be instantiated.
 * "instance" is the instance name to use for the instantiation.
+* "options" is an optional list of flags.
 * "specifications" is a list of zero or more lines used to map port names
   onto signal names.  This can take a couple of different forms.
 
@@ -712,6 +750,17 @@ Transformation of port names onto signal names occurs by applying a
 set of transformation rules onto the port name to produce the signal
 name that port should connect to.
 
+Some modules internally define local parameters which then leak
+out of the module into the module interface.  These local localparams
+can be handled by manually computing the correct value for each
+parameter, and then overriding the symbolic name of the parameter
+in the port width.  This can be specified like this:
+
+    localparam <param-name> <param-value>
+
+Think of "localparam" as being the same as "parameter", except that a
+parameter isn't added to the "#(...)" clause of a module instantiation.
+
 The simplest transformation simply maps a port to a signal, like this:
 
      .portname(signalname)
@@ -727,6 +776,13 @@ ports of INST-instantiated submodules.  Additionally, the AUTOINTERFACE macro
 can be used to propagate unbound ports from INST-instantiated submodules to the
 module interface.
 
+Options:
+
+* --pretty  Turns on "pretty print" style (equivalent to --style=pretty).
+* --style   Sets the output style ("default", "v2", "pretty", "v3")
+* --compact Use compact naming for ports whose names match the connecting
+            signal (ie. ".clk" instead of ".clk(clk)").
+
 See also: the AUTONET, AUTOINTERFACE, and FORINST macros.
 
 Example:
diff --git a/verilogpp b/verilogpp
index 07c24a9..83f66b7 100755
--- a/verilogpp
+++ b/verilogpp
@@ -139,10 +139,13 @@ $config{"register_delay"} = "#1ns";
 $config{"autonet_allwires"} = 0;
 $config{"prettyprint"} = 0; # Set to enable "pretty" generated code
 $config{"style"} = "default";
+$config{"min_type_width"} = 0; # v3 style only: don't pad type names by default
+$config{"sort_autoif"} = 0;  # sorts autointerface output.
 $config{"fsm_state_suffix"} = ""; # String appended to state signals
 $config{"enable_footer"} = 1;  # writes a timestamp comment at end of each file
 $config{"depend_mode"} = 0;  # generate a dependency comment instead of `include.
 $config{"generated_code_marker"} = "";  # extra indicator for generated text
+$config{"indent_like_macro"} = 0;  # enable to have code blocks indented like the macro.
 $config{"manifest"} = "";  # if set, update a manifest file when files are
                            # reprocessed.
 $config{"enum_states"} = 1;  # enumerate states by default
@@ -178,6 +181,10 @@ sub log_debug {
   }
 }
 
+sub log_info {
+  print STDERR "INFO: @_\n";
+}
+
 # Search INCDIR for a file.
 sub locate_file {
   my $filename = shift;
@@ -544,7 +551,14 @@ sub AsNet($$$) {
   my $self = shift;
   my $mapped_signal = shift;
   my $mapper = shift;
+  my $extra_dims = shift;
   my $width = $self->{width};
+  # If "extra_dims" contained "[1:0]", we would want
+  # to transform the "width" (the packed type attribute)
+  # in the following manner:
+  #    logic [7:0]  --> logic [1:0][7:0]
+  #    foobar_t     --> foobar_t [1:0]
+  #    foo_t[3:0]   --> foo_t [1:0][3:0]
   my $unpacked = [];
   if (defined($self->{unpacked})) {
     $unpacked = [ @{$self->{unpacked}} ];
@@ -562,6 +576,17 @@ sub AsNet($$$) {
       $unpacked->[$i] =~ s/\b${key}\b/$mapper->{LOCALPARAMS}->{$key}/g;
     }
   }
+  if ($extra_dims ne "") {
+    my $idx = index($width, "[");
+    if ($idx == -1) {
+      if ($width ne "") {
+        $width .= " ";
+      }
+      $width .= $extra_dims;
+    } else {
+      substr($width, $idx, 0) = $extra_dims;
+    }
+  }
   my $n = new Net($mapped_signal, $width);
   if ($#{$unpacked} >= 0) {
     $n->set_unpacked($unpacked);
@@ -1262,7 +1287,8 @@ sub init {
   $self->{width} = shift;
   $self->{unpacked} = undef;
   # Count the ports this net is connected to:
-  $self->{count} = { 'input' => 0, 'output' => 0, 'inout' => 0, 'modport' => 0 };
+  $self->{count} = { 'input' => 0, 'output' => 0, 'inout' => 0, 'modport' => 0,
+                     'assign_to' => 0, 'assign_from' => 0 };
 }
 
 sub set_unpacked($$) {
@@ -1289,6 +1315,12 @@ sub MakeCompatibleWith($$) {
   if ($#{$other_net->{unpacked}} > $#{$self->{unpacked}}) { $self->{unpacked} = $other_net->{unpacked}; }
 }
 
+sub ClearAssignmentCounts($) {
+  my $self = shift;
+  $self->{count}->{"assign_to"} = 0;
+  $self->{count}->{"assign_from"} = 0;
+}
+
 sub CountConnection {
   my $self = shift;
   my $dir = shift;
@@ -1297,12 +1329,27 @@ sub CountConnection {
   $self->{count}->{$dir} += 1;
 }
 
-sub NumberOfConnections {
+sub NumberOfOutputConnections {
   my $self = shift;
-  my $dir = shift;
-  return $self->{count}->{$dir};
+  return $self->{count}->{'output'} + $self->{count}->{'assign_to'};
 }
 
+sub NumberOfInputConnections {
+  my $self = shift;
+  return $self->{count}->{'input'} + $self->{count}->{'assign_from'};
+}
+
+sub NumberOfInoutConnections {
+  my $self = shift;
+  return $self->{count}->{'inout'};
+}
+
+sub NumberOfModportConnections {
+  my $self = shift;
+  return $self->{count}->{'modport'};
+}
+
+
 sub Declaration() {
   my $self = shift;
   my $no_regs = shift || 0;
@@ -1314,7 +1361,7 @@ sub Declaration() {
   if (!($no_regs || $config{"autonet_allwires"})) {
     if ($self->{count}->{inout} > 0) {
       $type = "tri";
-    } elsif ($self->{count}->{output} == 0) {
+    } elsif ($self->NumberOfOutputConnections() == 0) {
       $type = "reg";
     }
   }
@@ -1357,13 +1404,13 @@ sub Declaration() {
 sub Port {
   my $self = shift;
   my @return = ('output');
-  if ($self->NumberOfConnections('inout') > 0) {
+  if ($self->NumberOfInoutConnections() > 0) {
     @return = ('inout');
-  } elsif ($self->NumberOfConnections('output') == 0) {
+  } elsif ($self->NumberOfOutputConnections() == 0) {
     @return = ('input');
   }
   push @return, @{$self->Declaration(1)};
-  if ($self->NumberOfConnections('modport') == 1) {
+  if ($self->NumberOfModportConnections() == 1) {
     # this is an interface.  Replace the first two elements.
     shift @return for 1..2;
     unshift(@return, $self->{intf_modport});
@@ -1397,6 +1444,29 @@ sub init {
   }
 }
 
+sub reset_assignment_counts($) {
+  my $self = shift;
+  for my $netname (keys %{$self->{NETS}}) {
+    $self->{NETS}->{$netname}->ClearAssignmentCounts();
+  }
+}
+
+sub recount_assignments($$) {
+  my $self = shift;
+  my $my_interface = shift;
+
+  # mark assignments
+  $self->reset_assignment_counts();
+  for my $symbol_to (keys %{$my_interface->{assigns}}) {
+    # like an output from an assignment block:
+    $self->keep_track_of_assignment($symbol_to, "assign_to");
+  }
+  for my $symbol_from (keys %{$my_interface->{assign_from}}) {
+    # like an input to an assignment block:
+    $self->keep_track_of_assignment($symbol_from, "assign_from");
+  }
+}
+
 sub GetPackageIncludes {
   my $self = shift;
 
@@ -1441,9 +1511,9 @@ sub set_text {
 # macro expansion.
 #
 # returns the expanded macro in a consistent format.
-sub run_macro($$$) {
+sub run_macro($$$$) {
   my $self = shift;
-  my ($text, $function) = @_;
+  my ($text, $function, $indent) = @_;
 
   # trim cruft:
   my $macro = $text; # copy
@@ -1455,6 +1525,11 @@ sub run_macro($$$) {
 
   $macro =~ s/\\\s*\r?\n\r?\s*/ /gsmo;  # unsplit continued lines.
 
+  my $indent_like_macro = $main::config{"indent_like_macro"};
+  if ($macro =~ s/\s*--indent_like_macro//) {
+    $indent_like_macro = 1;
+  }
+
   my $marker = $main::config{"generated_code_marker"};
   # if --mark is specified for any macro, insert a marker before all generated
   # code.
@@ -1472,15 +1547,20 @@ sub run_macro($$$) {
   chomp($result);
 
   if ($marker ne "") {
-    $result =~ s/^/$marker /gmo;
-    $result =~ s/ $//gmo;
+    $marker = "${marker} ";
   }
+  if (!$indent_like_macro) {
+    $indent = "";
+  }
+  $marker = "${indent}${marker}";
+  $result =~ s/^/$marker/gmo;
+  $result =~ s/ $//gmo;
 
   # return the expanded macro:
   if ($result =~ m/^\s*$/ && $main::config{"omit_empty"}) {
     return "${text}";
   } else {
-    return "${text}\n/*PPSTART*/\n${result}\n/*PPSTOP*/\n";
+    return "${text}\n${indent}/*PPSTART*/\n${result}\n${indent}/*PPSTOP*/\n";
   }
 }
 
@@ -1492,10 +1572,10 @@ sub run_macro($$$) {
 sub expand_macro($$) {
   my $self = shift;
   my ($label, $function) = @_;
-  main::log_debug("expanding $label");
 
-  $self->{text} =~ s{(/\*\*${label}\b.*?\*/)}
-   {$self->run_macro($1, $function)}egxs;
+  $self->{text} =~ s{([ \t]*)(/\*\*${label}\b.*?\*/)}
+   { main::log_debug("found $label");
+     "${1}" . $self->run_macro($2, $function, $1)}egxs;
 }
 
 sub normalize_path($) {
@@ -1507,7 +1587,7 @@ sub expand_all_macros {
   my $self = shift;
 
   # delete old preprocessor output
-  my $count = ($self->{text} =~ s{\n?/\*PPSTART\*/.*?/\*PPSTOP\*/\n}{}gso);
+  my $count = ($self->{text} =~ s{\n?\s*/\*PPSTART\*/.*?\s*/\*PPSTOP\*/\n}{}gso);
 
   # operations
   if (!$main::trim) {
@@ -1526,6 +1606,8 @@ sub expand_all_macros {
     $self->expand_macro('FORINST', \&expand_forinst);
     $self->expand_macro('AUTOTOSTRING', \&expand_autotostring);
     $self->expand_macro('AUTOINC', \&expand_includes);
+    # note: AUTONC should expand before AUTOINTERFACE, as it will change
+    #       what ports are declared in AUTOINTERFACE.
     $self->expand_macro('AUTONC', \&expand_autonc);
     # note: AUTOINTERFACE must expand before AUTONET, as it will change
     #       AUTONET's behavior.
@@ -1665,6 +1747,11 @@ sub is_changed {
   return ($orig ne $self->{text});
 }
 
+sub _warn {
+  my @c = caller;
+  print STDERR "WARNING($c[2]): @_\n";
+}
+
 sub report_error {
   print STDERR "ERROR: @_\n";
   print "ERROR: @_\n";
@@ -1714,6 +1801,20 @@ sub parse_instantiate_macro($$) {
   }
   $mapper->{LOCALPARAMS} = \%LOCALPARAMS;
 
+  #
+  # parse out array_dims hacks
+  #
+  # This lets us say things like:
+  #    array_dims ii 7:0
+  # to tell the code to infer that a signal named "foo[ii]" is a slice of a
+  # data type that has an outer dimension of "[7:0]".
+  #
+  my %ARRAY_DIMS = ();
+  while ($macro =~ s/^\s*array_dims\s+(\S+)\s+(\S+)\s*$//mso) {
+    $ARRAY_DIMS{$1} = $2;
+  }
+  $mapper->{ARRAY_DIMS} = \%ARRAY_DIMS;
+
   #
   # parse out overrides
   #
@@ -1770,13 +1871,21 @@ sub keep_track_of_used_net {
 
   my $port = $prototype->GetPortByName($signal);
   my $normalized_net = $mapped_signal;
-  $normalized_net =~ s/\s*\[ [^\]]* \]\s*//gx;  # strip away slice operators.
+  my $extra_dims = "";
+  for my $array_dims (keys(%{$mapper->{ARRAY_DIMS}})) {
+    if ($normalized_net =~ s/\[\Q${array_dims}\E\]//) {
+      $extra_dims .= "[" . $mapper->{ARRAY_DIMS}->{$array_dims} . "]";
+    }
+  }
+  while ($normalized_net =~ s/\s*(\[ [^\]]* \])\s*//x) {
+    main::log_info("${normalized_net}: removed slice: ${1}");
+  }
   if (!defined($self->{NETS}->{$normalized_net})) {
     # This is the first time we've encountered this
     # wire.
-    $self->{NETS}->{$normalized_net} = $port->AsNet($normalized_net, $mapper);
+    $self->{NETS}->{$normalized_net} = $port->AsNet($normalized_net, $mapper, $extra_dims);
   } else {
-    $self->{NETS}->{$normalized_net}->MakeCompatibleWith($port->AsNet($normalized_net, $mapper));
+    $self->{NETS}->{$normalized_net}->MakeCompatibleWith($port->AsNet($normalized_net, $mapper, $extra_dims));
   }
 
   # update count of loads and drivers:
@@ -2157,8 +2266,10 @@ sub expand_instantiate_with_prototype {
     $self->keep_track_of_used_net($prototype, $signal, $mapped_signal, $mapper);
   }
   # trim final comma from last port:
-  $list_of_hookup_arrs[-1]->[0] =~ s/,$//;
-  $list_of_hookup_arrs[-1]->[1] =~ s/,$//;
+  if ($#list_of_hookup_arrs > -1) {
+    $list_of_hookup_arrs[-1]->[0] =~ s/,$//;
+    $list_of_hookup_arrs[-1]->[1] =~ s/,$//;
+  }
 
   #
   # print module instantiation
@@ -2189,7 +2300,7 @@ sub expand_instantiate_with_prototype {
         my $param = $params[$i];
         my $conjunction = ",\n";
         if ($i == $#params) { $conjunction = "\n"; }
-        $param =~ m/.(\S+)\s*\((.+)\)/;
+        $param =~ m/.(\S+?)\s*\((.+)\)/;
         printf("  .%-29s (%s)%s", $1, $2, $conjunction);
       }
       print ") ";
@@ -2301,10 +2412,14 @@ sub expand_autonc($$) {
   my @names = ();
   my @tieoffs = ();
   my @unused = ();
+  my $lint_unused_signals = "lint_unused_signals";
+  if ($macro =~ s/^(.*)--signal=(\S+)/$1/){
+    $lint_unused_signals = $2;
+  }
   foreach my $line (split(/\s*\n\s*/, $macro)) {
     chomp($line);
-    if ($line =~ m/^\s*$/) {continue;}
-    if ($line =~ m/^\/(.*)\/$/) {push @regexes, $1;}
+    if ($line =~ m/^\s*$/) {next;}
+    if ($line =~ m/^!?m?\/(.*)\/;?$/) {push @regexes, $line;}
     else {push @names, $line;}
   }
 
@@ -2312,12 +2427,7 @@ sub expand_autonc($$) {
   my $my_interface = new ModuleSpec()->parse_prototype($self->{text});
 
   # mark assignments
-  for my $symbol_to (keys %{$my_interface->{assigns}}) {
-    $self->keep_track_of_assignment($symbol_to, "output");
-  }
-  for my $symbol_from (keys %{$my_interface->{assign_from}}) {
-    $self->keep_track_of_assignment($symbol_from, "input");
-  }
+  $self->recount_assignments($my_interface);
 
   my @sigs = sort keys %{$self->{NETS}};
   foreach my $s (@sigs) {
@@ -2332,10 +2442,9 @@ sub expand_autonc($$) {
       $found = 1;
     } else {
       foreach my $re (@regexes) {
-        if ($s =~ $re) {
-          $found = 1;
-          last;
-        }
+        $_ = $s;
+        my $result = eval($re);
+        if ($result) { $found = 1; last; }
       }
     }
 
@@ -2347,15 +2456,15 @@ sub expand_autonc($$) {
     next if ($s eq $main::config{"clock"});
     next if ($s eq $main::config{"reset_n"});
 
-    if ($ref->NumberOfConnections('inout') > 0) {
+    if ($ref->NumberOfInoutConnections() > 0) {
       # ignore inout signals
-    } elsif ($ref->NumberOfConnections('modport') > 0) {
+    } elsif ($ref->NumberOfModportConnections() > 0) {
       # ignore interfaces
-    } elsif ($ref->NumberOfConnections('output') == 0) {
+    } elsif ($ref->NumberOfOutputConnections() == 0) {
       # no drivers, so assign to zero.
       push @tieoffs, $s;
       $ref->{count}->{output} = 1;
-    } elsif ($ref->NumberOfConnections('input') == 0) {
+    } elsif ($ref->NumberOfInputConnections() == 0) {
       # no loads, so add to lint_unused signal list.
       push @unused, $s;
       $ref->{count}->{input} = 1;
@@ -2363,14 +2472,16 @@ sub expand_autonc($$) {
   }
 
   if (@tieoffs) {
+    @tieoffs = sort @tieoffs;
     foreach my $s (@tieoffs) {
       print "assign $s = '0;\n";
     }
   }
   if (@unused) {
+    @unused = sort @unused;
     if (@tieoffs) { print "\n"; }
-    print "logic lint_unused_signals;\n";
-    print "assign lint_unused_signals =\n";
+    print "logic ${lint_unused_signals};\n";
+    print "assign ${lint_unused_signals} =\n";
     print "   ",join((" ||\n   ", map { "($_ == '0)" } @unused)),";\n";
   }
 }
@@ -2445,18 +2556,40 @@ The above example might expand to something like this:
     /*PPSTOP*/
 
     endmodule
+
+Additional options:
+
+* `--style=<style>` can be used to override the default styling.  ie. `--style=v3`
+
+* `--sort` can be used to force the interface lines to be sorted alphanumerically.
 EOT
 sub expand_autointerface($$) {
   my $self = shift;
   my $macro = shift;
 
+  my $min_type_width = $main::config{"min_type_width"};
+  my $sort_autoif = $main::config{"sort_autoif"};
   my $style = $main::config{"style"};
   if ($macro =~ s/^(.*)--style=(\S+)/$1/) {
     $style = $2;
   }
+  if ($macro =~ s/^(.*)--sort(ed)?/$1/) {
+    $sort_autoif = 1;
+  }
+
+  my @filters = ();
+  my @macro_lines = split(/\s*[\r\n]\s*/, $macro);
+  foreach my $line (@macro_lines) {
+    $line =~ s/^\s+//;
+    $line =~ s/\s+$//;
+    if ($line =~ m/^m/) {
+      push(@filters, $line);
+    }
+  }
 
   # parse the input and output ports of this module
   my $my_interface = new ModuleSpec()->parse_prototype($self->{text});
+  $self->recount_assignments($my_interface);
 
   my @sigs = sort keys %{$self->{NETS}};
   my @ports = ();
@@ -2470,6 +2603,22 @@ sub expand_autointerface($$) {
     next unless ($s =~ m/[[:alpha:]]/);  # Must have a letter
     next if ($s =~ m/\W/);  # Must only contain "word" characters.
 
+    # If we have filters enabled, skip signals that don't match filters.
+    if ($#filters > -1) {
+      my $matched = 0;
+      $_ = $s;
+      foreach my $filt (@filters) {
+        my $result = eval($filt);
+        if ($result) {
+          $matched = 1;
+          last;
+        }
+      }
+      if (!$matched) {
+        next;
+      }
+    }
+
     # examine each net:
     my $ref = $self->{NETS}->{$s};
 
@@ -2477,59 +2626,49 @@ sub expand_autointerface($$) {
     #
     # ... if the signal is connected to at least one bidirectional port,
     #     then we surface it as a bidirectional port.
-    if ($ref->NumberOfConnections('inout') > 0) {
+    if ($ref->NumberOfInoutConnections() > 0) {
       push (@ports, [' ', $ref->Port()]);
     # ... or, if it is not connected to any output ports, then it must
     #     be an input of the enclosing interface.
-    } elsif ($ref->NumberOfConnections('output') == 0) {
+    } elsif ($ref->NumberOfOutputConnections() == 0) {
       if (!exists($my_interface->{assigns}->{$ref->{name}})) {
         push (@ports, [' ', $ref->Port()]);
       }
     # ... or, if it is not connected to any input ports (ie. nobody
     #     within the module is listening to this signal), then it must
     #     be intended to be an output port of the enclosing interface.
-    } elsif ($ref->NumberOfConnections('input') == 0) {
+    } elsif ($ref->NumberOfInputConnections() == 0) {
       push (@ports, [' ', $ref->Port()]);
     }
   }
 
   &main::Pad2DArray(\@ports, 2, 5);
   if ($style eq "v3") {
+    my @text = ();
     for my $i (0..$#ports) {
       my @p = @{$ports[$i]};
       @p = grep {!/^$/} @p;
       if ($p[1] eq "input") { $p[1] = "input "; }
       if ($p[1] eq "inout") { $p[1] = "inout "; }
-      print (join(" ", @p));
-      if ($i == $#ports) {
-        print "\n";
-      } else {
-        print ",\n";
-      }
-    }
+      my $signame = pop @p;
+      $signame =~ s/^\s+|\s+$//g;
+      my $dir_and_nettype = join(" ", @p[1 .. $#p]);
+      $dir_and_nettype =~ s/^\s+|\s+$//g;
+      my $indent = $p[0];
+      my $min_width = $min_type_width + 6;  # type width + direction
+      my $formatstr = "%s %-${min_width}s %s";
+      my $line = sprintf ($formatstr, $p[0], $dir_and_nettype, $signame);
+      push (@text, $line);
+    }
+    if ($sort_autoif == 1) {
+      @text = sort @text;
+    }
+    print(join(",\n", @text) . "\n");
   } else {
     print &main::TabularAlign(\@ports, ",\n"), "\n";
   }
 }
 
-sub CountAssignments {
-  my $self = shift;
-  my $my_interface = shift;
-
-  foreach my $s (keys %{$my_interface->{assigns}}) {
-    if (defined($self->{NETS}->{$s})) {
-      my $ref = $self->{NETS}->{$s};
-      $ref->CountConnection('output');
-    }
-  }
-  foreach my $s (keys %{$my_interface->{assign_from}}) {
-    if (defined($self->{NETS}->{$s})) {
-      my $ref = $self->{NETS}->{$s};
-      $ref->CountConnection('input');
-    }
-  }
-}
-
 
 $MacroHelp{'AUTONET'} = <<EOT ;
 Usage:
@@ -2611,35 +2750,45 @@ sub expand_autonet($$) {
 
   # --init initializes undriven nets
   my $init = 0;
-  if ($macro =~ s/\s*--?init\s*//) {
+  if ($macro =~ s/\s*--?init//) {
     $init = 1;
   }
 
   # --warn warns of undriven or unloaded nets
   my $warn = 0;
-  if ($macro =~ s/\s*--?warn\s*//) {
+  if ($macro =~ s/\s*--?warn//) {
     $warn = 1;
   }
 
   # --cb auto-generates a clocking block for undriven/unloaded nets
   my $cb = 0;
-  if ($macro =~ s/\s*--?cb\s*//) {
+  if ($macro =~ s/\s*--?cb//) {
     $cb = 1;
   }
 
   my $skipif = 0;
-  if ($macro =~ s/\s*--?skipifs?\s*//) {
+  if ($macro =~ s/\s*--?skipifs?//) {
     $skipif = 1;
   }
 
   my $style = $main::config{"style"};
-  if ($macro =~ s/^(.*)--style=(\S+)/$1/) {
+  if ($macro =~ s/\s*--style=(\S+)//) {
     $style = $2;
   }
 
+  my @filters = ();
+  my @macro_lines = split(/\s*[\r\n]\s*/, $macro);
+  foreach my $line (@macro_lines) {
+    $line =~ s/^\s+//;
+    $line =~ s/\s+$//;
+    if ($line =~ m/^m/) {
+      push(@filters, $line);
+    }
+  }
+
   # parse the input and output ports of this module
   my $my_interface = new ModuleSpec()->parse_prototype($self->{text});
-  $self->CountAssignments($my_interface);
+  $self->recount_assignments($my_interface);
 
   my @sigs = sort keys %{$self->{NETS}};
 
@@ -2648,6 +2797,18 @@ sub expand_autonet($$) {
   my $cb_signals = new SignalSet();
 
   foreach my $s (@sigs) {
+    if ($#filters > -1) {
+      my $matched = 0;
+      $_ = $s;
+      foreach my $filt (@filters) {
+        my $result = eval($filt);
+        if ($result) { $matched = 1; }
+      }
+
+      if (!$matched) {
+        next;
+      }
+    }
     # if signal is in this module's interface, autonet should
     # skip it:
     if ($my_interface->HasPort($s)) {
@@ -2668,52 +2829,53 @@ sub expand_autonet($$) {
     # add it to autonets list of nets:
     my $ref = $self->{NETS}->{$s};
 
-    if ($skipif && $ref->NumberOfConnections('modport') > 0) {
+    if ($skipif && $ref->NumberOfModportConnections() > 0) {
       next;
     }
 
     my $warning = "";
     if ($warn) {
-      if (($ref->NumberOfConnections('input') == 0) &&
-          ($ref->NumberOfConnections('inout') == 0)) {
+      if (($ref->NumberOfInputConnections() == 0) &&
+          ($ref->NumberOfInoutConnections() == 0)) {
         $warning = "  // WARNING: zero load";
       }
-      if (($ref->NumberOfConnections('output') == 0) &&
-          ($ref->NumberOfConnections('inout') == 0)) {
+      if (($ref->NumberOfOutputConnections() == 0) &&
+          ($ref->NumberOfInoutConnections() == 0)) {
         $warning = "  // WARNING: zero drivers";
       }
-      if ($ref->NumberOfConnections('output') > 1) {
-        $warning = "  // WARNING: multiple drivers";
+      if ($ref->NumberOfOutputConnections() > 1) {
+        my $x = $ref->NumberOfOutputConnections();
+        $warning = "  // WARNING: multiple drivers ($x drivers)";
       }
     }
 
     if ($s =~ m/^(.*_)clk$/) {
       push(@cb_clocks, $1);
     }
-    elsif (($ref->NumberOfConnections('input')  == 0) &&
-           ($ref->NumberOfConnections('output') != 0) &&
-           ($ref->NumberOfConnections('inout')  == 0)) {
+    elsif (($ref->NumberOfInputConnections()  == 0) &&
+           ($ref->NumberOfOutputConnections() != 0) &&
+           ($ref->NumberOfInoutConnections()  == 0)) {
       $cb_signals->AddSignal($s, "input");
     }
-    elsif (($ref->NumberOfConnections('input')  != 0) &&
-           ($ref->NumberOfConnections('output') == 0) &&
-           ($ref->NumberOfConnections('inout')  == 0)) {
+    elsif (($ref->NumberOfInputConnections()  != 0) &&
+           ($ref->NumberOfOutputConnections() == 0) &&
+           ($ref->NumberOfInoutConnections()  == 0)) {
       $cb_signals->AddSignal($s, "output");
     }
-    elsif (($ref->NumberOfConnections('input')  == 0) &&
-           ($ref->NumberOfConnections('output') == 0) &&
-           ($ref->NumberOfConnections('inout')  != 0)) {
+    elsif (($ref->NumberOfInputConnections()  == 0) &&
+           ($ref->NumberOfOutputConnections() == 0) &&
+           ($ref->NumberOfInoutConnections()  != 0)) {
       $cb_signals->AddSignal($s, "inout");
     }
 
     # determine what to initialize the register too, if needed.
     my $assignment = "";  # empty string by default
     if ($init) {
-      if ($ref->NumberOfConnections('modport') > 0) {
+      if ($ref->NumberOfModportConnections() > 0) {
         $assignment = "";
-      } elsif ($ref->NumberOfConnections('inout') > 0) {
+      } elsif ($ref->NumberOfInoutConnections() > 0) {
         $assignment = " = 'Z";
-      } elsif ($ref->NumberOfConnections('output') == 0) {
+      } elsif ($ref->NumberOfOutputConnections() == 0) {
         $assignment = " = '0";
       }
       if ($assignment && defined($ref->{unpacked})) {
diff --git a/verilogpp_tests/autoif_genvar.vpp b/verilogpp_tests/autoif_genvar.vpp
new file mode 100644
index 0000000..70870bb
--- /dev/null
+++ b/verilogpp_tests/autoif_genvar.vpp
@@ -0,0 +1,44 @@
+// inst_of_unpacked instantiates an unpacked from unpacked.v
+
+module autoif_generate_for (
+  input wire clk,
+  input wire reset_n,
+  output [7:0] fee [0:10-1],
+  /**AUTOINTERFACE --style=v3 **/
+/*PPSTART*/
+
+/*PPSTOP*/
+);
+
+// TODO(jonathan): fix this:
+/**AUTONET --init **/
+/*PPSTART*/
+wire [3:0][1:0] foo_arr;
+/*PPSTOP*/
+
+for (array_dims ii = 0; ii < 4; ii++) begin : gen_instances
+/**INST drive_two.v drive_two
+   array_dims ii 3:0
+   s/foo/foo_arr[ii]/;
+**/
+/*PPSTART*/
+drive_two drive_two (
+  .foo (foo_arr[ii])
+);
+/*PPSTOP*/
+end : gen_instances
+
+for (array_dims ii = 0; ii < 4; ii++) begin : gen_sink_instances
+/**INST sink_two.v sink_two
+   array_dims ii 3:0
+   s/foo/foo_arr[ii]/;
+**/
+/*PPSTART*/
+drive_one sink_two (
+  .foo (foo_arr[ii])
+);
+/*PPSTOP*/
+
+end : gen_sink_instances
+
+endmodule
diff --git a/verilogpp_tests/autoif_indented.vpp b/verilogpp_tests/autoif_indented.vpp
new file mode 100644
index 0000000..01534b1
--- /dev/null
+++ b/verilogpp_tests/autoif_indented.vpp
@@ -0,0 +1,49 @@
+// inst_of_unpacked instantiates an unpacked from unpacked.v
+
+module inst_of_unpacked (
+  input wire clk,
+  input wire reset_n,
+  output [7:0] fee [0:10-1],
+
+  /**AUTOINTERFACE --indent_like_macro **/
+  /*PPSTART*/
+    output wire [7:0] bar,
+    input  wire       fee_en[0:10-1],
+    input  wire [7:0] foo[0:5],
+    input  wire       foo_en[0:5]
+  /*PPSTOP*/
+);
+
+// foo
+/**AUTONET --init **/
+/*PPSTART*/
+
+/*PPSTOP*/
+
+/**INST unpacked.v u_unpacked **/
+/*PPSTART*/
+unpacked u_unpacked (
+  .clk (clk),
+  .reset_n (reset_n),
+  .foo (foo),
+  .foo_en (foo_en),
+  .bar (bar)
+);
+/*PPSTOP*/
+
+    /**INST unpackedN.v u_unpackedN --indent_like_macro
+       parameter N 10
+       s/^foo/fee/;
+    **/
+    /*PPSTART*/
+    unpackedN #(
+      .N(10)) u_unpackedN (
+      .clk (clk),
+      .reset_n (reset_n),
+      .foo (fee),
+      .foo_en (fee_en),
+      .bar (bar)
+    );
+    /*PPSTOP*/
+
+endmodule
diff --git a/verilogpp_tests/autoif_v3.vpp b/verilogpp_tests/autoif_v3.vpp
index 0547998..5f6462f 100644
--- a/verilogpp_tests/autoif_v3.vpp
+++ b/verilogpp_tests/autoif_v3.vpp
@@ -4,12 +4,12 @@ module inst_of_unpacked (
   input wire clk,
   input wire reset_n,
   output [7:0] fee [0:10-1],
-  /**AUTOINTERFACE --style=v3 **/
+  /**AUTOINTERFACE --style=v3 --sort **/
 /*PPSTART*/
-  output wire [7:0] bar,
-  input  wire fee_en[0:10-1],
   input  wire [7:0] foo[0:5],
-  input  wire foo_en[0:5]
+  input  wire fee_en[0:10-1],
+  input  wire foo_en[0:5],
+  output wire [7:0] bar
 /*PPSTOP*/
 );
 
diff --git a/verilogpp_tests/autonc2.vpp b/verilogpp_tests/autonc2.vpp
index b3a70b4..04e0e1c 100644
--- a/verilogpp_tests/autonc2.vpp
+++ b/verilogpp_tests/autonc2.vpp
@@ -17,15 +17,15 @@ wire [7:0] foo[0:5];
 wire  foo_en[0:5];
 /*PPSTOP*/
 
-/**AUTONC
+/**AUTONC --signal=lint_my_unused_signals
   /.+/
 **/
 /*PPSTART*/
 assign foo = '0;
 assign foo_en = '0;
 
-logic lint_unused_signals;
-assign lint_unused_signals =
+logic lint_my_unused_signals;
+assign lint_my_unused_signals =
    (another_output == '0) ||
    (bar == '0);
 /*PPSTOP*/
diff --git a/verilogpp_tests/autonet_filtered.vpp b/verilogpp_tests/autonet_filtered.vpp
new file mode 100644
index 0000000..5364fa2
--- /dev/null
+++ b/verilogpp_tests/autonet_filtered.vpp
@@ -0,0 +1,38 @@
+// inst_of_unpacked instantiates an unpacked from unpacked.v
+
+module autonet_filtered (
+  input wire clk,
+  input wire reset_n );
+
+/**AUTONET --init --skipif
+  m/^fwd_/;
+  m/_valid$/;
+**/
+/*PPSTART*/
+my_type_t fwd_data = '0;
+wire  fwd_ready;
+reg  fwd_valid = '0;
+wire  rev_valid;
+/*PPSTOP*/
+
+/**INST typed_module.v typed_module  --style=v2
+* parameter TYPE_T my_type_t
+* parameter Mode 2
+**/
+/*PPSTART*/
+typed_moduled #(
+  .TYPE_T(my_type_t),
+  .Mode(2)
+) typed_module (
+  .clk,        // input
+  .rst_n,      // input
+  .fwd_data,   // input
+  .fwd_valid,  // input
+  .fwd_ready,  // output
+  .rev_data,   // output
+  .rev_valid,  // output
+  .rev_ready   // input
+);
+/*PPSTOP*/
+
+endmodule
diff --git a/verilogpp_tests/autonet_genvar.vpp b/verilogpp_tests/autonet_genvar.vpp
new file mode 100644
index 0000000..f8e8e45
--- /dev/null
+++ b/verilogpp_tests/autonet_genvar.vpp
@@ -0,0 +1,42 @@
+// inst_of_unpacked instantiates an unpacked from unpacked.v
+
+module autonet_genvar (
+  input wire clk,
+  input wire reset_n );
+
+axi4_if axi(.clk, .reset_n);
+
+/**AUTONET --init --skipif **/
+/*PPSTART*/
+my_fancy_t[6-1:0][1:0] fwd_data = '0;
+wire [6-1:0] fwd_ready;
+reg [6-1:0] fwd_valid = '0;
+my_fancy_t[1:0] rev_data;
+reg  rev_ready = '0;
+wire  rev_valid;
+reg  rst_n = '0;
+/*PPSTOP*/
+
+for (array_dims ii = 0; ii < 6; ii++) begin : gen_instances
+  /**INST typed_module.v typed_module --style=v2 --indent_like_macro
+  parameter TYPE_T my_fancy_t[1:0]
+  array_dims ii 6-1:0
+  s/fwd_(\S+)/fwd_${1}[ii]/;
+  **/
+  /*PPSTART*/
+  typed_moduled #(
+    .TYPE_T(my_fancy_t[1:0])
+  ) typed_module (
+    .clk,                        // input
+    .rst_n,                      // input
+    .fwd_data   (fwd_data[ii]),  // input
+    .fwd_valid  (fwd_valid[ii]), // input
+    .fwd_ready  (fwd_ready[ii]), // output
+    .rev_data,                   // output
+    .rev_valid,                  // output
+    .rev_ready                   // input
+  );
+  /*PPSTOP*/
+end : gen_instances
+
+endmodule
diff --git a/verilogpp_tests/connect_n_to_n.vpp b/verilogpp_tests/connect_n_to_n.vpp
index 14cde33..69fe2ce 100644
--- a/verilogpp_tests/connect_n_to_n.vpp
+++ b/verilogpp_tests/connect_n_to_n.vpp
@@ -17,7 +17,7 @@ drive_one drive_one_1 (
 );
 /*PPSTOP*/
 
-for (genvar ii = 0; ii < 2; ii += 1) begin : g_sink
+for (array_dims ii = 0; ii < 2; ii += 1) begin : g_sink
 /**INST sink_one.v sink_one
   .foo(bar[ii])
 **/
diff --git a/verilogpp_tests/instv3.vpp b/verilogpp_tests/instv3.vpp
index fd47110..e95665b 100644
--- a/verilogpp_tests/instv3.vpp
+++ b/verilogpp_tests/instv3.vpp
@@ -1,6 +1,10 @@
-/**INST bus_keeper.v keeper7 --style=v3**/
+/**INST bus_keeper.v keeper7 --style=v3
+  parameter WIDTH $bits(bus1_in)
+**/
 /*PPSTART*/
-bus_keeper keeper7 (
+bus_keeper #(
+  .WIDTH                         ($bits(bus1_in))
+) keeper7 (
   .clk,                                                          // input
   .reset_n,                                                      // input
   .busNNN_valid,                                                 // input
diff --git a/verilogpp_tests/preproc.manifest b/verilogpp_tests/preproc.manifest
deleted file mode 100644
index 855e3f7..0000000
--- a/verilogpp_tests/preproc.manifest
+++ /dev/null
@@ -1,55 +0,0 @@
-e338047b09235c54a83d5626830dba9e  ../verilogpp
-ffa007a4806acae2aa22fae129423ebb  autocb.vpp
-e650ff66cc1639b0412f5194bcbeb6f0  autoif.vpp
-bcafe31cdbc3425c992abed300acfbcb  autoif_v3.vpp
-2081fa73bc3e07c4f327902e67365f1f  autointerface_with_interface.vpp
-9590c1ebb34580fbc1e73b575bb94d74  autonc.vpp
-f87b0017fad53e4c8f74ce7950d325c9  autonc2.vpp
-20ece7df3404d1bc3b8fc7b2f24670f6  autonc3.vpp
-4313a969dcfa8480476ae6f251501a59  autonc4.vpp
-adf4397b7b5c4594f27499fc4dd750b7  autonet_skipif.vpp
-d8bf9099c93900253867a09b87c975c1  bar.vpp
-f53ad3ace68d13b0cfa962509f7aac7e  bus_keeper.v
-875e79d3a02ca25709b43c4ec4d996e7  busthing.v
-06ac85dcf869566b67f34896f8351c15  connect_from_array.vpp
-cece23c49bbd061d58a1f2c7b2b93a9d  connect_n_to_n.vpp
-5051d9f9ec99ea0dab3ab26e55546565  connect_to_array.vpp
-d458295df0234bb3d7dcbbc5c2d46ab6  drive_one.v
-9d4a3e8dabb67d3793081a2ad47ff869  drive_two.v
-d965329fce21a475bbd102e30793200c  foo.vpp
-9953d47357b8895179b277cbbeec420e  foreach.vpp
-58099f68bbae4cead0f4515559337e47  forinst.vpp
-4277c8e11642969680dd5534da726828  forinst_params.vpp
-7e7937f60d93529d3d343c2594b994c4  fsm.vpp
-446a4f65830a19a56d67daa984991188  hard2parse.v
-d538a5583cdba57c4ebaeffa3bc1889b  incdir_test.vpp
-51ba5116e93d3252c007296324ffce94  inst_locparam.vpp
-40601cad657d19cf7de45cdb08a1f827  inst_non_ansi.vpp
-1ba43f8894525f9d5cac017303322b80  inst_of_mod_with_interface.vpp
-802bb1901a42b4b1cb6baaa9eb9234b3  inst_of_signed_thing.vpp
-fe40f665771b6330bafa41add7135570  inst_of_typed_module.vpp
-bba772325acb574bf5f74edd944818d5  inst_of_unpacked.vpp
-6341c22c6d129c027a73582aa5407208  instpretty.vpp
-9e61861cb151968a07324288211f0603  instv2.vpp
-47d6aa5b76eb296a91fbb90f0f2c2d73  instv3.vpp
-4d568db3f89a79de93fb77cc20d69154  locparam.v
-7c439f5cdf30af3f4ddac68d373127dd  mark.vpp
-3e14e1391b4efd60fabaf617a4e8709e  missing_file.vpp
-bc8627ca8d97ff3344ee3396b924d568  mod_with_interface.v
-ac8a33665c3df3cc3c4bf0dc59175d82  multiclock.v
-cadd7d4192f7ff9e94faa7f2dde190fe  non_ansi.v
-cbf93af9a193c10198bdee6728bb5418  parameter_substitution.vpp
-a1b6387c90958d801423d77dc8c9ba8e  signed_thing.v
-3faf1ce6740e70274b260824fd6325be  sink_one.v
-bfdf1016afd58f35cf9192800ddb48ef  sink_two.v
-c549a383ecce9a0fef280d445212504d  splitlines.vpp
-1a8d1a7c8dc9c34f04cba346f62ae596  subdir/submodule.v
-398635838df34237c456fc86d09a22f9  subdir/subpath/module_a.v
-735aaebb6bd9f3200a086c6e444e40b8  subpaths_test.vpp
-a4efe1d1ce09ad84c12a1c35e179585b  tostring.vpp
-a604c3d55b35d04a4e7a6219257c9b3f  tostring2.vpp
-6858761f16ba200bb5ce571df3cb171d  typed_module.v
-808aad7f7d9ae0e7a3758b1b41067ea9  unpacked.v
-89638f917b75fef631024b26b72791c7  unpackedN.v
-ec1b851d9d6e13d81182d33b07875e92  verilogpp.fortest.rc
-be60aa4fc7942effca1526f484dd8dcb  warnings.vpp
diff --git a/verilogpp_tests/preproc.manifest.expected b/verilogpp_tests/preproc.manifest.expected
deleted file mode 100644
index f70b6a0..0000000
--- a/verilogpp_tests/preproc.manifest.expected
+++ /dev/null
@@ -1,55 +0,0 @@
-9ef4167253bde2fedc218c53e7a546fd  ../verilogpp
-ffa007a4806acae2aa22fae129423ebb  autocb.vpp
-e650ff66cc1639b0412f5194bcbeb6f0  autoif.vpp
-bcafe31cdbc3425c992abed300acfbcb  autoif_v3.vpp
-2081fa73bc3e07c4f327902e67365f1f  autointerface_with_interface.vpp
-9590c1ebb34580fbc1e73b575bb94d74  autonc.vpp
-f87b0017fad53e4c8f74ce7950d325c9  autonc2.vpp
-20ece7df3404d1bc3b8fc7b2f24670f6  autonc3.vpp
-4313a969dcfa8480476ae6f251501a59  autonc4.vpp
-adf4397b7b5c4594f27499fc4dd750b7  autonet_skipif.vpp
-d8bf9099c93900253867a09b87c975c1  bar.vpp
-f53ad3ace68d13b0cfa962509f7aac7e  bus_keeper.v
-875e79d3a02ca25709b43c4ec4d996e7  busthing.v
-06ac85dcf869566b67f34896f8351c15  connect_from_array.vpp
-cece23c49bbd061d58a1f2c7b2b93a9d  connect_n_to_n.vpp
-5051d9f9ec99ea0dab3ab26e55546565  connect_to_array.vpp
-d458295df0234bb3d7dcbbc5c2d46ab6  drive_one.v
-9d4a3e8dabb67d3793081a2ad47ff869  drive_two.v
-d965329fce21a475bbd102e30793200c  foo.vpp
-9953d47357b8895179b277cbbeec420e  foreach.vpp
-58099f68bbae4cead0f4515559337e47  forinst.vpp
-4277c8e11642969680dd5534da726828  forinst_params.vpp
-7e7937f60d93529d3d343c2594b994c4  fsm.vpp
-446a4f65830a19a56d67daa984991188  hard2parse.v
-d538a5583cdba57c4ebaeffa3bc1889b  incdir_test.vpp
-51ba5116e93d3252c007296324ffce94  inst_locparam.vpp
-40601cad657d19cf7de45cdb08a1f827  inst_non_ansi.vpp
-1ba43f8894525f9d5cac017303322b80  inst_of_mod_with_interface.vpp
-802bb1901a42b4b1cb6baaa9eb9234b3  inst_of_signed_thing.vpp
-fe40f665771b6330bafa41add7135570  inst_of_typed_module.vpp
-bba772325acb574bf5f74edd944818d5  inst_of_unpacked.vpp
-6341c22c6d129c027a73582aa5407208  instpretty.vpp
-9e61861cb151968a07324288211f0603  instv2.vpp
-47d6aa5b76eb296a91fbb90f0f2c2d73  instv3.vpp
-4d568db3f89a79de93fb77cc20d69154  locparam.v
-7c439f5cdf30af3f4ddac68d373127dd  mark.vpp
-3e14e1391b4efd60fabaf617a4e8709e  missing_file.vpp
-bc8627ca8d97ff3344ee3396b924d568  mod_with_interface.v
-ac8a33665c3df3cc3c4bf0dc59175d82  multiclock.v
-cadd7d4192f7ff9e94faa7f2dde190fe  non_ansi.v
-cbf93af9a193c10198bdee6728bb5418  parameter_substitution.vpp
-a1b6387c90958d801423d77dc8c9ba8e  signed_thing.v
-3faf1ce6740e70274b260824fd6325be  sink_one.v
-bfdf1016afd58f35cf9192800ddb48ef  sink_two.v
-c549a383ecce9a0fef280d445212504d  splitlines.vpp
-1a8d1a7c8dc9c34f04cba346f62ae596  subdir/submodule.v
-398635838df34237c456fc86d09a22f9  subdir/subpath/module_a.v
-735aaebb6bd9f3200a086c6e444e40b8  subpaths_test.vpp
-a4efe1d1ce09ad84c12a1c35e179585b  tostring.vpp
-a604c3d55b35d04a4e7a6219257c9b3f  tostring2.vpp
-6858761f16ba200bb5ce571df3cb171d  typed_module.v
-808aad7f7d9ae0e7a3758b1b41067ea9  unpacked.v
-89638f917b75fef631024b26b72791c7  unpackedN.v
-ec1b851d9d6e13d81182d33b07875e92  verilogpp.fortest.rc
-be60aa4fc7942effca1526f484dd8dcb  warnings.vpp
diff --git a/verilogpp_tests/verilogpp_files.t b/verilogpp_tests/verilogpp_files.t
index 0e331be..8dde9a9 100755
--- a/verilogpp_tests/verilogpp_files.t
+++ b/verilogpp_tests/verilogpp_files.t
@@ -29,6 +29,10 @@ use File::Basename;
 use lib File::Basename::dirname(abs_path($0));
 use File::Temp qw/ tempfile /;
 use test_utils;
+use Getopt::Long;
+
+my $update = 0;
+GetOptions("update" => \$update);
 
 my $expected_tests = 0;
 
@@ -55,28 +59,36 @@ my $rc = system($VPP,
                 @testfiles);
 # we don't check return codes as some test files are expected to fail.
 
+sub DiffFiles($$) {
+  my $expected = shift;
+  my $actual = shift;
+  $expected_tests += 2;
+  ok(-e $actual, "$actual exists");
+  my $rc = system("diff -c ${actual} ${expected}");
+  is($rc, 0, "Actual $actual matches expected $expected");
+  if ($rc == 0) {
+    # clean up
+    unlink($actual);
+  } elsif ($update) {
+    print("Updated ${expected}");
+    system("mv -f ${actual} ${expected}");
+  }
+}
+
 sub VerifyFile($) {
-  $expected_tests += 3;  # this method adds 3 checks.
+  $expected_tests += 1;  # this method adds 3 checks.
   my $infile = shift;
   my $outfile = $infile;
   $outfile =~ s/.vpp$/.v/;
   isnt($infile, $outfile, "$outfile named appropriately");
-  ok(-e $outfile, "$outfile exists");
-
-  my $rc = system("diff -c ${infile} ${outfile}");
-  is($rc, 0, "$outfile resynthesized identically");
-  if ($rc == 0) {
-    # clean up
-    unlink($outfile);
-  }
+  DiffFiles($infile, $outfile);
 }
 
-sub VerifyManifest() {
-  $expected_tests += 2;  # this method adds 2 checks
-  ok(-e "./preproc.manifest", "preproc.manifest exists");
-  my $rc = system("diff -c -I verilogpp\$ ./preproc.manifest.expected ./preproc.manifest");
-  is($rc, 0, "preproc.manifest contains expected checksums");
-}
+# Disabled low value, high-churn test:
+#sub VerifyManifest() {
+#  DiffFiles("./preproc.manifest.expected", "./preproc.manifest");
+#  unlink("./preproc.manifest");
+#}
 
 # invoke the preprocessor on these files:
 foreach my $testfile (@testfiles) {
@@ -84,6 +96,7 @@ foreach my $testfile (@testfiles) {
   VerifyFile($testfile);
 }
 
-VerifyManifest();
+# Disabled low value, high-churn test:
+# VerifyManifest();
 
 done_testing($expected_tests);
diff --git a/verilogpp_tests/warnings.vpp b/verilogpp_tests/warnings.vpp
index d58a525..b73064a 100644
--- a/verilogpp_tests/warnings.vpp
+++ b/verilogpp_tests/warnings.vpp
@@ -24,18 +24,19 @@ reg [`HARD2PARSE_COMMAND_WORD] control_input;  // WARNING: zero drivers
 wire [`HARD2PARSE_STATUS_WORD] control_output;  // WARNING: zero load
 wire [15:0] data_to_foobar;  // WARNING: zero load
 wire  data_to_foobar_valid;  // WARNING: zero load
-reg [31:0] foo_in32;  // WARNING: zero drivers
+wire [31:0] foo_in32;
 word_t foo_in_word;  // WARNING: zero drivers
 reg  foobar_clear_to_send;  // WARNING: zero drivers
 wire  foobar_ready_to_send;  // WARNING: zero load
 wire [31:0] in32;
 word_t in_word;  // WARNING: zero drivers
-wire [31:0] out32;  // WARNING: multiple drivers
+wire [31:0] out32;  // WARNING: multiple drivers (3 drivers)
 reg [`HARD2PARSE_COMMAND__SLOT_WIDTH-1:0] slot;  // WARNING: zero drivers
 /*PPSTOP*/
 
 // this should disable the warning for axi_rid
 assign axi_rid = 5;
+assign foo_in32 = 32'd20;
 
 /**INST bar.v u_bar1**/
 /*PPSTART*/