Bone_JTAG_pg3.sch

v 20110115 2
C 39500 39500 0 0 0 EMBEDDEDtitle-bordered-C.sym
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REVISION:
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DRAWN BY: 
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PAGE
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OF
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{
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author=Tom King
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file=Bone_JTAG_pg3.sch
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FPGA JTAG
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C 42500 55200 1 180 1 EMBEDDEDresistor-1.sym
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C 42500 54900 1 180 1 EMBEDDEDresistor-1.sym
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Bone JTAG Programmer/Debugger
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3
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3
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0.97
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C 47000 47700 1 180 0 EMBEDDEDoutput-1.sym
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P 47000 47600 46800 47600 1 0 0
{
T 46750 47650 5 6 0 0 180 0 1
pinseq=1
T 46750 47650 5 6 0 1 180 0 1
pinnumber=1
}
L 46800 47500 46800 47700 3 0 0 0 -1 -1
L 46800 47500 46300 47500 3 0 0 0 -1 -1
L 46300 47500 46200 47600 3 0 0 0 -1 -1
L 46200 47600 46300 47700 3 0 0 0 -1 -1
L 46300 47700 46800 47700 3 0 0 0 -1 -1
T 46900 47400 5 10 0 0 180 0 1
device=OUTPUT
]
{
T 46900 47400 5 10 0 0 180 0 1
device=OUTPUT
T 45400 47500 5 10 1 1 0 0 1
value=GPIO1_6
T 47000 47700 5 10 0 1 0 0 1
net=JC2:1
}
C 47000 48200 1 180 0 EMBEDDEDoutput-1.sym
[
P 47000 48100 46800 48100 1 0 0
{
T 46750 48150 5 6 0 0 180 0 1
pinseq=1
T 46750 48150 5 6 0 1 180 0 1
pinnumber=1
}
L 46800 48000 46800 48200 3 0 0 0 -1 -1
L 46800 48000 46300 48000 3 0 0 0 -1 -1
L 46300 48000 46200 48100 3 0 0 0 -1 -1
L 46200 48100 46300 48200 3 0 0 0 -1 -1
L 46300 48200 46800 48200 3 0 0 0 -1 -1
T 46900 47900 5 10 0 0 180 0 1
device=OUTPUT
]
{
T 46900 47900 5 10 0 0 180 0 1
device=OUTPUT
T 45400 48000 5 10 1 1 0 0 1
value=GPIO1_7
T 47000 48200 5 10 0 1 0 0 1
net=JC3:1
}
C 51600 44200 1 0 0 EMBEDDEDgnd-1.sym
[
T 51900 44250 8 10 0 0 0 0 1
net=GND:1
L 51680 44210 51720 44210 3 0 0 0 -1 -1
L 51655 44250 51745 44250 3 0 0 0 -1 -1
L 51600 44300 51800 44300 3 0 0 0 -1 -1
P 51700 44300 51700 44500 1 0 1
{
T 51758 44361 5 4 0 1 0 0 1
pinnumber=1
T 51758 44361 5 4 0 0 0 0 1
pinseq=1
T 51758 44361 5 4 0 1 0 0 1
pinlabel=1
T 51758 44361 5 4 0 1 0 0 1
pintype=pwr
}
]
C 56000 49500 1 0 0 EMBEDDEDoutput-1.sym
[
P 56000 49600 56200 49600 1 0 0
{
T 56250 49550 5 6 0 0 0 0 1
pinseq=1
T 56250 49550 5 6 0 1 0 0 1
pinnumber=1
}
L 56200 49700 56200 49500 3 0 0 0 -1 -1
L 56200 49700 56700 49700 3 0 0 0 -1 -1
L 56700 49700 56800 49600 3 0 0 0 -1 -1
L 56800 49600 56700 49500 3 0 0 0 -1 -1
L 56700 49500 56200 49500 3 0 0 0 -1 -1
T 56100 49800 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56100 49800 5 10 0 0 0 0 1
device=OUTPUT
T 56800 49500 5 10 1 1 0 0 1
value=Target_TMS
T 56000 49500 5 10 0 1 180 0 1
net=SPI0_SCLK:1
}
C 49300 44500 1 90 1 EMBEDDEDoutput-1.sym
[
L 49300 43800 49300 44300 3 0 0 0 -1 -1
L 49200 43700 49300 43800 3 0 0 0 -1 -1
L 49100 43800 49200 43700 3 0 0 0 -1 -1
L 49100 44300 49100 43800 3 0 0 0 -1 -1
L 49100 44300 49300 44300 3 0 0 0 -1 -1
P 49200 44500 49200 44300 1 0 0
{
T 49250 44250 5 6 0 0 90 6 1
pinseq=1
T 49250 44250 5 6 0 1 90 6 1
pinnumber=1
}
T 49000 44400 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 49000 44400 5 10 0 0 90 6 1
device=OUTPUT
T 49300 43600 5 10 1 1 90 6 1
value=PRU0_16_I
T 49300 44500 5 10 0 1 270 6 1
net=GPMC_WEN:1
}
C 47000 50500 1 0 1 EMBEDDEDoutput-1.sym
[
L 46300 50500 46800 50500 3 0 0 0 -1 -1
L 46200 50600 46300 50500 3 0 0 0 -1 -1
L 46300 50700 46200 50600 3 0 0 0 -1 -1
L 46800 50700 46300 50700 3 0 0 0 -1 -1
L 46800 50700 46800 50500 3 0 0 0 -1 -1
P 47000 50600 46800 50600 1 0 0
{
T 46750 50550 5 6 0 0 0 6 1
pinseq=1
T 46750 50550 5 6 0 1 0 6 1
pinnumber=1
}
T 46900 50800 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 46900 50800 5 10 0 0 0 6 1
device=OUTPUT
T 46100 50500 5 10 1 1 0 6 1
value=PRU0_14_O
T 47000 50500 5 10 0 1 180 6 1
net=GPMC_AD12:1
}
C 47000 50000 1 0 1 EMBEDDEDoutput-1.sym
[
L 46300 50000 46800 50000 3 0 0 0 -1 -1
L 46200 50100 46300 50000 3 0 0 0 -1 -1
L 46300 50200 46200 50100 3 0 0 0 -1 -1
L 46800 50200 46300 50200 3 0 0 0 -1 -1
L 46800 50200 46800 50000 3 0 0 0 -1 -1
P 47000 50100 46800 50100 1 0 0
{
T 46750 50050 5 6 0 1 0 6 1
pinnumber=1
T 46750 50050 5 6 0 0 0 6 1
pinseq=1
}
T 46900 50300 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 46900 50300 5 10 0 0 0 6 1
device=OUTPUT
T 46100 50000 5 10 1 1 0 6 1
value=PRU0_15_O
T 47000 50000 5 10 0 1 180 6 1
net=GPMC_AD13:1
}
C 47000 48500 1 0 1 EMBEDDEDoutput-1.sym
[
L 46300 48500 46800 48500 3 0 0 0 -1 -1
L 46200 48600 46300 48500 3 0 0 0 -1 -1
L 46300 48700 46200 48600 3 0 0 0 -1 -1
L 46800 48700 46300 48700 3 0 0 0 -1 -1
L 46800 48700 46800 48500 3 0 0 0 -1 -1
P 47000 48600 46800 48600 1 0 0
{
T 46750 48550 5 6 0 1 0 6 1
pinnumber=1
T 46750 48550 5 6 0 0 0 6 1
pinseq=1
}
T 46900 48800 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 46900 48800 5 10 0 0 0 6 1
device=OUTPUT
T 46100 48500 5 10 1 1 0 6 1
value=GPIO1_2
T 47000 48500 5 10 0 1 180 6 1
net=GPMC_AD9:1
}
C 47000 49000 1 0 1 EMBEDDEDoutput-1.sym
[
L 46300 49000 46800 49000 3 0 0 0 -1 -1
L 46200 49100 46300 49000 3 0 0 0 -1 -1
L 46300 49200 46200 49100 3 0 0 0 -1 -1
L 46800 49200 46300 49200 3 0 0 0 -1 -1
L 46800 49200 46800 49000 3 0 0 0 -1 -1
P 47000 49100 46800 49100 1 0 0
{
T 46750 49050 5 6 0 0 0 6 1
pinseq=1
T 46750 49050 5 6 0 1 0 6 1
pinnumber=1
}
T 46900 49300 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 46900 49300 5 10 0 0 0 6 1
device=OUTPUT
T 46100 49000 5 10 1 1 0 6 1
value=GPIO1_3
T 47000 49000 5 10 0 1 180 6 1
net=GPMC_AD6:1
}
C 56000 50000 1 0 0 EMBEDDEDoutput-1.sym
[
T 56100 50300 5 10 0 0 0 0 1
device=OUTPUT
P 56000 50100 56200 50100 1 0 0
{
T 56250 50050 5 6 0 1 0 0 1
pinnumber=1
T 56250 50050 5 6 0 0 0 0 1
pinseq=1
}
L 56200 50200 56200 50000 3 0 0 0 -1 -1
L 56200 50200 56700 50200 3 0 0 0 -1 -1
L 56700 50200 56800 50100 3 0 0 0 -1 -1
L 56800 50100 56700 50000 3 0 0 0 -1 -1
L 56700 50000 56200 50000 3 0 0 0 -1 -1
]
{
T 56100 50300 5 10 0 0 0 0 1
device=OUTPUT
T 56800 50000 5 10 1 1 0 0 1
value=Target_Trst
T 56000 50000 5 10 0 1 180 0 1
net=SPI0_D0:1
}
C 47000 46700 1 180 0 EMBEDDEDoutput-1.sym
[
T 46900 46400 5 10 0 0 180 0 1
device=OUTPUT
P 47000 46600 46800 46600 1 0 0
{
T 46750 46650 5 6 0 1 180 0 1
pinnumber=1
T 46750 46650 5 6 0 0 180 0 1
pinseq=1
}
L 46800 46500 46800 46700 3 0 0 0 -1 -1
L 46800 46500 46300 46500 3 0 0 0 -1 -1
L 46300 46500 46200 46600 3 0 0 0 -1 -1
L 46200 46600 46300 46700 3 0 0 0 -1 -1
L 46300 46700 46800 46700 3 0 0 0 -1 -1
]
{
T 46900 46400 5 10 0 0 180 0 1
device=OUTPUT
T 45300 46500 5 10 1 1 0 0 1
value=GPIO1_16
T 47000 46700 5 10 0 1 0 0 1
net=JB6:1
}
C 47000 47200 1 180 0 EMBEDDEDoutput-1.sym
[
T 46900 46900 5 10 0 0 180 0 1
device=OUTPUT
P 47000 47100 46800 47100 1 0 0
{
T 46750 47150 5 6 0 1 180 0 1
pinnumber=1
T 46750 47150 5 6 0 0 180 0 1
pinseq=1
}
L 46800 47000 46800 47200 3 0 0 0 -1 -1
L 46800 47000 46300 47000 3 0 0 0 -1 -1
L 46300 47000 46200 47100 3 0 0 0 -1 -1
L 46200 47100 46300 47200 3 0 0 0 -1 -1
L 46300 47200 46800 47200 3 0 0 0 -1 -1
]
{
T 46900 46900 5 10 0 0 180 0 1
device=OUTPUT
T 45300 47000 5 10 1 1 0 0 1
value=GPIO1_15
T 47000 47200 5 10 0 1 0 0 1
net=JB6:1
}
C 47000 46200 1 180 0 EMBEDDEDoutput-1.sym
[
T 46900 45900 5 10 0 0 180 0 1
device=OUTPUT
P 47000 46100 46800 46100 1 0 0
{
T 46750 46150 5 6 0 1 180 0 1
pinnumber=1
T 46750 46150 5 6 0 0 180 0 1
pinseq=1
}
L 46800 46000 46800 46200 3 0 0 0 -1 -1
L 46800 46000 46300 46000 3 0 0 0 -1 -1
L 46300 46000 46200 46100 3 0 0 0 -1 -1
L 46200 46100 46300 46200 3 0 0 0 -1 -1
L 46300 46200 46800 46200 3 0 0 0 -1 -1
]
{
T 46900 45900 5 10 0 0 180 0 1
device=OUTPUT
T 45400 46000 5 10 1 1 0 0 1
value=GPIO1_17
T 47000 46200 5 10 0 1 0 0 1
net=JB6:1
}
N 45300 49600 47600 49600 4
N 53600 52400 53600 54000 4
C 58200 46800 1 0 0 EMBEDDEDgnd-1.sym
[
T 58500 46850 8 10 0 0 0 0 1
net=GND:1
L 58280 46810 58320 46810 3 0 0 0 -1 -1
L 58255 46850 58345 46850 3 0 0 0 -1 -1
L 58200 46900 58400 46900 3 0 0 0 -1 -1
P 58300 46900 58300 47100 1 0 1
{
T 58358 46961 5 4 0 1 0 0 1
pintype=pwr
T 58358 46961 5 4 0 1 0 0 1
pinlabel=1
T 58358 46961 5 4 0 0 0 0 1
pinseq=1
T 58358 46961 5 4 0 1 0 0 1
pinnumber=1
}
]
N 55600 47100 58300 47100 4
N 51700 44500 51700 44800 4
N 58300 47600 55600 47600 4
N 43800 47300 47000 47300 4
{
T 43900 47300 5 10 1 1 0 0 1
netname=CPLD_TDI
}
N 47000 47300 47000 47100 4
N 43800 46800 47000 46800 4
{
T 43900 46800 5 10 1 1 0 0 1
netname=CPLD_TMS
}
N 47000 46800 47000 46600 4
N 43800 46300 47000 46300 4
{
T 43900 46300 5 10 1 1 0 0 1
netname=CPLD_TCK
}
N 47000 46300 47000 46100 4
N 43300 51100 47600 51100 4
{
T 44800 51100 5 10 1 1 0 0 1
netname=CPLD_CLK
}
N 56000 46600 56000 46400 4
N 56000 46400 60200 46400 4
{
T 59100 46400 5 10 1 1 0 0 1
netname=CPLD_TDO
}
C 46000 44000 1 180 1 EMBEDDEDoutput-1.sym
[
T 46100 43700 5 10 0 0 180 6 1
device=OUTPUT
P 46000 43900 46200 43900 1 0 0
{
T 46250 43950 5 6 0 0 180 6 1
pinseq=1
T 46250 43950 5 6 0 1 180 6 1
pinnumber=1
}
L 46200 43800 46200 44000 3 0 0 0 -1 -1
L 46200 43800 46700 43800 3 0 0 0 -1 -1
L 46700 43800 46800 43900 3 0 0 0 -1 -1
L 46800 43900 46700 44000 3 0 0 0 -1 -1
L 46700 44000 46200 44000 3 0 0 0 -1 -1
]
{
T 46100 43700 5 10 0 0 180 6 1
device=OUTPUT
T 46900 44000 5 10 1 1 180 6 1
value=VCCINT
T 46000 44000 5 10 0 1 0 6 1
net=VCCINT:1
}
T 57500 57200 9 10 1 0 0 0 2


C 47100 44400 1 0 0 EMBEDDEDXC9536XL-VQ44.sym
[
T 47595 44795 8 10 0 1 0 0 1
footprint=VQFP44-0.8MM.fp
T 50595 48495 8 10 0 1 0 0 1
value=XC9536XL-xVQ44C
T 48295 52095 8 10 0 1 0 0 1
refdes=U?
P 55600 46100 55100 46100 1 0 0
{
T 55700 46100 5 10 0 0 0 0 1
pintype=unknown
T 55045 46095 5 10 1 1 0 6 1
pinlabel=IO2_13
T 55195 46145 5 10 1 1 0 0 1
pinnumber=23
T 55700 46100 5 10 0 0 0 0 1
pinseq=0
}
P 55600 46600 55100 46600 1 0 0
{
T 55700 46600 5 10 0 0 0 0 1
pintype=unknown
T 55045 46595 5 10 1 1 0 6 1
pinlabel=TDO
T 55195 46645 5 10 1 1 0 0 1
pinnumber=24
T 55700 46600 5 10 0 0 0 0 1
pinseq=0
}
P 55600 47100 55100 47100 1 0 0
{
T 55700 47100 5 10 0 0 0 0 1
pintype=unknown
T 55045 47095 5 10 1 1 0 6 1
pinlabel=GND
T 55195 47145 5 10 1 1 0 0 1
pinnumber=25
T 55700 47100 5 10 0 0 0 0 1
pinseq=0
}
P 55600 47600 55100 47600 1 0 0
{
T 55700 47600 5 10 0 0 0 0 1
pintype=unknown
T 55045 47595 5 10 1 1 0 6 1
pinlabel=Vccio
T 55195 47645 5 10 1 1 0 0 1
pinnumber=26
T 55700 47600 5 10 0 0 0 0 1
pinseq=0
}
P 55600 48100 55100 48100 1 0 0
{
T 55700 48100 5 10 0 0 0 0 1
pintype=unknown
T 55045 48095 5 10 1 1 0 6 1
pinlabel=IO2_12
T 55195 48145 5 10 1 1 0 0 1
pinnumber=27
T 55700 48100 5 10 0 0 0 0 1
pinseq=0
}
P 55600 48600 55100 48600 1 0 0
{
T 55700 48600 5 10 0 0 0 0 1
pintype=unknown
T 55045 48595 5 10 1 1 0 6 1
pinlabel=IO2_11
T 55195 48645 5 10 1 1 0 0 1
pinnumber=28
T 55700 48600 5 10 0 0 0 0 1
pinseq=0
}
P 55600 49100 55100 49100 1 0 0
{
T 55800 49100 5 10 0 0 0 0 1
pintype=unknown
T 55045 49095 5 10 1 1 0 6 1
pinlabel=IO2_10
T 55195 49145 5 10 1 1 0 0 1
pinnumber=29
T 55800 49100 5 10 0 0 0 0 1
pinseq=0
}
P 55600 49600 55100 49600 1 0 0
{
T 55800 49600 5 10 0 0 0 0 1
pintype=unknown
T 55045 49595 5 10 1 1 0 6 1
pinlabel=IO2_9
T 55195 49645 5 10 1 1 0 0 1
pinnumber=30
T 55800 49600 5 10 0 0 0 0 1
pinseq=0
}
P 55600 50100 55100 50100 1 0 0
{
T 55700 50100 5 10 0 0 0 0 1
pintype=unknown
T 55045 50095 5 10 1 1 0 6 1
pinlabel=IO2_8
T 55195 50145 5 10 1 1 0 0 1
pinnumber=31
T 55700 50100 5 10 0 0 0 0 1
pinseq=0
}
P 55600 50600 55100 50600 1 0 0
{
T 55600 50600 5 10 0 0 0 0 1
pintype=unknown
T 55045 50595 5 10 1 1 0 6 1
pinlabel=IO2_7
T 55195 50645 5 10 1 1 0 0 1
pinnumber=32
T 55600 50600 5 10 0 0 0 0 1
pinseq=0
}
P 55600 51100 55100 51100 1 0 0
{
T 55700 51100 5 10 0 0 0 0 1
pintype=unknown
T 55045 51095 5 10 1 1 0 6 1
pinlabel=2_7/GSR
T 55195 51145 5 10 1 1 0 0 1
pinnumber=33
T 55700 51100 5 10 0 0 0 0 1
pinseq=0
}
P 54200 44800 54200 45300 1 0 0
{
T 54200 44800 5 10 0 0 0 0 1
pintype=unknown
T 54200 45355 5 10 1 1 90 0 1
pinlabel=IO2_14
T 54150 45205 5 10 1 1 90 6 1
pinnumber=22
T 54200 44800 5 10 0 0 0 0 1
pinseq=0
}
P 53700 44800 53700 45300 1 0 0
{
T 53700 44800 5 10 0 0 0 0 1
pintype=unknown
T 53700 45355 5 10 1 1 90 0 1
pinlabel=IO2_15
T 53650 45205 5 10 1 1 90 6 1
pinnumber=21
T 53700 44800 5 10 0 0 0 0 1
pinseq=0
}
P 53200 44800 53200 45300 1 0 0
{
T 53200 44800 5 10 0 0 0 0 1
pintype=unknown
T 53200 45355 5 10 1 1 90 0 1
pinlabel=IO2_16
T 53150 45205 5 10 1 1 90 6 1
pinnumber=20
T 53200 44800 5 10 0 0 0 0 1
pinseq=0
}
P 52700 44800 52700 45300 1 0 0
{
T 52700 44700 5 10 0 0 0 0 1
pintype=unknown
T 52700 45355 5 10 1 1 90 0 1
pinlabel=IO2_17
T 52650 45205 5 10 1 1 90 6 1
pinnumber=19
T 52700 44700 5 10 0 0 0 0 1
pinseq=0
}
P 52200 44800 52200 45300 1 0 0
{
T 52200 44700 5 10 0 0 0 0 1
pintype=unknown
T 52200 45355 5 10 1 1 90 0 1
pinlabel=IO1_17
T 52150 45205 5 10 1 1 90 6 1
pinnumber=18
T 52200 44700 5 10 0 0 0 0 1
pinseq=0
}
P 51700 44800 51700 45300 1 0 0
{
T 51700 44800 5 10 0 0 0 0 1
pintype=unknown
T 51700 45355 5 10 1 1 90 0 1
pinlabel=GND
T 51650 45205 5 10 1 1 90 6 1
pinnumber=17
T 51700 44800 5 10 0 0 0 0 1
pinseq=0
}
P 51200 44800 51200 45300 1 0 0
{
T 51200 44800 5 10 0 0 0 0 1
pintype=unknown
T 51200 45355 5 10 1 1 90 0 1
pinlabel=IO1_16
T 51150 45205 5 10 1 1 90 6 1
pinnumber=16
T 51200 44800 5 10 0 0 0 0 1
pinseq=0
}
P 50700 44800 50700 45300 1 0 0
{
T 50700 44800 5 10 0 0 0 0 1
pintype=unknown
T 50700 45355 5 10 1 1 90 0 1
pinlabel=Vccint
T 50650 45205 5 10 1 1 90 6 1
pinnumber=15
T 50700 44800 5 10 0 0 0 0 1
pinseq=0
}
P 50200 44800 50200 45300 1 0 0
{
T 50200 44800 5 10 0 0 0 0 1
pintype=unknown
T 50200 45355 5 10 1 1 90 0 1
pinlabel=IO1_15
T 50150 45205 5 10 1 1 90 6 1
pinnumber=14
T 50200 44800 5 10 0 0 0 0 1
pinseq=0
}
P 49700 44800 49700 45300 1 0 0
{
T 49700 44800 5 10 0 0 0 0 1
pintype=unknown
T 49700 45355 5 10 1 1 90 0 1
pinlabel=IO1_14
T 49650 45205 5 10 1 1 90 6 1
pinnumber=13
T 49700 44800 5 10 0 0 0 0 1
pinseq=0
}
P 49200 44800 49200 45300 1 0 0
{
T 49200 44800 5 10 0 0 0 0 1
pintype=unknown
T 49200 45355 5 10 1 1 90 0 1
pinlabel=IO1_13
T 49150 45205 5 10 1 1 90 6 1
pinnumber=12
T 49200 44800 5 10 0 0 0 0 1
pinseq=0
}
P 54100 52400 54100 51900 1 0 0
{
T 54100 52400 5 10 0 0 0 0 1
pintype=unknown
T 54100 51845 5 10 1 1 90 6 1
pinlabel=2_5/GTS2
T 54050 51995 5 10 1 1 90 0 1
pinnumber=34
T 54100 52400 5 10 0 0 0 0 1
pinseq=0
}
P 53600 52400 53600 51900 1 0 0
{
T 53600 52400 5 10 0 0 0 0 1
pintype=unknown
T 53600 51845 5 10 1 1 90 6 1
pinlabel=Vccint
T 53550 51995 5 10 1 1 90 0 1
pinnumber=35
T 53600 52400 5 10 0 0 0 0 1
pinseq=0
}
P 53100 52400 53100 51900 1 0 0
{
T 53100 52400 5 10 0 0 0 0 1
pintype=unknown
T 53100 51845 5 10 1 1 90 6 1
pinlabel=2_3/GTS1
T 53050 51995 5 10 1 1 90 0 1
pinnumber=36
T 53100 52400 5 10 0 0 0 0 1
pinseq=0
}
P 52600 52400 52600 51900 1 0 0
{
T 52600 52400 5 10 0 0 0 0 1
pintype=unknown
T 52600 51845 5 10 1 1 90 6 1
pinlabel=IO2_4
T 52550 51995 5 10 1 1 90 0 1
pinnumber=37
T 52600 52400 5 10 0 0 0 0 1
pinseq=0
}
P 52100 52400 52100 51900 1 0 0
{
T 52100 52400 5 10 0 0 0 0 1
pintype=unknown
T 52100 51845 5 10 1 1 90 6 1
pinlabel=IO2_2
T 52050 51995 5 10 1 1 90 0 1
pinnumber=38
T 52100 52400 5 10 0 0 0 0 1
pinseq=0
}
P 51600 52400 51600 51900 1 0 0
{
T 51600 52400 5 10 0 0 0 0 1
pintype=unknown
T 51600 51845 5 10 1 1 90 6 1
pinlabel=IO2_1
T 51550 51995 5 10 1 1 90 0 1
pinnumber=39
T 51600 52400 5 10 0 0 0 0 1
pinseq=0
}
P 51100 52400 51100 51900 1 0 0
{
T 51100 52400 5 10 0 0 0 0 1
pintype=unknown
T 51100 51845 5 10 1 1 90 6 1
pinlabel=IO1_1
T 51050 51995 5 10 1 1 90 0 1
pinnumber=40
T 51100 52400 5 10 0 0 0 0 1
pinseq=0
}
P 50600 52400 50600 51900 1 0 0
{
T 50600 52400 5 10 0 0 0 0 1
pintype=unknown
T 50600 51845 5 10 1 1 90 6 1
pinlabel=IO1_2
T 50550 51995 5 10 1 1 90 0 1
pinnumber=41
T 50600 52400 5 10 0 0 0 0 1
pinseq=0
}
P 50100 52400 50100 51900 1 0 0
{
T 50100 52400 5 10 0 0 0 0 1
pintype=unknown
T 50100 51845 5 10 1 1 90 6 1
pinlabel=IO1_4
T 50050 51995 5 10 1 1 90 0 1
pinnumber=42
T 50100 52400 5 10 0 0 0 0 1
pinseq=0
}
P 49600 52400 49600 51900 1 0 0
{
T 49600 52400 5 10 0 0 0 0 1
pintype=unknown
T 49600 51845 5 10 1 1 90 6 1
pinlabel=1_3/GCK1
T 49550 51995 5 10 1 1 90 0 1
pinnumber=43
T 49600 52400 5 10 0 0 0 0 1
pinseq=0
}
P 49100 52400 49100 51900 1 0 0
{
T 49100 52300 5 10 0 0 0 0 1
pintype=unknown
T 49100 51845 5 10 1 1 90 6 1
pinlabel=1_5/GCK2
T 49050 51995 5 10 1 1 90 0 1
pinnumber=44
T 49100 52300 5 10 0 0 0 0 1
pinseq=0
}
P 47600 46100 48100 46100 1 0 0
{
T 47600 46100 5 10 0 0 0 0 1
pintype=unknown
T 48155 46095 5 10 1 1 0 0 1
pinlabel=TCK
T 48005 46145 5 10 1 1 0 6 1
pinnumber=11
T 47600 46100 5 10 0 0 0 0 1
pinseq=0
}
P 47600 46600 48100 46600 1 0 0
{
T 47600 46600 5 10 0 0 0 0 1
pintype=unknown
T 48155 46595 5 10 1 1 0 0 1
pinlabel=TMS
T 48005 46645 5 10 1 1 0 6 1
pinnumber=10
T 47600 46600 5 10 0 0 0 0 1
pinseq=0
}
P 47600 47100 48100 47100 1 0 0
{
T 47600 47100 5 10 0 0 0 0 1
pintype=unknown
T 48155 47095 5 10 1 1 0 0 1
pinlabel=TDI
T 48005 47145 5 10 1 1 0 6 1
pinnumber=9
T 47600 47100 5 10 0 0 0 0 1
pinseq=0
}
P 47600 47600 48100 47600 1 0 0
{
T 47600 47600 5 10 0 0 0 0 1
pintype=unknown
T 48155 47595 5 10 1 1 0 0 1
pinlabel=IO1_12
T 48005 47645 5 10 1 1 0 6 1
pinnumber=8
T 47600 47600 5 10 0 0 0 0 1
pinseq=0
}
P 47600 48100 48100 48100 1 0 0
{
T 47600 48100 5 10 0 0 0 0 1
pintype=unknown
T 48155 48095 5 10 1 1 0 0 1
pinlabel=IO1_11
T 48005 48145 5 10 1 1 0 6 1
pinnumber=7
T 47600 48100 5 10 0 0 0 0 1
pinseq=0
}
P 47600 48600 48100 48600 1 0 0
{
T 47600 48600 5 10 0 0 0 0 1
pintype=unknown
T 48155 48595 5 10 1 1 0 0 1
pinlabel=IO1_10
T 48005 48645 5 10 1 1 0 6 1
pinnumber=6
T 47600 48600 5 10 0 0 0 0 1
pinseq=0
}
P 47600 49100 48100 49100 1 0 0
{
T 47600 49100 5 10 0 0 0 0 1
pintype=unknown
T 48155 49095 5 10 1 1 0 0 1
pinlabel=IO1_9
T 48005 49145 5 10 1 1 0 6 1
pinnumber=5
T 47600 49100 5 10 0 0 0 0 1
pinseq=0
}
P 47600 49600 48100 49600 1 0 0
{
T 47600 49600 5 10 0 0 0 0 1
pintype=unknown
T 48155 49595 5 10 1 1 0 0 1
pinlabel=GND
T 48005 49645 5 10 1 1 0 6 1
pinnumber=4
T 47600 49600 5 10 0 0 0 0 1
pinseq=0
}
P 47600 50100 48100 50100 1 0 0
{
T 47600 50100 5 10 0 0 0 0 1
pintype=unknown
T 48155 50095 5 10 1 1 0 0 1
pinlabel=IO1_8
T 48005 50145 5 10 1 1 0 6 1
pinnumber=3
T 47600 50100 5 10 0 0 0 0 1
pinseq=0
}
P 47600 50600 48100 50600 1 0 0
{
T 47600 50600 5 10 0 0 0 0 1
pintype=unknown
T 48155 50595 5 10 1 1 0 0 1
pinlabel=IO1_6
T 48005 50645 5 10 1 1 0 6 1
pinnumber=2
T 47600 50600 5 10 0 0 0 0 1
pinseq=0
}
P 47600 51100 48100 51100 1 0 0
{
T 47600 51100 5 10 0 0 0 0 1
pintype=unknown
T 48155 51095 5 10 1 1 0 0 1
pinlabel=IO/GCK3
T 48005 51145 5 10 1 1 0 6 1
pinnumber=1
T 47600 51100 5 10 0 0 0 0 1
pinseq=0
}
B 48100 45300 7000 6600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
]
{
T 48295 52095 5 10 1 1 0 0 1
refdes=U301
T 50595 48495 5 10 1 1 0 0 1
value=XC9536XL-xVQ44C
T 47595 44795 5 10 0 1 0 0 1
footprint=VQFP44-0.8MM.fp
}
C 45900 55200 1 0 0 EMBEDDEDoutput-1.sym
[
T 46000 55500 5 10 0 0 0 0 1
device=OUTPUT
P 45900 55300 46100 55300 1 0 0
{
T 46150 55250 5 6 0 0 0 0 1
pinseq=1
T 46150 55250 5 6 0 1 0 0 1
pinnumber=1
}
L 46100 55400 46100 55200 3 0 0 0 -1 -1
L 46100 55400 46600 55400 3 0 0 0 -1 -1
L 46600 55400 46700 55300 3 0 0 0 -1 -1
L 46700 55300 46600 55200 3 0 0 0 -1 -1
L 46600 55200 46100 55200 3 0 0 0 -1 -1
]
{
T 46000 55500 5 10 0 0 0 0 1
device=OUTPUT
T 46700 55200 5 10 1 1 0 0 1
value=GPIO1_16
T 45900 55200 5 10 0 1 180 0 1
net=SPI0_D0:1
}
C 45900 54400 1 0 0 EMBEDDEDoutput-1.sym
[
T 46000 54700 5 10 0 0 0 0 1
device=OUTPUT
P 45900 54500 46100 54500 1 0 0
{
T 46150 54450 5 6 0 0 0 0 1
pinseq=1
T 46150 54450 5 6 0 1 0 0 1
pinnumber=1
}
L 46100 54600 46100 54400 3 0 0 0 -1 -1
L 46100 54600 46600 54600 3 0 0 0 -1 -1
L 46600 54600 46700 54500 3 0 0 0 -1 -1
L 46700 54500 46600 54400 3 0 0 0 -1 -1
L 46600 54400 46100 54400 3 0 0 0 -1 -1
]
{
T 46000 54700 5 10 0 0 0 0 1
device=OUTPUT
T 46700 54400 5 10 1 1 0 0 1
value=GPIO1_15
T 45900 54400 5 10 0 1 180 0 1
net=SPI0_D0:1
}
C 45900 53700 1 0 0 EMBEDDEDoutput-1.sym
[
T 46000 54000 5 10 0 0 0 0 1
device=OUTPUT
P 45900 53800 46100 53800 1 0 0
{
T 46150 53750 5 6 0 0 0 0 1
pinseq=1
T 46150 53750 5 6 0 1 0 0 1
pinnumber=1
}
L 46100 53900 46100 53700 3 0 0 0 -1 -1
L 46100 53900 46600 53900 3 0 0 0 -1 -1
L 46600 53900 46700 53800 3 0 0 0 -1 -1
L 46700 53800 46600 53700 3 0 0 0 -1 -1
L 46600 53700 46100 53700 3 0 0 0 -1 -1
]
{
T 46000 54000 5 10 0 0 0 0 1
device=OUTPUT
T 46700 53700 5 10 1 1 0 0 1
value=GPIO1_14
T 45900 53700 5 10 0 1 180 0 1
net=SPI0_D0:1
}
C 45900 52900 1 0 0 EMBEDDEDoutput-1.sym
[
T 46000 53200 5 10 0 0 0 0 1
device=OUTPUT
P 45900 53000 46100 53000 1 0 0
{
T 46150 52950 5 6 0 0 0 0 1
pinseq=1
T 46150 52950 5 6 0 1 0 0 1
pinnumber=1
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L 46100 53100 46100 52900 3 0 0 0 -1 -1
L 46100 53100 46600 53100 3 0 0 0 -1 -1
L 46600 53100 46700 53000 3 0 0 0 -1 -1
L 46700 53000 46600 52900 3 0 0 0 -1 -1
L 46600 52900 46100 52900 3 0 0 0 -1 -1
]
{
T 46000 53200 5 10 0 0 0 0 1
device=OUTPUT
T 46700 52900 5 10 1 1 0 0 1
value=GPIO1_17
T 45900 52900 5 10 0 1 180 0 1
net=SPI0_D0:1
}
N 42200 52100 43300 52100 4
C 41700 51000 1 0 0 EMBEDDEDfxo-hc73.sym
[
P 43300 51100 43000 51100 1 0 0
{
T 43300 51100 5 8 0 0 0 0 1
pintype=pas
T 42945 51095 5 8 1 1 0 6 1
pinlabel=out
T 43095 51145 5 8 1 1 0 0 1
pinnumber=3
T 43300 51100 5 8 0 0 0 0 1
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}
P 43000 51400 43300 51400 1 0 1
{
T 43095 51445 5 8 1 1 0 0 1
pinnumber=4
T 42450 51350 5 8 0 0 0 0 1
pinseq=4
T 42945 51395 5 8 1 1 0 6 1
pinlabel=vdd
T 42450 51350 5 8 0 1 0 0 1
pintype=pas
}
T 42000 51600 8 10 0 1 0 0 1
refdes=U?
B 42000 51000 1000 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 42000 51400 41700 51400 1 0 1
{
T 41905 51445 5 8 1 1 0 6 1
pinnumber=1
T 42550 51350 5 8 0 0 0 6 1
pinseq=1
T 42055 51395 5 8 1 1 0 0 1
pinlabel=ena
T 42550 51350 5 8 0 1 0 6 1
pintype=pas
}
P 42000 51100 41700 51100 1 0 1
{
T 41905 51145 5 8 1 1 0 6 1
pinnumber=2
T 42550 51050 5 8 0 0 0 6 1
pinseq=2
T 42055 51095 5 8 1 1 0 0 1
pinlabel=gnd
T 42550 51050 5 8 0 1 0 6 1
pintype=pas
}
T 40000 49500 5 10 0 0 0 0 1
device=fxo-hc73
]
{
T 40000 49500 5 10 0 0 0 0 1
device=fxo-hc73
T 42000 51600 5 10 1 1 0 0 1
refdes=X301
T 42100 50800 5 10 1 1 0 0 1
value=FXO-HC73-100
T 41700 51000 5 10 0 0 0 0 1
footprint=xtal_can50
}
C 41200 50800 1 0 0 EMBEDDEDgnd-1.sym
[
L 41280 50810 41320 50810 3 0 0 0 -1 -1
L 41255 50850 41345 50850 3 0 0 0 -1 -1
L 41200 50900 41400 50900 3 0 0 0 -1 -1
P 41300 50900 41300 51100 1 0 1
{
T 41358 50961 5 4 0 1 0 0 1
pintype=pwr
T 41358 50961 5 4 0 1 0 0 1
pinlabel=1
T 41358 50961 5 4 0 0 0 0 1
pinseq=1
T 41358 50961 5 4 0 1 0 0 1
pinnumber=1
}
T 41500 50850 8 10 0 0 0 0 1
net=GND:1
]
N 43300 51400 43300 52100 4
N 41300 51100 41700 51100 4
T 41400 51200 9 10 1 0 0 0 2
N/C

C 45200 43000 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 44300 43200 5 10 0 0 90 0 1
symversion=0.1
T 44100 43200 5 10 0 0 90 0 1
numslots=0
T 43900 43200 5 10 0 0 90 0 1
description=capacitor
T 44700 43200 8 10 0 1 90 0 1
refdes=C?
T 44500 43200 5 10 0 0 90 0 1
device=CAPACITOR
L 45000 43400 45000 43200 3 0 0 0 -1 -1
L 45000 43700 45000 43500 3 0 0 0 -1 -1
L 44800 43500 45200 43500 3 0 0 0 -1 -1
L 44800 43400 45200 43400 3 0 0 0 -1 -1
P 45000 43900 45000 43700 1 0 0
{
T 45000 43700 5 8 0 1 90 8 1
pintype=pas
T 45000 43700 9 8 0 1 90 6 1
pinlabel=2
T 45050 43750 5 8 0 1 90 2 1
pinseq=2
T 44950 43750 5 8 0 1 90 0 1
pinnumber=2
}
P 45000 43000 45000 43200 1 0 0
{
T 45000 43200 5 8 0 1 90 2 1
pintype=pas
T 45000 43200 9 8 0 1 90 0 1
pinlabel=1
T 45050 43150 5 8 0 1 90 8 1
pinseq=1
T 44950 43150 5 8 0 1 90 6 1
pinnumber=1
}
]
{
T 44500 43200 5 10 0 0 90 0 1
device=CAPACITOR
T 44800 43600 5 10 1 1 180 0 1
refdes=C304
T 44300 43200 5 10 0 0 90 0 1
symversion=0.1
T 44300 43200 5 10 1 1 0 0 1
value=0.1uf
T 45200 43000 5 10 0 0 0 0 1
footprint=0603
}
C 49700 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 49600 52900 49600 53100 1 0 0
{
T 49650 53150 5 6 0 0 90 0 1
pinseq=1
T 49650 53150 5 6 0 1 90 0 1
pinnumber=1
}
L 49500 53100 49700 53100 3 0 0 0 -1 -1
L 49500 53100 49500 53600 3 0 0 0 -1 -1
L 49500 53600 49600 53700 3 0 0 0 -1 -1
L 49600 53700 49700 53600 3 0 0 0 -1 -1
L 49700 53600 49700 53100 3 0 0 0 -1 -1
T 49400 53000 5 10 0 0 90 0 1
device=OUTPUT
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{
T 49400 53000 5 10 0 0 90 0 1
device=OUTPUT
T 49700 53700 5 10 1 1 90 0 1
value=PRU1_16_I
T 49700 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
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N 55600 46600 56000 46600 4
N 47000 46100 47600 46100 4
N 47000 46600 47600 46600 4
N 47000 47100 47600 47100 4
N 47000 47600 47600 47600 4
N 47000 48100 47600 48100 4
N 47000 48600 47600 48600 4
N 47000 49100 47600 49100 4
N 47000 50100 47600 50100 4
N 47000 50600 47600 50600 4
C 50200 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 50100 52900 50100 53100 1 0 0
{
T 50150 53150 5 6 0 0 90 0 1
pinseq=1
T 50150 53150 5 6 0 1 90 0 1
pinnumber=1
}
L 50000 53100 50200 53100 3 0 0 0 -1 -1
L 50000 53100 50000 53600 3 0 0 0 -1 -1
L 50000 53600 50100 53700 3 0 0 0 -1 -1
L 50100 53700 50200 53600 3 0 0 0 -1 -1
L 50200 53600 50200 53100 3 0 0 0 -1 -1
T 49900 53000 5 10 0 0 90 0 1
device=OUTPUT
]
{
T 49900 53000 5 10 0 0 90 0 1
device=OUTPUT
T 50200 53700 5 10 1 1 90 0 1
value=PRU1_10
T 50200 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
}
C 50700 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 50600 52900 50600 53100 1 0 0
{
T 50650 53150 5 6 0 0 90 0 1
pinseq=1
T 50650 53150 5 6 0 1 90 0 1
pinnumber=1
}
L 50500 53100 50700 53100 3 0 0 0 -1 -1
L 50500 53100 50500 53600 3 0 0 0 -1 -1
L 50500 53600 50600 53700 3 0 0 0 -1 -1
L 50600 53700 50700 53600 3 0 0 0 -1 -1
L 50700 53600 50700 53100 3 0 0 0 -1 -1
T 50400 53000 5 10 0 0 90 0 1
device=OUTPUT
]
{
T 50400 53000 5 10 0 0 90 0 1
device=OUTPUT
T 50700 53700 5 10 1 1 90 0 1
value=PRU1_11
T 50700 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
}
C 51700 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 51600 52900 51600 53100 1 0 0
{
T 51650 53150 5 6 0 0 90 0 1
pinseq=1
T 51650 53150 5 6 0 1 90 0 1
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L 51500 53100 51700 53100 3 0 0 0 -1 -1
L 51500 53100 51500 53600 3 0 0 0 -1 -1
L 51500 53600 51600 53700 3 0 0 0 -1 -1
L 51600 53700 51700 53600 3 0 0 0 -1 -1
L 51700 53600 51700 53100 3 0 0 0 -1 -1
T 51400 53000 5 10 0 0 90 0 1
device=OUTPUT
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{
T 51400 53000 5 10 0 0 90 0 1
device=OUTPUT
T 51700 53700 5 10 1 1 90 0 1
value=PRU1_6
T 51700 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
}
C 51200 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 51100 52900 51100 53100 1 0 0
{
T 51150 53150 5 6 0 0 90 0 1
pinseq=1
T 51150 53150 5 6 0 1 90 0 1
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L 51000 53100 51200 53100 3 0 0 0 -1 -1
L 51000 53100 51000 53600 3 0 0 0 -1 -1
L 51000 53600 51100 53700 3 0 0 0 -1 -1
L 51100 53700 51200 53600 3 0 0 0 -1 -1
L 51200 53600 51200 53100 3 0 0 0 -1 -1
T 50900 53000 5 10 0 0 90 0 1
device=OUTPUT
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{
T 50900 53000 5 10 0 0 90 0 1
device=OUTPUT
T 51200 53700 5 10 1 1 90 0 1
value=PRU1_7
T 51200 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
}
C 52700 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 52600 52900 52600 53100 1 0 0
{
T 52650 53150 5 6 0 0 90 0 1
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T 52650 53150 5 6 0 1 90 0 1
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L 52500 53100 52700 53100 3 0 0 0 -1 -1
L 52500 53100 52500 53600 3 0 0 0 -1 -1
L 52500 53600 52600 53700 3 0 0 0 -1 -1
L 52600 53700 52700 53600 3 0 0 0 -1 -1
L 52700 53600 52700 53100 3 0 0 0 -1 -1
T 52400 53000 5 10 0 0 90 0 1
device=OUTPUT
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{
T 52400 53000 5 10 0 0 90 0 1
device=OUTPUT
T 52700 53700 5 10 1 1 90 0 1
value=PRU1_4
T 52700 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
}
C 52200 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 52100 52900 52100 53100 1 0 0
{
T 52150 53150 5 6 0 0 90 0 1
pinseq=1
T 52150 53150 5 6 0 1 90 0 1
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L 52000 53100 52200 53100 3 0 0 0 -1 -1
L 52000 53100 52000 53600 3 0 0 0 -1 -1
L 52000 53600 52100 53700 3 0 0 0 -1 -1
L 52100 53700 52200 53600 3 0 0 0 -1 -1
L 52200 53600 52200 53100 3 0 0 0 -1 -1
T 51900 53000 5 10 0 0 90 0 1
device=OUTPUT
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{
T 51900 53000 5 10 0 0 90 0 1
device=OUTPUT
T 52200 53700 5 10 1 1 90 0 1
value=PRU1_5
T 52200 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
}
C 54200 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 54100 52900 54100 53100 1 0 0
{
T 54150 53150 5 6 0 0 90 0 1
pinseq=1
T 54150 53150 5 6 0 1 90 0 1
pinnumber=1
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L 54000 53100 54200 53100 3 0 0 0 -1 -1
L 54000 53100 54000 53600 3 0 0 0 -1 -1
L 54000 53600 54100 53700 3 0 0 0 -1 -1
L 54100 53700 54200 53600 3 0 0 0 -1 -1
L 54200 53600 54200 53100 3 0 0 0 -1 -1
T 53900 53000 5 10 0 0 90 0 1
device=OUTPUT
]
{
T 53900 53000 5 10 0 0 90 0 1
device=OUTPUT
T 54200 53700 5 10 1 1 90 0 1
value=PRU1_2
T 54200 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
}
C 53200 52900 1 90 0 EMBEDDEDoutput-1.sym
[
P 53100 52900 53100 53100 1 0 0
{
T 53150 53150 5 6 0 0 90 0 1
pinseq=1
T 53150 53150 5 6 0 1 90 0 1
pinnumber=1
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L 53000 53100 53200 53100 3 0 0 0 -1 -1
L 53000 53100 53000 53600 3 0 0 0 -1 -1
L 53000 53600 53100 53700 3 0 0 0 -1 -1
L 53100 53700 53200 53600 3 0 0 0 -1 -1
L 53200 53600 53200 53100 3 0 0 0 -1 -1
T 52900 53000 5 10 0 0 90 0 1
device=OUTPUT
]
{
T 52900 53000 5 10 0 0 90 0 1
device=OUTPUT
T 53200 53700 5 10 1 1 90 0 1
value=PRU1_3
T 53200 52900 5 10 0 1 270 0 1
net=SPI0_D0:1
}
C 49800 44500 1 90 1 EMBEDDEDoutput-1.sym
[
L 49800 43800 49800 44300 3 0 0 0 -1 -1
L 49700 43700 49800 43800 3 0 0 0 -1 -1
L 49600 43800 49700 43700 3 0 0 0 -1 -1
L 49600 44300 49600 43800 3 0 0 0 -1 -1
L 49600 44300 49800 44300 3 0 0 0 -1 -1
P 49700 44500 49700 44300 1 0 0
{
T 49750 44250 5 6 0 1 90 6 1
pinnumber=1
T 49750 44250 5 6 0 0 90 6 1
pinseq=1
}
T 49500 44400 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 49500 44400 5 10 0 0 90 6 1
device=OUTPUT
T 49800 43600 5 10 1 1 90 6 1
value=PRU0_7
T 49800 44500 5 10 0 1 270 6 1
net=GPMC_WEN:1
}
C 50300 44500 1 90 1 EMBEDDEDoutput-1.sym
[
L 50300 43800 50300 44300 3 0 0 0 -1 -1
L 50200 43700 50300 43800 3 0 0 0 -1 -1
L 50100 43800 50200 43700 3 0 0 0 -1 -1
L 50100 44300 50100 43800 3 0 0 0 -1 -1
L 50100 44300 50300 44300 3 0 0 0 -1 -1
P 50200 44500 50200 44300 1 0 0
{
T 50250 44250 5 6 0 1 90 6 1
pinnumber=1
T 50250 44250 5 6 0 0 90 6 1
pinseq=1
}
T 50000 44400 5 10 0 0 90 6 1
device=OUTPUT
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{
T 50000 44400 5 10 0 0 90 6 1
device=OUTPUT
T 50300 43600 5 10 1 1 90 6 1
value=PRU0_5
T 50300 44500 5 10 0 1 270 6 1
net=GPMC_WEN:1
}
C 50800 44500 1 90 1 EMBEDDEDoutput-1.sym
[
L 50800 43800 50800 44300 3 0 0 0 -1 -1
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L 50600 43800 50700 43700 3 0 0 0 -1 -1
L 50600 44300 50600 43800 3 0 0 0 -1 -1
L 50600 44300 50800 44300 3 0 0 0 -1 -1
P 50700 44500 50700 44300 1 0 0
{
T 50750 44250 5 6 0 1 90 6 1
pinnumber=1
T 50750 44250 5 6 0 0 90 6 1
pinseq=1
}
T 50500 44400 5 10 0 0 90 6 1
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]
{
T 50500 44400 5 10 0 0 90 6 1
device=OUTPUT
T 50800 43600 5 10 1 1 90 6 1
value=VCCINT
T 50800 44500 5 10 0 1 270 6 1
net=GPMC_WEN:1
}
C 51300 44500 1 90 1 EMBEDDEDoutput-1.sym
[
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L 51100 43800 51200 43700 3 0 0 0 -1 -1
L 51100 44300 51100 43800 3 0 0 0 -1 -1
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P 51200 44500 51200 44300 1 0 0
{
T 51250 44250 5 6 0 1 90 6 1
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T 51250 44250 5 6 0 0 90 6 1
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}
T 51000 44400 5 10 0 0 90 6 1
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{
T 51000 44400 5 10 0 0 90 6 1
device=OUTPUT
T 51300 43600 5 10 1 1 90 6 1
value=PRU0_3
T 51300 44500 5 10 0 1 270 6 1
net=GPMC_WEN:1
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C 52300 44500 1 90 1 EMBEDDEDoutput-1.sym
[
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P 52200 44500 52200 44300 1 0 0
{
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T 52250 44250 5 6 0 0 90 6 1
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}
T 52000 44400 5 10 0 0 90 6 1
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{
T 52000 44400 5 10 0 0 90 6 1
device=OUTPUT
T 52300 43600 5 10 1 1 90 6 1
value=PRU0_1
T 52300 44500 5 10 0 1 270 6 1
net=GPMC_WEN:1
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C 52800 44500 1 90 1 EMBEDDEDoutput-1.sym
[
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L 52600 43800 52700 43700 3 0 0 0 -1 -1
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P 52700 44500 52700 44300 1 0 0
{
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T 52500 44400 5 10 0 0 90 6 1
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{
T 52500 44400 5 10 0 0 90 6 1
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T 52800 43600 5 10 1 1 90 6 1
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T 52800 44500 5 10 0 1 270 6 1
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C 53300 44500 1 90 1 EMBEDDEDoutput-1.sym
[
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P 53200 44500 53200 44300 1 0 0
{
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T 53000 44400 5 10 0 0 90 6 1
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{
T 53000 44400 5 10 0 0 90 6 1
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T 53300 43600 5 10 1 1 90 6 1
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T 53300 44500 5 10 0 1 270 6 1
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C 53800 44500 1 90 1 EMBEDDEDoutput-1.sym
[
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P 53700 44500 53700 44300 1 0 0
{
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T 53500 44400 5 10 0 0 90 6 1
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{
T 53500 44400 5 10 0 0 90 6 1
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T 53800 43600 5 10 1 1 90 6 1
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T 53800 44500 5 10 0 1 270 6 1
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C 54300 44500 1 90 1 EMBEDDEDoutput-1.sym
[
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{
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T 54000 44400 5 10 0 0 90 6 1
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{
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device=OUTPUT
T 54300 43600 5 10 1 1 90 6 1
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C 56000 48500 1 0 0 EMBEDDEDoutput-1.sym
[
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{
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C 56000 48000 1 0 0 EMBEDDEDoutput-1.sym
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{
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C 56000 50500 1 0 0 EMBEDDEDoutput-1.sym
[
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{
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C 56000 51000 1 0 0 EMBEDDEDoutput-1.sym
[
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{
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T 56800 51000 5 10 1 1 0 0 1
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C 56000 46000 1 0 0 EMBEDDEDoutput-1.sym
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