Merge pull request #115 from litex-hub/fix-cscontrol-switch-glitch

cscontrol: Keep different chip-select asserted

Author: enjoy-digital

litespi/cscontrol.py

@@ -14,23 +14,27 @@ class LiteSPICSControl(LiteXModule):
     def __init__(self, pads, cs, cs_delay=10, with_sdr_cs=True, **kwargs):
         self.enable = enable = Signal()
         cs_n = Signal().like(pads.cs_n)
-        last_cs = Signal()
+        last_cs = Signal().like(cs)
 
         self.timer = timer  = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
 
         if len(pads.cs_n) > 1:
-            # Remember last active CS when multiple CS lines are used, so we only wait when
-            # the same CS line is active again
+            # Remember the last completed CS selection, so the delay only applies when the same
+            # CS line is selected again. Update it after the transfer to keep a different-CS
+            # bypass active for the complete transfer.
             last_active_cs = Signal(len(cs))
-            self.sync += If(enable, last_active_cs.eq(cs))
+            self.sync += If((cs == 0) & (last_cs != 0),
+                last_active_cs.eq(last_cs)
+            )
 
             enable_cond = timer.done | (last_active_cs != cs)
         else:
             enable_cond = timer.done
 
-        self.sync += last_cs.eq(cs != 0)
+        self.sync += last_cs.eq(cs)
 
-        self.comb += timer.wait.eq(~((cs == 0) & last_cs)) # Reset wait on falling edge of cs
+        # Reset wait on falling edge of CS.
+        self.comb += timer.wait.eq(~((cs == 0) & (last_cs != 0)))
         self.comb += enable.eq((cs != 0) & enable_cond)
         self.comb += cs_n.eq(~(Replicate(enable, len(pads.cs_n)) & cs))
 

test/test_cscontrol.py

@@ -0,0 +1,85 @@
+#
+# This file is part of LiteSPI.
+#
+# Copyright (c) 2026 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import unittest
+
+from migen import *
+
+from litespi.cscontrol import LiteSPICSControl
+
+
+class _LiteSPICSControlDUT(Module):
+    def __init__(self, cs_delay=4):
+        self.pads = pads = Record([
+            ("cs_n", 2),
+        ])
+        self.cs = cs = Signal(2)
+
+        self.submodules.cs_control = LiteSPICSControl(
+            pads        = pads,
+            cs          = cs,
+            cs_delay    = cs_delay,
+            with_sdr_cs = False,
+        )
+
+
+class TestLiteSPICSControl(unittest.TestCase):
+    def test_first_selection_stays_asserted(self):
+        for cs, cs_n in [(0b01, 0b10), (0b10, 0b01)]:
+            with self.subTest(cs=cs):
+                dut = _LiteSPICSControlDUT()
+
+                def generator():
+                    yield dut.cs.eq(cs)
+                    for _ in range(8):
+                        yield
+                        self.assertEqual((yield dut.pads.cs_n), cs_n)
+
+                run_simulation(dut, generator())
+
+    def test_different_selection_stays_asserted(self):
+        for first_cs, second_cs, second_cs_n in [
+            (0b01, 0b10, 0b01),
+            (0b10, 0b01, 0b10),
+        ]:
+            with self.subTest(first_cs=first_cs, second_cs=second_cs):
+                dut = _LiteSPICSControlDUT()
+
+                def generator():
+                    # Complete a transfer and start the inter-transfer delay.
+                    yield dut.cs.eq(first_cs)
+                    for _ in range(8):
+                        yield
+                    yield dut.cs.eq(0)
+                    yield
+
+                    # A different chip can be selected immediately and must remain selected.
+                    yield dut.cs.eq(second_cs)
+                    for _ in range(8):
+                        yield
+                        self.assertEqual((yield dut.pads.cs_n), second_cs_n)
+
+                run_simulation(dut, generator())
+
+    def test_same_selection_observes_delay(self):
+        dut = _LiteSPICSControlDUT()
+
+        def generator():
+            yield dut.cs.eq(0b01)
+            for _ in range(8):
+                yield
+            yield dut.cs.eq(0)
+            yield
+
+            yield dut.cs.eq(0b01)
+            yield
+            self.assertEqual((yield dut.pads.cs_n), 0b11)
+
+            for _ in range(8):
+                yield
+            self.assertEqual((yield dut.pads.cs_n), 0b10)
+
+        run_simulation(dut, generator())