The Verilog/ext/VexiiRiscv/folder cannot be found.

[liqihong8]

I think incomplete project files can lead to build errors. Referring to the pythondata_cpu-vexriscv/verilog file, the complete file structure path should be as follows: pythondata-cpu-vexiiriscv/pythondata_cpu_vexiiriscv/verilog/ext/VexiiRiscv/。 But this project does not have it.

[Dolu1990]

Normaly, by running a SoC generation with cpu vexiiriscv enabled in parameters, Litex will clone VexiiRiscv.
Did you tried ?

Reason it is done like this is to avoid clonning vexiiriscv for people which do not needs it.

[liqihong8]

I have tried, and the operation process and error printing are as follows:

(my-venv) root@9cbacacea84b:/my-venv/work/python-litex-20250311# litex-boards/litex_boards/targets/efinix_ti375_c529_dev_kit.py --cpu-type=vexiiriscv --cpu-variant=debian --updat
e-repo=no --with-coherent-dma --vexii-args="--fetch-l1-hardware-prefetch=nl --fetch-l1-refill-count=2 --fetch-l1-mem-data-width-min=128 --lsu-l1-mem-data-width-min=128 --lsu-softw
are-prefetch --lsu-hardware-prefetch rpt --performance-counters 9 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 4 --lsu-l1-writeback-count 4 --lsu-l1-store-buffer-slots=4 --r
elaxed-div" --l2-bytes=524288 --sys-clk-freq 100000000 --cpu-clk-freq 200000000 --with-cpu-clk --bus-standard axi-lite --cpu-count=4 --build
Namespace(bios_console='full', bios_format='integer', bios_lto=False, bram_output_regs_packing='1', build=True, build_backend='litex', bus_address_width=32, bus_bursting=False, bu
s_data_width=32, bus_interconnect='shared', bus_standard='axi-lite', bus_timeout=1000000, cpu_cfu=None, cpu_clk_freq=200000000.0, cpu_count='4', cpu_reset_address=None, cpu_type='
vexiiriscv', cpu_variant='debian', csr_address_width=14, csr_data_width=32, csr_ordering='big', csr_paging=2048, doc=False, eth_ip='192.168.1.50', flash=False, gateware_dir=None,
generated_dir=None, ident=None, include_dir=None, infer_clk_enable='3', infer_sync_set_reset='1', integrated_main_ram_size=None, integrated_rom_init=None, integrated_rom_size=1310
72, integrated_sram_size=8192, jtagbone_chain=1, l2_bytes='524288', l2_self_flush=None, l2_size=8192, l2_ways=0, load=False, log_filename=None, log_level='info', memory_x=None, mu
lt_input_regs_packing='1', mult_output_regs_packing='1', no_compile=False, no_compile_gateware=False, no_compile_software=False, no_ctrl=False, no_ident_version=False, no_netlist_
cache=False, no_timer=False, no_uart=False, output_dir=None, remote_ip='192.168.1.100', retiming='1', seq_opt='1', soc_csv=None, soc_json=None, soc_svd=None, software_dir=None, sy
(my-venv) root@9cbacacea84b:/my-venv/work/python-litex-20250311# litex-boards/litex_boards/targets/efinix_ti375_c529_dev_kit.py --cpu-type=vexi
iriscv --cpu-variant=debian --update-repo=no --with-coherent-dma --vexii-args="--fetch-l1-hardware-prefetch=nl --fetch-l1-refill-count=2 --fetch
-l1-mem-data-width-min=128 --lsu-l1-mem-data-width-min=128 --lsu-software-prefetch --lsu-hardware-prefetch rpt --performance-counters 9 --lsu-l1
-store-buffer-ops=32 --lsu-l1-refill-count 4 --lsu-l1-writeback-count 4 --lsu-l1-store-buffer-slots=4 --relaxed-div" --l2-bytes=524288 --sys-clk
-freq 100000000 --cpu-clk-freq 200000000 --with-cpu-clk --bus-standard axi-lite --cpu-count=4 --build
Namespace(bios_console='full', bios_format='integer', bios_lto=False, bram_output_regs_packing='1', build=True, build_backend='litex', bus_addre
ss_width=32, bus_bursting=False, bus_data_width=32, bus_interconnect='shared', bus_standard='axi-lite', bus_timeout=1000000, cpu_cfu=None, cpu_c
lk_freq=200000000.0, cpu_count='4', cpu_reset_address=None, cpu_type='vexiiriscv', cpu_variant='debian', csr_address_width=14, csr_data_width=32
, csr_ordering='big', csr_paging=2048, doc=False, eth_ip='192.168.1.50', flash=False, gateware_dir=None, generated_dir=None, ident=None, include
dir=None, infer_clk_enable='3', infer_sync_set_reset='1', integrated_main_ram_size=None, integrated_rom_init=None, integrated_rom_size=131072,
integrated_sram_size=8192, jtagbone_chain=1, l2_bytes='524288', l2_self_flush=None, l2_size=8192, l2_ways=0, load=False, log_filename=None, log
level='info', memory_x=None, mult_input_regs_packing='1', mult_output_regs_packing='1', no_compile=False, no_compile_gateware=False, no_compile_
software=False, no_ctrl=False, no_ident_version=False, no_netlist_cache=False, no_timer=False, no_uart=False, output_dir=None, remote_ip='192.16
8.1.100', retiming='1', seq_opt='1', soc_csv=None, soc_json=None, soc_svd=None, software_dir=None, synth_mode='speed', sys_clk_freq=100000000.0,
timer_uptime=False, toolchain='efinity', uart_baudrate=115200, uart_fifo_depth=16, uart_name='serial', update_repo='no', vexii_args='--fetch-l1
-hardware-prefetch=nl --fetch-l1-refill-count=2 --fetch-l1-mem-data-width-min=128 --lsu-l1-mem-data-width-min=128 --lsu-software-prefetch --lsu-
hardware-prefetch rpt --performance-counters 9 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 4 --lsu-l1-writeback-count 4 --lsu-l1-store-buffer-slots=4 --relaxed-div', vexii_
macsg=[], vexii_video=[], watchdog_reset_delay=None, watchdog_width=32, with_axi3=False, with_coherent_dma=True, with_cpu_clk=True, with_etherbone=False, with_ethernet=False, with
_jtag_instruction=False, with_jtag_tap=False, with_jtagbone=False, with_ohci=False, with_sdcard=False, with_spi_sdcard=False, with_uartbone=False, with_watchdog=False)
/bin/sh: 1: cd: can't cd to /root/my-venv/work/python-litex-20250311/pythondata-cpu-vexiiriscv/pythondata_cpu_vexiiriscv/verilog/ext/VexiiRiscv
Traceback (most recent call last):
File "litex-boards/litex_boards/targets/efinix_ti375_c529_dev_kit.py", line 590, in
main()
File "litex-boards/litex_boards/targets/efinix_ti375_c529_dev_kit.py", line 561, in main
args = parser.parse_args()
File "/root/my-venv/work/python-litex-20250311/litex/litex/build/parser.py", line 241, in parse_args
cpu_cls.args_read(self._args)
File "/root/my-venv/work/python-litex-20250311/litex/litex/soc/cores/cpu/vexiiriscv/core.py", line 197, in args_read
subprocess.check_call(cmd, shell=True)
File "/usr/lib/python3.8/subprocess.py", line 364, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command 'cd /root/my-venv/work/python-litex-20250311/pythondata-cpu-vexiiriscv/pythondata_cpu_vexiiriscv/verilog/ext/VexiiRiscv && sbt "runMain vexi
iriscv.soc.litex.PythonArgsGen --with-mul --with-div --allow-bypass-from=0 --performance-counters=0 --fetch-l1 --fetch-l1-ways=2 --lsu-l1 --lsu-l1-ways=2 --with-lsu-bypass --rel
axed-branch --with-rva --with-supervisor --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64 --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64 --xlen=64 --with-rvc --with-rvf --with-r
vd --fma-reduced-accuracy --fpu-ignore-subnormal --with-btb --with-ras --with-gshare --fetch-l1-hardware-prefetch=nl --fetch-l1-refill-count=2 --fetch-l1-mem-data-width-min=128 --
lsu-l1-mem-data-width-min=128 --lsu-software-prefetch --lsu-hardware-prefetch rpt --performance-counters 9 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 4 --lsu-l1-writeback-
count 4 --lsu-l1-store-buffer-slots=4 --relaxed-div --python-file=/root/my-venv/work/python-litex-20250311/pythondata-cpu-vexiiriscv/pythondata_cpu_vexiiriscv/verilog/35c1a5cde7a2
fd16c784299f87fc545d.py"' returned non-zero exit status 2.

log.txt

[liqihong8]

I understand, we need to remove -- update repo=no from the parameter list.