CIRGen support for __sync_{and,or,xor,nand}_and_fetch builtin

[bcardosolopes]

add and sub are already supported.

[moar55]

I would like to take this issue.

[bcardosolopes]

@moar55 neat, assigned to you!

[moar55]

Hey, I was looking at the previous tests. And was wondering why does sync_op_and_fetch translates to

cir.atomic.fetch(add, {{%.*}} : !cir.ptr<!s8i>, [[VAL0]] : !s8i, seq_cst) fetch_first : !s8i
cir.binop(add, [[RES0]], [[VAL0]]) : !s8i

Wouldn't it be less instructions if fetch_first was not set (and thus the following binop wouldn't be needed.
Or is there a reason for this that I may not be aware of?

[moar55]

One other thing more related to this task, I don't see the BinOpKind::Nand. Should this be added along with the lowering logic to mlir::llvm?

[bcardosolopes]

Wouldn't it be less instructions if fetch_first was not set (and thus the following binop wouldn't be needed.
Or is there a reason for this that I may not be aware of?

What have you found when you compared to LLVM output from OG? We go about the same

[bcardosolopes]

One other thing more related to this task, I don't see the BinOpKind::Nand. Should this be added along with the lowering logic to mlir::llvm?

Do you need it as part of implementing anything? If so yes, if just for completeness best we don't.