From 1f347276b852999c8590b4019cb931915211edd9 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Sat, 16 Nov 2024 03:11:32 +0300 Subject: [PATCH] [Sparc] TableGen-erate SDNode descriptions --- llvm/lib/Target/Sparc/CMakeLists.txt | 2 + llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 1 + llvm/lib/Target/Sparc/SparcISelLowering.cpp | 42 +----------------- llvm/lib/Target/Sparc/SparcISelLowering.h | 43 ------------------- llvm/lib/Target/Sparc/SparcInstrInfo.td | 3 ++ .../Target/Sparc/SparcSelectionDAGInfo.cpp | 19 ++++++++ llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h | 28 ++++++++++++ llvm/lib/Target/Sparc/SparcSubtarget.cpp | 11 ++++- llvm/lib/Target/Sparc/SparcSubtarget.h | 10 ++--- 9 files changed, 69 insertions(+), 90 deletions(-) create mode 100644 llvm/lib/Target/Sparc/SparcSelectionDAGInfo.cpp create mode 100644 llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h diff --git a/llvm/lib/Target/Sparc/CMakeLists.txt b/llvm/lib/Target/Sparc/CMakeLists.txt index bf76ed9d671b9..e9d78c50fc11e 100644 --- a/llvm/lib/Target/Sparc/CMakeLists.txt +++ b/llvm/lib/Target/Sparc/CMakeLists.txt @@ -10,6 +10,7 @@ tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info) tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info) +tablegen(LLVM SparcGenSDNodeInfo.inc -gen-sd-node-info -sdnode-namespace=SPISD) tablegen(LLVM SparcGenSearchableTables.inc -gen-searchable-tables) tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget) @@ -25,6 +26,7 @@ add_llvm_target(SparcCodeGen SparcFrameLowering.cpp SparcMachineFunctionInfo.cpp SparcRegisterInfo.cpp + SparcSelectionDAGInfo.cpp SparcSubtarget.cpp SparcTargetMachine.cpp SparcMCInstLower.cpp diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 461f859957041..55bf40e185ff4 100644 --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -10,6 +10,7 @@ // //===----------------------------------------------------------------------===// +#include "SparcSelectionDAGInfo.h" #include "SparcTargetMachine.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 0b98327d53434..15669b5bade4e 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -16,6 +16,7 @@ #include "MCTargetDesc/SparcMCTargetDesc.h" #include "SparcMachineFunctionInfo.h" #include "SparcRegisterInfo.h" +#include "SparcSelectionDAGInfo.h" #include "SparcTargetMachine.h" #include "SparcTargetObjectFile.h" #include "llvm/ADT/StringExtras.h" @@ -2037,47 +2038,6 @@ bool SparcTargetLowering::useSoftFloat() const { return Subtarget->useSoftFloat(); } -const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { - switch ((SPISD::NodeType)Opcode) { - case SPISD::FIRST_NUMBER: break; - case SPISD::CMPICC: return "SPISD::CMPICC"; - case SPISD::CMPFCC: return "SPISD::CMPFCC"; - case SPISD::CMPFCC_V9: - return "SPISD::CMPFCC_V9"; - case SPISD::BRICC: return "SPISD::BRICC"; - case SPISD::BPICC: - return "SPISD::BPICC"; - case SPISD::BPXCC: - return "SPISD::BPXCC"; - case SPISD::BRFCC: return "SPISD::BRFCC"; - case SPISD::BRFCC_V9: - return "SPISD::BRFCC_V9"; - case SPISD::BR_REG: - return "SPISD::BR_REG"; - case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; - case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC"; - case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; - case SPISD::SELECT_REG: - return "SPISD::SELECT_REG"; - case SPISD::Hi: return "SPISD::Hi"; - case SPISD::Lo: return "SPISD::Lo"; - case SPISD::FTOI: return "SPISD::FTOI"; - case SPISD::ITOF: return "SPISD::ITOF"; - case SPISD::FTOX: return "SPISD::FTOX"; - case SPISD::XTOF: return "SPISD::XTOF"; - case SPISD::CALL: return "SPISD::CALL"; - case SPISD::RET_GLUE: return "SPISD::RET_GLUE"; - case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; - case SPISD::FLUSHW: return "SPISD::FLUSHW"; - case SPISD::TLS_ADD: return "SPISD::TLS_ADD"; - case SPISD::TLS_LD: return "SPISD::TLS_LD"; - case SPISD::TLS_CALL: return "SPISD::TLS_CALL"; - case SPISD::TAIL_CALL: return "SPISD::TAIL_CALL"; - case SPISD::LOAD_GDOP: return "SPISD::LOAD_GDOP"; - } - return nullptr; -} - EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, EVT VT) const { if (!VT.isVector()) diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h index deb66854a1e7a..d7e4c48672a58 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.h +++ b/llvm/lib/Target/Sparc/SparcISelLowering.h @@ -20,47 +20,6 @@ namespace llvm { class SparcSubtarget; - namespace SPISD { - enum NodeType : unsigned { - FIRST_NUMBER = ISD::BUILTIN_OP_END, - CMPICC, // Compare two GPR operands, set icc+xcc. - CMPFCC, // Compare two FP operands, set fcc. - CMPFCC_V9, // Compare two FP operands, set fcc (v9 variant). - BRICC, // Branch to dest on icc condition - BPICC, // Branch to dest on icc condition, with prediction (64-bit only). - BPXCC, // Branch to dest on xcc condition, with prediction (64-bit only). - BRFCC, // Branch to dest on fcc condition - BRFCC_V9, // Branch to dest on fcc condition (v9 variant). - BR_REG, // Branch to dest using the comparison of a register with zero. - SELECT_ICC, // Select between two values using the current ICC flags. - SELECT_XCC, // Select between two values using the current XCC flags. - SELECT_FCC, // Select between two values using the current FCC flags. - SELECT_REG, // Select between two values using the comparison of a register - // with zero. - - Hi, - Lo, // Hi/Lo operations, typically on a global address. - - FTOI, // FP to Int within a FP register. - ITOF, // Int to FP within a FP register. - FTOX, // FP to Int64 within a FP register. - XTOF, // Int64 to FP within a FP register. - - CALL, // A call instruction. - RET_GLUE, // Return with a glue operand. - GLOBAL_BASE_REG, // Global base reg for PIC. - FLUSHW, // FLUSH register windows to stack. - - TAIL_CALL, // Tail call - - TLS_ADD, // For Thread Local Storage (TLS). - TLS_LD, - TLS_CALL, - - LOAD_GDOP, // Load operation w/ gdop relocation. - }; - } - class SparcTargetLowering : public TargetLowering { const SparcSubtarget *Subtarget; public: @@ -82,8 +41,6 @@ namespace llvm { EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; - const char *getTargetNodeName(unsigned Opcode) const override; - ConstraintType getConstraintType(StringRef Constraint) const override; ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 5617681821a3f..fd9e36732ea4e 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -321,6 +321,9 @@ def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def retglue : SDNode<"SPISD::RET_GLUE", SDT_SPRet, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; +def global_base_reg : SDNode<"SPISD::GLOBAL_BASE_REG", + SDTypeProfile<1, 0, [SDTCisVT<0, iPTR>]>>; + def flushw : SDNode<"SPISD::FLUSHW", SDTNone, [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; diff --git a/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.cpp b/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.cpp new file mode 100644 index 0000000000000..7801479051ecd --- /dev/null +++ b/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.cpp @@ -0,0 +1,19 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "SparcSelectionDAGInfo.h" + +#define GET_SDNODE_DESC +#include "SparcGenSDNodeInfo.inc" + +using namespace llvm; + +SparcSelectionDAGInfo::SparcSelectionDAGInfo() + : SelectionDAGGenTargetInfo(SparcGenSDNodeInfo) {} + +SparcSelectionDAGInfo::~SparcSelectionDAGInfo() = default; diff --git a/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h b/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h new file mode 100644 index 0000000000000..78b27b76a321b --- /dev/null +++ b/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h @@ -0,0 +1,28 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_SPARC_SPARCSELECTIONDAGINFO_H +#define LLVM_LIB_TARGET_SPARC_SPARCSELECTIONDAGINFO_H + +#include "llvm/CodeGen/SelectionDAGTargetInfo.h" + +#define GET_SDNODE_ENUM +#include "SparcGenSDNodeInfo.inc" + +namespace llvm { + +class SparcSelectionDAGInfo : public SelectionDAGGenTargetInfo { +public: + SparcSelectionDAGInfo(); + + ~SparcSelectionDAGInfo() override; +}; + +} // namespace llvm + +#endif // LLVM_LIB_TARGET_SPARC_SPARCSELECTIONDAGINFO_H diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp index 3ccb742981ea5..e42df1d68613b 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "SparcSubtarget.h" +#include "SparcSelectionDAGInfo.h" #include "llvm/ADT/StringRef.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/MathExtras.h" @@ -52,7 +53,15 @@ SparcSubtarget::SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU, ReserveRegister(TM.getMCRegisterInfo()->getNumRegs()), TargetTriple(TM.getTargetTriple()), Is64Bit(is64Bit), InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)), - TLInfo(TM, *this), FrameLowering(*this) {} + TLInfo(TM, *this), FrameLowering(*this) { + TSInfo = std::make_unique(); +} + +SparcSubtarget::~SparcSubtarget() = default; + +const SelectionDAGTargetInfo *SparcSubtarget::getSelectionDAGInfo() const { + return TSInfo.get(); +} int SparcSubtarget::getAdjustedFrameSize(int frameSize) const { diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.h b/llvm/lib/Target/Sparc/SparcSubtarget.h index fe4aca5195306..5785c199f44b5 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.h +++ b/llvm/lib/Target/Sparc/SparcSubtarget.h @@ -17,7 +17,6 @@ #include "SparcFrameLowering.h" #include "SparcISelLowering.h" #include "SparcInstrInfo.h" -#include "llvm/CodeGen/SelectionDAGTargetInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/Support/ErrorHandling.h" @@ -46,13 +45,15 @@ class SparcSubtarget : public SparcGenSubtargetInfo { SparcInstrInfo InstrInfo; SparcTargetLowering TLInfo; - SelectionDAGTargetInfo TSInfo; + std::unique_ptr TSInfo; SparcFrameLowering FrameLowering; public: SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU, const StringRef &FS, const TargetMachine &TM, bool is64bit); + ~SparcSubtarget() override; + const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; } const TargetFrameLowering *getFrameLowering() const override { return &FrameLowering; @@ -63,9 +64,8 @@ class SparcSubtarget : public SparcGenSubtargetInfo { const SparcTargetLowering *getTargetLowering() const override { return &TLInfo; } - const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { - return &TSInfo; - } + + const SelectionDAGTargetInfo *getSelectionDAGInfo() const override; bool enableMachineScheduler() const override;