diff --git a/test/WaveOps/WaveActiveMax.fp16.test b/test/WaveOps/WaveActiveMax.fp16.test new file mode 100644 index 00000000..08b17a41 --- /dev/null +++ b/test/WaveOps/WaveActiveMax.fp16.test @@ -0,0 +1,687 @@ +#--- source.hlsl +#define VALUE_SETS 2 +#define NUM_MASKS 16 +#define NUM_THREADS 4 + +struct MaskStruct { + int mask[NUM_THREADS]; +}; + +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test half2 +RWStructuredBuffer Out3 : register(u3); // test half3 +RWStructuredBuffer Out4 : register(u4); // test half4 +RWStructuredBuffer Out5 : register(u5); // constant folding +StructuredBuffer Masks : register(t6); + + +[numthreads(NUM_THREADS,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + for (int ValueSet = 0; ValueSet < VALUE_SETS; ValueSet++) { + const uint ValueSetOffset = ValueSet * NUM_MASKS * NUM_THREADS; + for (int MaskIdx = 0; MaskIdx < NUM_MASKS; MaskIdx++) { + half4 v = In[ValueSet * ValueSetOffset + MaskIdx * NUM_THREADS + tid.x]; + const uint OutIdx = ValueSetOffset + MaskIdx * NUM_THREADS + tid.x; + if (Masks[MaskIdx].mask[tid.x]) { + Out1[OutIdx] = WaveActiveMax( v.x ); + Out2[OutIdx].xy = WaveActiveMax( v.xy ); + Out3[OutIdx].xyz = WaveActiveMax( v.xyz ); + Out4[OutIdx] = WaveActiveMax( v ); + } + } + } + + // constant folding case + Out5[0] = WaveActiveMax(half4(1,2,3,4)); +} + + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Float16 + Stride: 8 + # 2 value sets + # For each value set, + # and for each specific one of the 16 thread masks in that value set, + # and for each of the 4 threads in that thread mask, + # there will be a unique set of 4 values, such that + # none of the other threads in that thread mask share any values + Data: [ + 0x2000, 0x2200, 0x2400, 0x2800, # <-- Value set 0, thread mask 0, thread id 0 will read these In values + 0x2A00, 0x2C00, 0x2E00, 0x3000, # <-- Value set 0, thread mask 0, thread id 1 will read these In values + 0x3200, 0x3400, 0x3600, 0x3800, + 0x3900, 0x3A00, 0x3B00, 0x3BC0, + 0x2200, 0x2400, 0x2800, 0x2A00, # <-- Value set 0, thread mask 1, thread id 0 will read these In values + 0x2C00, 0x2E00, 0x3000, 0x3200, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x3A00, 0x3B00, 0x3BC0, 0x2000, + 0x2400, 0x2800, 0x2A00, 0x2C00, + 0x2E00, 0x3000, 0x3200, 0x3400, + 0x3600, 0x3800, 0x3900, 0x3A00, + 0x3B00, 0x3BC0, 0x2000, 0x2200, + 0x2800, 0x2A00, 0x2C00, 0x2E00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x2000, 0x2200, 0x2400, + 0x2A00, 0x2C00, 0x2E00, 0x3000, + 0x3200, 0x3400, 0x3600, 0x3800, + 0x3900, 0x3A00, 0x3B00, 0x3BC0, + 0x2000, 0x2200, 0x2400, 0x2800, + 0x2C00, 0x2E00, 0x3000, 0x3200, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x3A00, 0x3B00, 0x3BC0, 0x2000, + 0x2200, 0x2400, 0x2800, 0x2A00, + 0x2E00, 0x3000, 0x3200, 0x3400, + 0x3600, 0x3800, 0x3900, 0x3A00, + 0x3B00, 0x3BC0, 0x2000, 0x2200, + 0x2400, 0x2800, 0x2A00, 0x2C00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x2000, 0x2200, 0x2400, + 0x2800, 0x2A00, 0x2C00, 0x2E00, + 0x3200, 0x3400, 0x3600, 0x3800, + 0x3900, 0x3A00, 0x3B00, 0x3BC0, + 0x2000, 0x2200, 0x2400, 0x2800, + 0x2A00, 0x2C00, 0x2E00, 0x3000, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x3A00, 0x3B00, 0x3BC0, 0x2000, + 0x2200, 0x2400, 0x2800, 0x2A00, + 0x2C00, 0x2E00, 0x3000, 0x3200, + 0x3600, 0x3800, 0x3900, 0x3A00, + 0x3B00, 0x3BC0, 0x2000, 0x2200, + 0x2400, 0x2800, 0x2A00, 0x2C00, + 0x2E00, 0x3000, 0x3200, 0x3400, + 0x3800, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x2000, 0x2200, 0x2400, + 0x2800, 0x2A00, 0x2C00, 0x2E00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3900, 0x3A00, 0x3B00, 0x3BC0, + 0x2000, 0x2200, 0x2400, 0x2800, + 0x2A00, 0x2C00, 0x2E00, 0x3000, + 0x3200, 0x3400, 0x3600, 0x3800, + 0x3A00, 0x3B00, 0x3BC0, 0x2000, + 0x2200, 0x2400, 0x2800, 0x2A00, + 0x2C00, 0x2E00, 0x3000, 0x3200, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x3B00, 0x3BC0, 0x2000, 0x2200, + 0x2400, 0x2800, 0x2A00, 0x2C00, + 0x2E00, 0x3000, 0x3200, 0x3400, + 0x3600, 0x3800, 0x3900, 0x3A00, + 0x3BC0, 0x2000, 0x2200, 0x2400, + 0x2800, 0x2A00, 0x2C00, 0x2E00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3900, 0x3A00, 0x3B00, + 0x2800, 0x2400, 0x2200, 0x2000, # <-- Value set 1, thread mask 0, thread id 0 will read these In values + 0x3000, 0x2E00, 0x2C00, 0x2A00, + 0x3800, 0x3600, 0x3400, 0x3200, + 0x3BC0, 0x3B00, 0x3A00, 0x3900, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x3200, 0x3000, 0x2E00, 0x2C00, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x2000, 0x3BC0, 0x3B00, 0x3A00, + 0x2C00, 0x2A00, 0x2800, 0x2400, + 0x3400, 0x3200, 0x3000, 0x2E00, + 0x3A00, 0x3900, 0x3800, 0x3600, + 0x2200, 0x2000, 0x3BC0, 0x3B00, + 0x2E00, 0x2C00, 0x2A00, 0x2800, + 0x3600, 0x3400, 0x3200, 0x3000, + 0x3B00, 0x3A00, 0x3900, 0x3800, + 0x2400, 0x2200, 0x2000, 0x3BC0, + 0x3000, 0x2E00, 0x2C00, 0x2A00, + 0x3800, 0x3600, 0x3400, 0x3200, + 0x3BC0, 0x3B00, 0x3A00, 0x3900, + 0x2800, 0x2400, 0x2200, 0x2000, + 0x3200, 0x3000, 0x2E00, 0x2C00, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x2000, 0x3BC0, 0x3B00, 0x3A00, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x3400, 0x3200, 0x3000, 0x2E00, + 0x3A00, 0x3900, 0x3800, 0x3600, + 0x2200, 0x2000, 0x3BC0, 0x3B00, + 0x2C00, 0x2A00, 0x2800, 0x2400, + 0x3600, 0x3400, 0x3200, 0x3000, + 0x3B00, 0x3A00, 0x3900, 0x3800, + 0x2400, 0x2200, 0x2000, 0x3BC0, + 0x2E00, 0x2C00, 0x2A00, 0x2800, + 0x3800, 0x3600, 0x3400, 0x3200, + 0x3BC0, 0x3B00, 0x3A00, 0x3900, + 0x2800, 0x2400, 0x2200, 0x2000, + 0x3000, 0x2E00, 0x2C00, 0x2A00, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x2000, 0x3BC0, 0x3B00, 0x3A00, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x3200, 0x3000, 0x2E00, 0x2C00, + 0x3A00, 0x3900, 0x3800, 0x3600, + 0x2200, 0x2000, 0x3BC0, 0x3B00, + 0x2C00, 0x2A00, 0x2800, 0x2400, + 0x3400, 0x3200, 0x3000, 0x2E00, + 0x3B00, 0x3A00, 0x3900, 0x3800, + 0x2400, 0x2200, 0x2000, 0x3BC0, + 0x2E00, 0x2C00, 0x2A00, 0x2800, + 0x3600, 0x3400, 0x3200, 0x3000, + 0x3BC0, 0x3B00, 0x3A00, 0x3900, + 0x2800, 0x2400, 0x2200, 0x2000, + 0x3000, 0x2E00, 0x2C00, 0x2A00, + 0x3800, 0x3600, 0x3400, 0x3200, + 0x2000, 0x3BC0, 0x3B00, 0x3A00, + 0x2A00, 0x2800, 0x2400, 0x2200, + 0x3200, 0x3000, 0x2E00, 0x2C00, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x2200, 0x2000, 0x3BC0, 0x3B00, + 0x2C00, 0x2A00, 0x2800, 0x2400, + 0x3400, 0x3200, 0x3000, 0x2E00, + 0x3A00, 0x3900, 0x3800, 0x3600, + 0x2400, 0x2200, 0x2000, 0x3BC0, + 0x2E00, 0x2C00, 0x2A00, 0x2800, + 0x3600, 0x3400, 0x3200, 0x3000, + 0x3B00, 0x3A00, 0x3900, 0x3800 ] + + - Name: Out1 + Format: Float16 + Stride: 2 + # 1 half is 2 bytes, * 4 halves for 4 threads, * 16 thread masks, * 2 value sets + ZeroInitSize: 256 + - Name: Out2 + Format: Float16 + Stride: 4 + ZeroInitSize: 512 + - Name: Out3 + Format: Float16 + Stride: 8 + ZeroInitSize: 1024 + - Name: Out4 + Format: Float16 + Stride: 8 + ZeroInitSize: 1024 + - Name: Out5 + Format: Float16 + Stride: 8 + ZeroInitSize: 8 + - Name: Masks + Format: Int32 + Stride: 8 + # 16 active mask sets for threads 0, 1, 2, 3: + # 0 0 0 0 + # 0 0 0 1 + # 0 0 1 0 + # 0 0 1 1 + # 0 1 0 0 + # 0 1 0 1 + # 0 1 1 0 + # 0 1 1 1 + # 1 0 0 0 + # 1 0 0 1 + # 1 0 1 0 + # 1 0 1 1 + # 1 1 0 0 + # 1 1 0 1 + # 1 1 1 0 + # 1 1 1 1 + Data: [ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1] + - Name: ExpectedOut1 + Format: Float16 + Stride: 8 + # 2 value sets, 16 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3A00, + 0x0, 0x0, 0x3600, 0x0, + 0x0, 0x0, 0x3BC0, 0x3BC0, + 0x0, 0x3200, 0x0, 0x0, + 0x0, 0x3400, 0x0, 0x3400, + 0x0, 0x3B00, 0x3B00, 0x0, + 0x0, 0x3BC0, 0x3BC0, 0x3BC0, + 0x3200, 0x0, 0x0, 0x0, + 0x3400, 0x0, 0x0, 0x3400, + 0x3600, 0x0, 0x3600, 0x0, + 0x3800, 0x0, 0x3800, 0x3800, + 0x3900, 0x3900, 0x0, 0x0, + 0x3A00, 0x3A00, 0x0, 0x3A00, + 0x3B00, 0x3B00, 0x3B00, 0x0, + 0x3BC0, 0x3BC0, 0x3BC0, 0x3BC0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2000, + 0x0, 0x0, 0x3A00, 0x0, + 0x0, 0x0, 0x3B00, 0x3B00, + 0x0, 0x3800, 0x0, 0x0, + 0x0, 0x3900, 0x0, 0x3900, + 0x0, 0x3A00, 0x3A00, 0x0, + 0x0, 0x3B00, 0x3B00, 0x3B00, + 0x3800, 0x0, 0x0, 0x0, + 0x3900, 0x0, 0x0, 0x3900, + 0x3A00, 0x0, 0x3A00, 0x0, + 0x3B00, 0x0, 0x3B00, 0x3B00, + 0x3BC0, 0x3BC0, 0x0, 0x0, + 0x3900, 0x3900, 0x0, 0x3900, + 0x3400, 0x3400, 0x3400, 0x0, + 0x3B00, 0x3B00, 0x3B00, 0x3B00 ] + - Name: ExpectedOut2 + Format: Float16 + Stride: 8 + # 2 value sets, 16 masks per value set, 4 threads per mask, 1 result value per thread + Data: [ 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3A00, 0x3B00, + 0x0, 0x0, 0x0, 0x0, + 0x3600, 0x3800, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3BC0, 0x3900, 0x3BC0, 0x3900, + 0x0, 0x0, 0x3200, 0x3400, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3400, 0x3600, + 0x0, 0x0, 0x3400, 0x3600, + 0x0, 0x0, 0x3B00, 0x3BC0, + 0x3B00, 0x3BC0, 0x0, 0x0, + 0x0, 0x0, 0x3BC0, 0x3900, + 0x3BC0, 0x3900, 0x3BC0, 0x3900, + 0x3200, 0x3400, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x0, 0x0, + 0x0, 0x0, 0x3400, 0x3600, + 0x3600, 0x3800, 0x0, 0x0, + 0x3600, 0x3800, 0x0, 0x0, + 0x3800, 0x3900, 0x0, 0x0, + 0x3800, 0x3900, 0x3800, 0x3900, + 0x3900, 0x3A00, 0x3900, 0x3A00, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3B00, 0x3A00, 0x3B00, + 0x0, 0x0, 0x3A00, 0x3B00, + 0x3B00, 0x3BC0, 0x3B00, 0x3BC0, + 0x3B00, 0x3BC0, 0x0, 0x0, + 0x3BC0, 0x3900, 0x3BC0, 0x3900, + 0x3BC0, 0x3900, 0x3BC0, 0x3900, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2000, 0x3BC0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3900, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3B00, 0x3A00, + 0x0, 0x0, 0x3800, 0x3600, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3900, 0x3800, + 0x0, 0x0, 0x3900, 0x3800, + 0x0, 0x0, 0x3A00, 0x3900, + 0x3A00, 0x3900, 0x0, 0x0, + 0x0, 0x0, 0x3B00, 0x3A00, + 0x3B00, 0x3A00, 0x3B00, 0x3A00, + 0x3800, 0x3600, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x0, 0x0, + 0x0, 0x0, 0x3900, 0x3800, + 0x3A00, 0x3900, 0x0, 0x0, + 0x3A00, 0x3900, 0x0, 0x0, + 0x3B00, 0x3A00, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3B00, 0x3A00, + 0x3BC0, 0x3B00, 0x3BC0, 0x3B00, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3BC0, 0x3900, 0x3BC0, + 0x0, 0x0, 0x3900, 0x3BC0, + 0x3400, 0x3200, 0x3400, 0x3200, + 0x3400, 0x3200, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3B00, 0x3A00, + 0x3B00, 0x3A00, 0x3B00, 0x3A00 ] + - Name: ExpectedOut3 + Format: Float16 + Stride: 8 + # 2 value sets, 16 masks per value set, 4 threads per mask, 4 result values per thread + # Note, vecs of 3 must be aligned, so the 3 result values are placed into a 4 element vec + Data: [ 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3B00, 0x3BC0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3600, 0x3800, 0x3900, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3200, 0x3400, 0x3600, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x3800, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x3800, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3BC0, 0x3900, 0x0, + 0x3B00, 0x3BC0, 0x3900, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x3200, 0x3400, 0x3600, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x3800, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x3800, 0x0, + 0x3600, 0x3800, 0x3900, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3600, 0x3800, 0x3900, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3800, 0x3900, 0x3A00, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3800, 0x3900, 0x3A00, 0x0, + 0x3800, 0x3900, 0x3A00, 0x0, + 0x3900, 0x3A00, 0x3B00, 0x0, + 0x3900, 0x3A00, 0x3B00, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3B00, 0x3BC0, 0x0, + 0x3A00, 0x3B00, 0x3BC0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3B00, 0x3BC0, 0x0, + 0x3B00, 0x3BC0, 0x3200, 0x0, + 0x3B00, 0x3BC0, 0x3200, 0x0, + 0x3B00, 0x3BC0, 0x3200, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2000, 0x3BC0, 0x3B00, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3900, 0x3800, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3800, 0x3600, 0x3400, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x3600, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x3600, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3900, 0x3BC0, 0x0, + 0x3A00, 0x3900, 0x3BC0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3800, 0x3600, 0x3400, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x3600, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x3600, 0x0, + 0x3A00, 0x3900, 0x3800, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3900, 0x3800, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3BC0, 0x3B00, 0x3A00, 0x0, + 0x3BC0, 0x3B00, 0x3A00, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3BC0, 0x3B00, 0x0, + 0x3900, 0x3BC0, 0x3B00, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3BC0, 0x3B00, 0x0, + 0x3400, 0x3200, 0x3BC0, 0x0, + 0x3400, 0x3200, 0x3BC0, 0x0, + 0x3400, 0x3200, 0x3BC0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x0 ] + - Name: ExpectedOut4 + Format: Float16 + Stride: 8 + Data: [ 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3B00, 0x3BC0, 0x2000, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3600, 0x3800, 0x3900, 0x3A00, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x0, 0x0, 0x0, 0x0, + 0x3200, 0x3400, 0x3600, 0x3800, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3BC0, 0x3900, 0x3A00, + 0x3B00, 0x3BC0, 0x3900, 0x3A00, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x3200, 0x3400, 0x3600, 0x3800, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3400, 0x3600, 0x3800, 0x3900, + 0x3600, 0x3800, 0x3900, 0x3A00, + 0x0, 0x0, 0x0, 0x0, + 0x3600, 0x3800, 0x3900, 0x3A00, + 0x0, 0x0, 0x0, 0x0, + 0x3800, 0x3900, 0x3A00, 0x3B00, + 0x0, 0x0, 0x0, 0x0, + 0x3800, 0x3900, 0x3A00, 0x3B00, + 0x3800, 0x3900, 0x3A00, 0x3B00, + 0x3900, 0x3A00, 0x3B00, 0x3BC0, + 0x3900, 0x3A00, 0x3B00, 0x3BC0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3B00, 0x3BC0, 0x3900, + 0x3A00, 0x3B00, 0x3BC0, 0x3900, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3B00, 0x3BC0, 0x3900, + 0x3B00, 0x3BC0, 0x3200, 0x3400, + 0x3B00, 0x3BC0, 0x3200, 0x3400, + 0x3B00, 0x3BC0, 0x3200, 0x3400, + 0x0, 0x0, 0x0, 0x0, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x3BC0, 0x3900, 0x3A00, 0x3B00, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x2000, 0x3BC0, 0x3B00, 0x3A00, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3900, 0x3800, 0x3600, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0, + 0x0, 0x0, 0x0, 0x0, + 0x3800, 0x3600, 0x3400, 0x3200, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3900, 0x3BC0, 0x3B00, + 0x3A00, 0x3900, 0x3BC0, 0x3B00, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0, + 0x3800, 0x3600, 0x3400, 0x3200, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3800, 0x3600, 0x3400, + 0x3A00, 0x3900, 0x3800, 0x3600, + 0x0, 0x0, 0x0, 0x0, + 0x3A00, 0x3900, 0x3800, 0x3600, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x3800, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x3800, + 0x3B00, 0x3A00, 0x3900, 0x3800, + 0x3BC0, 0x3B00, 0x3A00, 0x3900, + 0x3BC0, 0x3B00, 0x3A00, 0x3900, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3BC0, 0x3B00, 0x3A00, + 0x3900, 0x3BC0, 0x3B00, 0x3A00, + 0x0, 0x0, 0x0, 0x0, + 0x3900, 0x3BC0, 0x3B00, 0x3A00, + 0x3400, 0x3200, 0x3BC0, 0x3B00, + 0x3400, 0x3200, 0x3BC0, 0x3B00, + 0x3400, 0x3200, 0x3BC0, 0x3B00, + 0x0, 0x0, 0x0, 0x0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0, + 0x3B00, 0x3A00, 0x3900, 0x3BC0 ] + - Name: ExpectedOut5 + Format: Float16 + Stride: 8 + Data: [ 0x3C00, 0x4000, 0x4200, 0x4400 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + - Name: Masks + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + +... +#--- end + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# RUN: split-file %s %t +# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveActiveMax.fp32.test b/test/WaveOps/WaveActiveMax.fp32.test new file mode 100644 index 00000000..4b7fcaf7 --- /dev/null +++ b/test/WaveOps/WaveActiveMax.fp32.test @@ -0,0 +1,177 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test float2 +RWStructuredBuffer Out3 : register(u3); // test float3 +RWStructuredBuffer Out4 : register(u4); // test float4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + float4 v = In[tid.x]; + + float s1 = WaveActiveMax( v.x ); + float s2 = tid.x < 3 ? WaveActiveMax( v.x ) : 0; + float s3 = tid.x < 2 ? WaveActiveMax( v.x ) : 0; + float s4 = tid.x < 1 ? WaveActiveMax( v.x ) : 0; + + float2 v2_1 = WaveActiveMax( v.xy ); + float2 v2_2 = tid.x < 3 ? WaveActiveMax( v.xy ) : float2(0,0); + float2 v2_3 = tid.x < 2 ? WaveActiveMax( v.xy ) : float2(0,0); + float2 v2_4 = tid.x < 1 ? WaveActiveMax( v.xy ) : float2(0,0); + + float3 v3_1 = WaveActiveMax( v.xyz ); + float3 v3_2 = tid.x < 3 ? WaveActiveMax( v.xyz ) : float3(0,0,0); + float3 v3_3 = tid.x < 2 ? WaveActiveMax( v.xyz ) : float3(0,0,0); + float3 v3_4 = tid.x < 1 ? WaveActiveMax( v.xyz ) : float3(0,0,0); + + float4 v4_1 = WaveActiveMax( v ); + float4 v4_2 = tid.x < 3 ? WaveActiveMax( v ) : float4(0,0,0,0); + float4 v4_3 = tid.x < 2 ? WaveActiveMax( v ) : float4(0,0,0,0); + float4 v4_4 = tid.x < 1 ? WaveActiveMax( v ) : float4(0,0,0,0); + + float scalars[4] = { s4, s3, s2, s1 }; + float2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + float3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + float4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveActiveMax(float4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Float32 + Stride: 16 + Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + - Name: Out1 + Format: Float32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out2 + Format: Float32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out3 + Format: Float32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out4 + Format: Float32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out5 + Format: Float32 + Stride: 16 + ZeroInitSize: 16 + - Name: ExpectedOut1 + Format: Float32 + Stride: 16 + Data: [ 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 0.0, 0.0, 3.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0 ] + - Name: ExpectedOut2 + Format: Float32 + Stride: 16 + Data: [ 1.0, 10.0, 0.0, 0.0, 2.0, 20.0, 0.0, 0.0, 3.0, 30.0, 0.0, 0.0, 4.0, 40.0, 0.0, 0.0 ] + - Name: ExpectedOut3 + Format: Float32 + Stride: 16 + Data: [ 1.0, 10.0, 100.0, 0.0, 2.0, 20.0, 200.0, 0.0, 3.0, 30.0, 300.0, 0.0, 4.0, 40.0, 400.0, 0.0 ] + - Name: ExpectedOut4 + Format: Float32 + Stride: 16 + Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + - Name: ExpectedOut5 + Format: Float32 + Stride: 16 + Data: [ 1.0, 2.0, 3.0, 4.0 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + +... +#--- end + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# Tracked by https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveActiveMax.fp64.test b/test/WaveOps/WaveActiveMax.fp64.test new file mode 100644 index 00000000..50f9ed87 --- /dev/null +++ b/test/WaveOps/WaveActiveMax.fp64.test @@ -0,0 +1,179 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test double2 +RWStructuredBuffer Out3 : register(u3); // test double3 +RWStructuredBuffer Out4 : register(u4); // test double4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + double4 v = In[tid.x]; + + double s1 = WaveActiveMax( v.x ); + double s2 = tid.x < 3 ? WaveActiveMax( v.x ) : 0; + double s3 = tid.x < 2 ? WaveActiveMax( v.x ) : 0; + double s4 = tid.x < 1 ? WaveActiveMax( v.x ) : 0; + + double2 v2_1 = WaveActiveMax( v.xy ); + double2 v2_2 = tid.x < 3 ? WaveActiveMax( v.xy ) : double2(0,0); + double2 v2_3 = tid.x < 2 ? WaveActiveMax( v.xy ) : double2(0,0); + double2 v2_4 = tid.x < 1 ? WaveActiveMax( v.xy ) : double2(0,0); + + double3 v3_1 = WaveActiveMax( v.xyz ); + double3 v3_2 = tid.x < 3 ? WaveActiveMax( v.xyz ) : double3(0,0,0); + double3 v3_3 = tid.x < 2 ? WaveActiveMax( v.xyz ) : double3(0,0,0); + double3 v3_4 = tid.x < 1 ? WaveActiveMax( v.xyz ) : double3(0,0,0); + + double4 v4_1 = WaveActiveMax( v ); + double4 v4_2 = tid.x < 3 ? WaveActiveMax( v ) : double4(0,0,0,0); + double4 v4_3 = tid.x < 2 ? WaveActiveMax( v ) : double4(0,0,0,0); + double4 v4_4 = tid.x < 1 ? WaveActiveMax( v ) : double4(0,0,0,0); + + double scalars[4] = { s4, s3, s2, s1 }; + double2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + double3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + double4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveActiveMax(double4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Float64 + Stride: 32 + Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + - Name: Out1 + Format: Float64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out2 + Format: Float64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out3 + Format: Float64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out4 + Format: Float64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out5 + Format: Float64 + Stride: 32 + ZeroInitSize: 32 + - Name: ExpectedOut1 + Format: Float64 + Stride: 32 + Data: [ 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 0.0, 0.0, 3.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0 ] + - Name: ExpectedOut2 + Format: Float64 + Stride: 32 + Data: [ 1.0, 10.0, 0.0, 0.0, 2.0, 20.0, 0.0, 0.0, 3.0, 30.0, 0.0, 0.0, 4.0, 40.0, 0.0, 0.0 ] + - Name: ExpectedOut3 + Format: Float64 + Stride: 32 + Data: [ 1.0, 10.0, 100.0, 0.0, 2.0, 20.0, 200.0, 0.0, 3.0, 30.0, 300.0, 0.0, 4.0, 40.0, 400.0, 0.0 ] + - Name: ExpectedOut4 + Format: Float64 + Stride: 32 + Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ] + - Name: ExpectedOut5 + Format: Float64 + Stride: 32 + Data: [ 1.0, 2.0, 3.0, 4.0 ] +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + +... +#--- end + +# REQUIRES: Double + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveActiveMax.int16.test b/test/WaveOps/WaveActiveMax.int16.test new file mode 100644 index 00000000..496fb159 --- /dev/null +++ b/test/WaveOps/WaveActiveMax.int16.test @@ -0,0 +1,329 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int16_t2 +RWStructuredBuffer Out3 : register(u3); // test int16_t3 +RWStructuredBuffer Out4 : register(u4); // test int16_t4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +// uints +StructuredBuffer UIn : register(t6); +RWStructuredBuffer UOut1 : register(u7); +RWStructuredBuffer UOut2 : register(u8); +RWStructuredBuffer UOut3 : register(u9); +RWStructuredBuffer UOut4 : register(u10); +RWStructuredBuffer UOut5 : register(u11); + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + int16_t4 v = In[tid.x]; + + int16_t s1 = WaveActiveMax( v.x ); + int16_t s2 = tid.x < 3 ? WaveActiveMax( v.x ) : 0; + int16_t s3 = tid.x < 2 ? WaveActiveMax( v.x ) : 0; + int16_t s4 = tid.x < 1 ? WaveActiveMax( v.x ) : 0; + + int16_t2 v2_1 = WaveActiveMax( v.xy ); + int16_t2 v2_2 = tid.x < 3 ? WaveActiveMax( v.xy ) : int16_t2(0,0); + int16_t2 v2_3 = tid.x < 2 ? WaveActiveMax( v.xy ) : int16_t2(0,0); + int16_t2 v2_4 = tid.x < 1 ? WaveActiveMax( v.xy ) : int16_t2(0,0); + + int16_t3 v3_1 = WaveActiveMax( v.xyz ); + int16_t3 v3_2 = tid.x < 3 ? WaveActiveMax( v.xyz ) : int16_t3(0,0,0); + int16_t3 v3_3 = tid.x < 2 ? WaveActiveMax( v.xyz ) : int16_t3(0,0,0); + int16_t3 v3_4 = tid.x < 1 ? WaveActiveMax( v.xyz ) : int16_t3(0,0,0); + + int16_t4 v4_1 = WaveActiveMax( v ); + int16_t4 v4_2 = tid.x < 3 ? WaveActiveMax( v ) : int16_t4(0,0,0,0); + int16_t4 v4_3 = tid.x < 2 ? WaveActiveMax( v ) : int16_t4(0,0,0,0); + int16_t4 v4_4 = tid.x < 1 ? WaveActiveMax( v ) : int16_t4(0,0,0,0); + + int16_t scalars[4] = { s4, s3, s2, s1 }; + int16_t2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + int16_t3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + int16_t4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveActiveMax(int16_t4(1,2,3,4)); + + // UINT case + + uint16_t4 uv = UIn[tid.x]; + + uint16_t us1 = WaveActiveMax( uv.x ); + uint16_t us2 = tid.x < 3 ? WaveActiveMax( uv.x ) : 0; + uint16_t us3 = tid.x < 2 ? WaveActiveMax( uv.x ) : 0; + uint16_t us4 = tid.x < 1 ? WaveActiveMax( uv.x ) : 0; + + uint16_t2 uv2_1 = WaveActiveMax( uv.xy ); + uint16_t2 uv2_2 = tid.x < 3 ? WaveActiveMax( uv.xy ) : uint16_t2(0,0); + uint16_t2 uv2_3 = tid.x < 2 ? WaveActiveMax( uv.xy ) : uint16_t2(0,0); + uint16_t2 uv2_4 = tid.x < 1 ? WaveActiveMax( uv.xy ) : uint16_t2(0,0); + + uint16_t3 uv3_1 = WaveActiveMax( uv.xyz ); + uint16_t3 uv3_2 = tid.x < 3 ? WaveActiveMax( uv.xyz ) : uint16_t3(0,0,0); + uint16_t3 uv3_3 = tid.x < 2 ? WaveActiveMax( uv.xyz ) : uint16_t3(0,0,0); + uint16_t3 uv3_4 = tid.x < 1 ? WaveActiveMax( uv.xyz ) : uint16_t3(0,0,0); + + uint16_t4 uv4_1 = WaveActiveMax( uv ); + uint16_t4 uv4_2 = tid.x < 3 ? WaveActiveMax( uv ) : uint16_t4(0,0,0,0); + uint16_t4 uv4_3 = tid.x < 2 ? WaveActiveMax( uv ) : uint16_t4(0,0,0,0); + uint16_t4 uv4_4 = tid.x < 1 ? WaveActiveMax( uv ) : uint16_t4(0,0,0,0); + + uint16_t uscalars[4] = { us4, us3, us2, us1 }; + uint16_t2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; + uint16_t3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; + uint16_t4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; + + UOut1[tid.x].x = uscalars[tid.x]; + UOut2[tid.x].xy = uvec2s[tid.x]; + UOut3[tid.x].xyz = uvec3s[tid.x]; + UOut4[tid.x] = uvec4s[tid.x]; + + // constant folding case + UOut5[0] = WaveActiveMax(uint16_t4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Int16 + Stride: 8 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: Out1 + Format: Int16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out2 + Format: Int16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out3 + Format: Int16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out4 + Format: Int16 + Stride: 8 + ZeroInitSize: 32 + - Name: Out5 + Format: Int16 + Stride: 8 + ZeroInitSize: 8 + - Name: ExpectedOut1 + Format: Int16 + Stride: 8 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: ExpectedOut2 + Format: Int16 + Stride: 8 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: ExpectedOut3 + Format: Int16 + Stride: 8 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: ExpectedOut4 + Format: Int16 + Stride: 8 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: ExpectedOut5 + Format: Int16 + Stride: 8 + Data: [ 1, 2, 3, 4 ] + - Name: UIn + Format: UInt16 + Stride: 2 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UOut1 + Format: UInt16 + Stride: 8 + ZeroInitSize: 32 + - Name: UOut2 + Format: UInt16 + Stride: 8 + ZeroInitSize: 32 + - Name: UOut3 + Format: UInt16 + Stride: 8 + ZeroInitSize: 32 + - Name: UOut4 + Format: UInt16 + Stride: 8 + ZeroInitSize: 32 + - Name: UOut5 + Format: UInt16 + Stride: 8 + ZeroInitSize: 8 + - Name: UExpectedOut1 + Format: UInt16 + Stride: 8 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: UExpectedOut2 + Format: UInt16 + Stride: 8 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: UExpectedOut3 + Format: UInt16 + Stride: 8 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: UExpectedOut4 + Format: UInt16 + Stride: 8 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UExpectedOut5 + Format: UInt16 + Stride: 2 + Data: [ 1, 2, 3, 4 ] + +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + - Result: UExpectedOut1 + Rule: BufferExact + Actual: UOut1 + Expected: UExpectedOut1 + - Result: UExpectedOut2 + Rule: BufferExact + Actual: UOut2 + Expected: UExpectedOut2 + - Result: UExpectedOut3 + Rule: BufferExact + Actual: UOut3 + Expected: UExpectedOut3 + - Result: UExpectedOut4 + Rule: BufferExact + Actual: UOut4 + Expected: UExpectedOut4 + - Result: UExpectedOut5 + Rule: BufferExact + Actual: UOut5 + Expected: UExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + - Name: UIn + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + - Name: UOut1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 7 + Space: 0 + VulkanBinding: + Binding: 7 + - Name: UOut2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 8 + Space: 0 + VulkanBinding: + Binding: 8 + - Name: UOut3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 9 + Space: 0 + VulkanBinding: + Binding: 9 + - Name: UOut4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 10 + Space: 0 + VulkanBinding: + Binding: 10 + - Name: UOut5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 11 + Space: 0 + VulkanBinding: + Binding: 11 + +... +#--- end + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# RUN: split-file %s %t +# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveActiveMax.int32.test b/test/WaveOps/WaveActiveMax.int32.test new file mode 100644 index 00000000..0aa6a43b --- /dev/null +++ b/test/WaveOps/WaveActiveMax.int32.test @@ -0,0 +1,329 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int2 +RWStructuredBuffer Out3 : register(u3); // test int3 +RWStructuredBuffer Out4 : register(u4); // test int4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +// uints +StructuredBuffer UIn : register(t6); +RWStructuredBuffer UOut1 : register(u7); +RWStructuredBuffer UOut2 : register(u8); +RWStructuredBuffer UOut3 : register(u9); +RWStructuredBuffer UOut4 : register(u10); +RWStructuredBuffer UOut5 : register(u11); + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + int4 v = In[tid.x]; + + int s1 = WaveActiveMax( v.x ); + int s2 = tid.x < 3 ? WaveActiveMax( v.x ) : 0; + int s3 = tid.x < 2 ? WaveActiveMax( v.x ) : 0; + int s4 = tid.x < 1 ? WaveActiveMax( v.x ) : 0; + + int2 v2_1 = WaveActiveMax( v.xy ); + int2 v2_2 = tid.x < 3 ? WaveActiveMax( v.xy ) : int2(0,0); + int2 v2_3 = tid.x < 2 ? WaveActiveMax( v.xy ) : int2(0,0); + int2 v2_4 = tid.x < 1 ? WaveActiveMax( v.xy ) : int2(0,0); + + int3 v3_1 = WaveActiveMax( v.xyz ); + int3 v3_2 = tid.x < 3 ? WaveActiveMax( v.xyz ) : int3(0,0,0); + int3 v3_3 = tid.x < 2 ? WaveActiveMax( v.xyz ) : int3(0,0,0); + int3 v3_4 = tid.x < 1 ? WaveActiveMax( v.xyz ) : int3(0,0,0); + + int4 v4_1 = WaveActiveMax( v ); + int4 v4_2 = tid.x < 3 ? WaveActiveMax( v ) : int4(0,0,0,0); + int4 v4_3 = tid.x < 2 ? WaveActiveMax( v ) : int4(0,0,0,0); + int4 v4_4 = tid.x < 1 ? WaveActiveMax( v ) : int4(0,0,0,0); + + int scalars[4] = { s4, s3, s2, s1 }; + int2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + int3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + int4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveActiveMax(int4(1,2,3,4)); + + // UINT case + + uint4 uv = UIn[tid.x]; + + uint us1 = WaveActiveMax( uv.x ); + uint us2 = tid.x < 3 ? WaveActiveMax( uv.x ) : 0; + uint us3 = tid.x < 2 ? WaveActiveMax( uv.x ) : 0; + uint us4 = tid.x < 1 ? WaveActiveMax( uv.x ) : 0; + + uint2 uv2_1 = WaveActiveMax( uv.xy ); + uint2 uv2_2 = tid.x < 3 ? WaveActiveMax( uv.xy ) : uint2(0,0); + uint2 uv2_3 = tid.x < 2 ? WaveActiveMax( uv.xy ) : uint2(0,0); + uint2 uv2_4 = tid.x < 1 ? WaveActiveMax( uv.xy ) : uint2(0,0); + + uint3 uv3_1 = WaveActiveMax( uv.xyz ); + uint3 uv3_2 = tid.x < 3 ? WaveActiveMax( uv.xyz ) : uint3(0,0,0); + uint3 uv3_3 = tid.x < 2 ? WaveActiveMax( uv.xyz ) : uint3(0,0,0); + uint3 uv3_4 = tid.x < 1 ? WaveActiveMax( uv.xyz ) : uint3(0,0,0); + + uint4 uv4_1 = WaveActiveMax( uv ); + uint4 uv4_2 = tid.x < 3 ? WaveActiveMax( uv ) : uint4(0,0,0,0); + uint4 uv4_3 = tid.x < 2 ? WaveActiveMax( uv ) : uint4(0,0,0,0); + uint4 uv4_4 = tid.x < 1 ? WaveActiveMax( uv ) : uint4(0,0,0,0); + + uint uscalars[4] = { us4, us3, us2, us1 }; + uint2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; + uint3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; + uint4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; + + UOut1[tid.x].x = uscalars[tid.x]; + UOut2[tid.x].xy = uvec2s[tid.x]; + UOut3[tid.x].xyz = uvec3s[tid.x]; + UOut4[tid.x] = uvec4s[tid.x]; + + // constant folding case + UOut5[0] = WaveActiveMax(uint4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Int32 + Stride: 16 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: Out1 + Format: Int32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out2 + Format: Int32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out3 + Format: Int32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out4 + Format: Int32 + Stride: 16 + ZeroInitSize: 64 + - Name: Out5 + Format: Int32 + Stride: 16 + ZeroInitSize: 16 + - Name: ExpectedOut1 + Format: Int32 + Stride: 16 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: ExpectedOut2 + Format: Int32 + Stride: 16 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: ExpectedOut3 + Format: Int32 + Stride: 16 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: ExpectedOut4 + Format: Int32 + Stride: 16 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: ExpectedOut5 + Format: Int32 + Stride: 16 + Data: [ 1, 2, 3, 4 ] + - Name: UIn + Format: UInt32 + Stride: 16 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UOut1 + Format: UInt32 + Stride: 16 + ZeroInitSize: 64 + - Name: UOut2 + Format: UInt32 + Stride: 16 + ZeroInitSize: 64 + - Name: UOut3 + Format: UInt32 + Stride: 16 + ZeroInitSize: 64 + - Name: UOut4 + Format: UInt32 + Stride: 16 + ZeroInitSize: 64 + - Name: UOut5 + Format: UInt32 + Stride: 16 + ZeroInitSize: 16 + - Name: UExpectedOut1 + Format: UInt32 + Stride: 16 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: UExpectedOut2 + Format: UInt32 + Stride: 16 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: UExpectedOut3 + Format: UInt32 + Stride: 16 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: UExpectedOut4 + Format: UInt32 + Stride: 16 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UExpectedOut5 + Format: UInt32 + Stride: 4 + Data: [ 1, 2, 3, 4 ] + +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + - Result: UExpectedOut1 + Rule: BufferExact + Actual: UOut1 + Expected: UExpectedOut1 + - Result: UExpectedOut2 + Rule: BufferExact + Actual: UOut2 + Expected: UExpectedOut2 + - Result: UExpectedOut3 + Rule: BufferExact + Actual: UOut3 + Expected: UExpectedOut3 + - Result: UExpectedOut4 + Rule: BufferExact + Actual: UOut4 + Expected: UExpectedOut4 + - Result: UExpectedOut5 + Rule: BufferExact + Actual: UOut5 + Expected: UExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + - Name: UIn + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + - Name: UOut1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 7 + Space: 0 + VulkanBinding: + Binding: 7 + - Name: UOut2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 8 + Space: 0 + VulkanBinding: + Binding: 8 + - Name: UOut3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 9 + Space: 0 + VulkanBinding: + Binding: 9 + - Name: UOut4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 10 + Space: 0 + VulkanBinding: + Binding: 10 + - Name: UOut5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 11 + Space: 0 + VulkanBinding: + Binding: 11 + +... +#--- end + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/WaveOps/WaveActiveMax.int64.test b/test/WaveOps/WaveActiveMax.int64.test new file mode 100644 index 00000000..41872738 --- /dev/null +++ b/test/WaveOps/WaveActiveMax.int64.test @@ -0,0 +1,332 @@ +#--- source.hlsl +StructuredBuffer In : register(t0); +RWStructuredBuffer Out1 : register(u1); // test scalar +RWStructuredBuffer Out2 : register(u2); // test int64_t2 +RWStructuredBuffer Out3 : register(u3); // test int64_t3 +RWStructuredBuffer Out4 : register(u4); // test int64_t4 +RWStructuredBuffer Out5 : register(u5); // constant folding + +// uint64_ts +StructuredBuffer UIn : register(t6); +RWStructuredBuffer UOut1 : register(u7); +RWStructuredBuffer UOut2 : register(u8); +RWStructuredBuffer UOut3 : register(u9); +RWStructuredBuffer UOut4 : register(u10); +RWStructuredBuffer UOut5 : register(u11); + +[numthreads(4,1,1)] +void main(uint3 tid : SV_GroupThreadID) +{ + int64_t4 v = In[tid.x]; + + int64_t s1 = WaveActiveMax( v.x ); + int64_t s2 = tid.x < 3 ? WaveActiveMax( v.x ) : 0; + int64_t s3 = tid.x < 2 ? WaveActiveMax( v.x ) : 0; + int64_t s4 = tid.x < 1 ? WaveActiveMax( v.x ) : 0; + + int64_t2 v2_1 = WaveActiveMax( v.xy ); + int64_t2 v2_2 = tid.x < 3 ? WaveActiveMax( v.xy ) : int64_t2(0,0); + int64_t2 v2_3 = tid.x < 2 ? WaveActiveMax( v.xy ) : int64_t2(0,0); + int64_t2 v2_4 = tid.x < 1 ? WaveActiveMax( v.xy ) : int64_t2(0,0); + + int64_t3 v3_1 = WaveActiveMax( v.xyz ); + int64_t3 v3_2 = tid.x < 3 ? WaveActiveMax( v.xyz ) : int64_t3(0,0,0); + int64_t3 v3_3 = tid.x < 2 ? WaveActiveMax( v.xyz ) : int64_t3(0,0,0); + int64_t3 v3_4 = tid.x < 1 ? WaveActiveMax( v.xyz ) : int64_t3(0,0,0); + + int64_t4 v4_1 = WaveActiveMax( v ); + int64_t4 v4_2 = tid.x < 3 ? WaveActiveMax( v ) : int64_t4(0,0,0,0); + int64_t4 v4_3 = tid.x < 2 ? WaveActiveMax( v ) : int64_t4(0,0,0,0); + int64_t4 v4_4 = tid.x < 1 ? WaveActiveMax( v ) : int64_t4(0,0,0,0); + + int64_t scalars[4] = { s4, s3, s2, s1 }; + int64_t2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 }; + int64_t3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 }; + int64_t4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 }; + + Out1[tid.x].x = scalars[tid.x]; + Out2[tid.x].xy = vec2s[tid.x]; + Out3[tid.x].xyz = vec3s[tid.x]; + Out4[tid.x] = vec4s[tid.x]; + + // constant folding case + Out5[0] = WaveActiveMax(int64_t4(1,2,3,4)); + + // UINT64_t case + + uint64_t4 uv = UIn[tid.x]; + + uint64_t us1 = WaveActiveMax( uv.x ); + uint64_t us2 = tid.x < 3 ? WaveActiveMax( uv.x ) : 0; + uint64_t us3 = tid.x < 2 ? WaveActiveMax( uv.x ) : 0; + uint64_t us4 = tid.x < 1 ? WaveActiveMax( uv.x ) : 0; + + uint64_t2 uv2_1 = WaveActiveMax( uv.xy ); + uint64_t2 uv2_2 = tid.x < 3 ? WaveActiveMax( uv.xy ) : uint64_t2(0,0); + uint64_t2 uv2_3 = tid.x < 2 ? WaveActiveMax( uv.xy ) : uint64_t2(0,0); + uint64_t2 uv2_4 = tid.x < 1 ? WaveActiveMax( uv.xy ) : uint64_t2(0,0); + + uint64_t3 uv3_1 = WaveActiveMax( uv.xyz ); + uint64_t3 uv3_2 = tid.x < 3 ? WaveActiveMax( uv.xyz ) : uint64_t3(0,0,0); + uint64_t3 uv3_3 = tid.x < 2 ? WaveActiveMax( uv.xyz ) : uint64_t3(0,0,0); + uint64_t3 uv3_4 = tid.x < 1 ? WaveActiveMax( uv.xyz ) : uint64_t3(0,0,0); + + uint64_t4 uv4_1 = WaveActiveMax( uv ); + uint64_t4 uv4_2 = tid.x < 3 ? WaveActiveMax( uv ) : uint64_t4(0,0,0,0); + uint64_t4 uv4_3 = tid.x < 2 ? WaveActiveMax( uv ) : uint64_t4(0,0,0,0); + uint64_t4 uv4_4 = tid.x < 1 ? WaveActiveMax( uv ) : uint64_t4(0,0,0,0); + + uint64_t uscalars[4] = { us4, us3, us2, us1 }; + uint64_t2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 }; + uint64_t3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 }; + uint64_t4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 }; + + UOut1[tid.x].x = uscalars[tid.x]; + UOut2[tid.x].xy = uvec2s[tid.x]; + UOut3[tid.x].xyz = uvec3s[tid.x]; + UOut4[tid.x] = uvec4s[tid.x]; + + // constant folding case + UOut5[0] = WaveActiveMax(uint64_t4(1,2,3,4)); +} + +//--- pipeline.yaml + +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [1, 1, 1] +Buffers: + - Name: In + Format: Int64 + Stride: 32 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: Out1 + Format: Int64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out2 + Format: Int64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out3 + Format: Int64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out4 + Format: Int64 + Stride: 32 + ZeroInitSize: 128 + - Name: Out5 + Format: Int64 + Stride: 32 + ZeroInitSize: 32 + - Name: ExpectedOut1 + Format: Int64 + Stride: 32 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: ExpectedOut2 + Format: Int64 + Stride: 32 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: ExpectedOut3 + Format: Int64 + Stride: 32 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: ExpectedOut4 + Format: Int64 + Stride: 32 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: ExpectedOut5 + Format: Int64 + Stride: 8 + Data: [ 1, 2, 3, 4 ] + - Name: UIn + Format: UInt64 + Stride: 32 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UOut1 + Format: UInt64 + Stride: 32 + ZeroInitSize: 128 + - Name: UOut2 + Format: UInt64 + Stride: 32 + ZeroInitSize: 128 + - Name: UOut3 + Format: UInt64 + Stride: 32 + ZeroInitSize: 128 + - Name: UOut4 + Format: UInt64 + Stride: 32 + ZeroInitSize: 128 + - Name: UOut5 + Format: UInt64 + Stride: 32 + ZeroInitSize: 32 + - Name: UExpectedOut1 + Format: UInt64 + Stride: 32 + Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ] + - Name: UExpectedOut2 + Format: UInt64 + Stride: 32 + Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ] + - Name: UExpectedOut3 + Format: UInt64 + Stride: 32 + Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ] + - Name: UExpectedOut4 + Format: UInt64 + Stride: 32 + Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ] + - Name: UExpectedOut5 + Format: UInt64 + Stride: 8 + Data: [ 1, 2, 3, 4 ] + +Results: + - Result: ExpectedOut1 + Rule: BufferExact + Actual: Out1 + Expected: ExpectedOut1 + - Result: ExpectedOut2 + Rule: BufferExact + Actual: Out2 + Expected: ExpectedOut2 + - Result: ExpectedOut3 + Rule: BufferExact + Actual: Out3 + Expected: ExpectedOut3 + - Result: ExpectedOut4 + Rule: BufferExact + Actual: Out4 + Expected: ExpectedOut4 + - Result: ExpectedOut5 + Rule: BufferExact + Actual: Out5 + Expected: ExpectedOut5 + - Result: UExpectedOut1 + Rule: BufferExact + Actual: UOut1 + Expected: UExpectedOut1 + - Result: UExpectedOut2 + Rule: BufferExact + Actual: UOut2 + Expected: UExpectedOut2 + - Result: UExpectedOut3 + Rule: BufferExact + Actual: UOut3 + Expected: UExpectedOut3 + - Result: UExpectedOut4 + Rule: BufferExact + Actual: UOut4 + Expected: UExpectedOut4 + - Result: UExpectedOut5 + Rule: BufferExact + Actual: UOut5 + Expected: UExpectedOut5 +DescriptorSets: + - Resources: + - Name: In + Kind: StructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: Out1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 + - Name: Out2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 2 + Space: 0 + VulkanBinding: + Binding: 2 + - Name: Out3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 3 + Space: 0 + VulkanBinding: + Binding: 3 + - Name: Out4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 4 + Space: 0 + VulkanBinding: + Binding: 4 + - Name: Out5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 5 + Space: 0 + VulkanBinding: + Binding: 5 + - Name: UIn + Kind: StructuredBuffer + DirectXBinding: + Register: 6 + Space: 0 + VulkanBinding: + Binding: 6 + - Name: UOut1 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 7 + Space: 0 + VulkanBinding: + Binding: 7 + - Name: UOut2 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 8 + Space: 0 + VulkanBinding: + Binding: 8 + - Name: UOut3 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 9 + Space: 0 + VulkanBinding: + Binding: 9 + - Name: UOut4 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 10 + Space: 0 + VulkanBinding: + Binding: 10 + - Name: UOut5 + Kind: RWStructuredBuffer + DirectXBinding: + Register: 11 + Space: 0 + VulkanBinding: + Binding: 11 + +... +#--- end + +# Bug https://github.com/llvm/llvm-project/issues/156775 +# XFAIL: Clang + +# Bug https://github.com/llvm/offload-test-suite/issues/393 +# XFAIL: Metal + +# Bug https://github.com/llvm/offload-test-suite/issues/430 +# XFAIL: DirectX && WARP + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o