diff --git a/docs/opentitan/ot_darjeeling.md b/docs/opentitan/ot_darjeeling.md
index 23b95dc23cc77..c3980084ade24 100644
--- a/docs/opentitan/ot_darjeeling.md
+++ b/docs/opentitan/ot_darjeeling.md
@@ -2,7 +2,7 @@
 
 ## Supported version
 
-Please check out `hw/opentitan/ot_ref.log`
+Please check out the `ot_darjeeling.c` file header.
 
 ## Supported devices
 
diff --git a/hw/opentitan/ot_aes.c b/hw/opentitan/ot_aes.c
index 119603073eb88..c336773364963 100644
--- a/hw/opentitan/ot_aes.c
+++ b/hw/opentitan/ot_aes.c
@@ -1132,9 +1132,8 @@ static uint64_t ot_aes_read(void *opaque, hwaddr addr, unsigned size)
     case R_DATA_IN_2:
     case R_DATA_IN_3:
     case R_TRIGGER:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0u;
         break;
     case R_IV_0:
@@ -1174,9 +1173,8 @@ static uint64_t ot_aes_read(void *opaque, hwaddr addr, unsigned size)
         }
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0u;
         break;
     }
@@ -1216,9 +1214,8 @@ static void ot_aes_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_DATA_OUT_2:
     case R_DATA_OUT_3:
     case R_STATUS:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     case R_KEY_SHARE0_0:
     case R_KEY_SHARE0_1:
@@ -1336,9 +1333,8 @@ static void ot_aes_write(void *opaque, hwaddr addr, uint64_t val64,
         ot_aes_handle_trigger(s);
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_alert.c b/hw/opentitan/ot_alert.c
index 8310dca09cb39..71eacd1501696 100644
--- a/hw/opentitan/ot_alert.c
+++ b/hw/opentitan/ot_alert.c
@@ -814,9 +814,8 @@ static uint64_t ot_alert_regs_read(void *opaque, hwaddr addr, unsigned size)
     hwaddr reg = R32_OFF(addr);
 
     if (reg >= s->reg_count) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s:Invalid register 0x%03" HWADDR_PRIx "\n", __func__,
-                      addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid register 0x%03x\n",
+                      __func__, (uint32_t)addr);
         return 0;
     }
 
@@ -843,9 +842,8 @@ static void ot_alert_regs_write(void *opaque, hwaddr addr, uint64_t val64,
                             pc);
 
     if (reg >= s->reg_count) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s:Invalid register 0x%03" HWADDR_PRIx "\n", __func__,
-                      addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid register 0x%03x\n",
+                      __func__, (uint32_t)addr);
         return;
     }
 
diff --git a/hw/opentitan/ot_aon_timer.c b/hw/opentitan/ot_aon_timer.c
index 99d9c85eb552b..ac9e033a70cc5 100644
--- a/hw/opentitan/ot_aon_timer.c
+++ b/hw/opentitan/ot_aon_timer.c
@@ -401,14 +401,13 @@ static uint64_t ot_aon_timer_read(void *opaque, hwaddr addr, unsigned size)
     }
     case R_ALERT_TEST:
     case R_INTR_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -548,8 +547,8 @@ static void ot_aon_timer_write(void *opaque, hwaddr addr, uint64_t value,
         /* ignore write, in QEMU wkup_cause is always 0 */
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
     }
 }
 
diff --git a/hw/opentitan/ot_ast_dj.c b/hw/opentitan/ot_ast_dj.c
index dc9ce59f31d62..231e04c3e7b88 100644
--- a/hw/opentitan/ot_ast_dj.c
+++ b/hw/opentitan/ot_ast_dj.c
@@ -389,8 +389,8 @@ static uint64_t ot_ast_dj_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->regsb[reg - R_REGB0];
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -463,8 +463,8 @@ static void ot_ast_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         s->regsb[reg - R_REGB0] = val32;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_ast_eg.c b/hw/opentitan/ot_ast_eg.c
index af0c89f41255d..89b4bf02c78db 100644
--- a/hw/opentitan/ot_ast_eg.c
+++ b/hw/opentitan/ot_ast_eg.c
@@ -387,8 +387,8 @@ static uint64_t ot_ast_eg_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->regsb[reg - R_REGB0];
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -461,8 +461,8 @@ static void ot_ast_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         s->regsb[reg - R_REGB0] = val32;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_clkmgr.c b/hw/opentitan/ot_clkmgr.c
index 86984a0665d4b..cab6f467f53e8 100644
--- a/hw/opentitan/ot_clkmgr.c
+++ b/hw/opentitan/ot_clkmgr.c
@@ -1032,9 +1032,8 @@ static uint64_t ot_clkmgr_read(void *opaque, hwaddr addr, unsigned size)
         val32 = ot_clkmgr_get_clock_hints(s);
         break;
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
@@ -1096,8 +1095,8 @@ static uint64_t ot_clkmgr_read(void *opaque, hwaddr addr, unsigned size)
         break;
     default:
         val32 = 0;
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 
@@ -1181,9 +1180,8 @@ static void ot_clkmgr_write(void *opaque, hwaddr addr, uint64_t val64,
         break;
     case R_EXTCLK_STATUS:
     case R_CLK_HINTS_STATUS:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
         break;
@@ -1271,13 +1269,12 @@ static void ot_clkmgr_write(void *opaque, hwaddr addr, uint64_t val64,
         s->regs[reg_err] &= ~val32; /* RW1C */
         break;
     case R_FATAL_ERR_CODE:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_csrng.c b/hw/opentitan/ot_csrng.c
index fac3a915dbd57..5f7ab6b236de4 100644
--- a/hw/opentitan/ot_csrng.c
+++ b/hw/opentitan/ot_csrng.c
@@ -1750,14 +1750,13 @@ static uint64_t ot_csrng_regs_read(void *opaque, hwaddr addr, unsigned size)
     case R_INTR_TEST:
     case R_ALERT_TEST:
     case R_CMD_REQ:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -1925,14 +1924,13 @@ static void ot_csrng_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_INT_STATE_VAL:
     case R_ERR_CODE:
     case R_MAIN_SM_STATE:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
         // JW: handle new registers.
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_dma.c b/hw/opentitan/ot_dma.c
index 6d4fd6a39f9fb..fe1248070e3ae 100644
--- a/hw/opentitan/ot_dma.c
+++ b/hw/opentitan/ot_dma.c
@@ -1177,15 +1177,13 @@ static uint64_t ot_dma_regs_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -1260,9 +1258,8 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_DEST_ADDR_LIMIT_LO ... R_DEST_ADDR_LIMIT_HI:
     case R_DEST_ADDR_THRESHOLD_LO ... R_DEST_ADDR_THRESHOLD_HI:
         qemu_log_mask(LOG_UNIMP,
-                      "%s: %s: Limit reg 0x%02" HWADDR_PRIx " (%s) is not "
-                      "supported\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+                      "%s: %s: Limit reg 0x%03x (%s) is not supported\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         s->regs[reg] = val32;
         break;
     case R_ENABLED_MEMORY_RANGE_BASE:
@@ -1270,9 +1267,8 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         if (!ot_dma_is_range_locked(s)) {
             s->regs[reg] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: %s: 0x%02" HWADDR_PRIx " (%s) is locked\n",
-                          __func__, s->ot_id, addr, REG_NAME(reg));
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: 0x%03x (%s) is locked\n",
+                          __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
             /* not sure what to do here, should we set an error? */
         }
         break;
@@ -1282,9 +1278,9 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         break;
     case R_HANDSHAKE_INTR:
         qemu_log_mask(LOG_UNIMP,
-                      "%s: %s: Handshake reg 0x%02" HWADDR_PRIx " (%s) is not "
+                      "%s: %s: Handshake reg 0x%03x (%s) is not "
                       "supported\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 &= R_HANDSHAKE_INTR_ENABLE_MASK;
         s->regs[reg] = val32;
         break;
@@ -1297,9 +1293,8 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             val32 &= R_RANGE_VALID_VALID_MASK;
             s->regs[reg] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: %s: 0x%02" HWADDR_PRIx " (%s) is locked\n",
-                          __func__, s->ot_id, addr, REG_NAME(reg));
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: 0x%03x (%s) is locked\n",
+                          __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         }
         break;
     case R_RANGE_REGWEN:
@@ -1353,13 +1348,12 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_CFG_REGWEN:
     case R_ERROR_CODE:
     case R_SHA2_DIGEST_0 ... R_SHA2_DIGEST_15:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_edn.c b/hw/opentitan/ot_edn.c
index 9c6865414d7f6..2acdf25ee95bb 100644
--- a/hw/opentitan/ot_edn.c
+++ b/hw/opentitan/ot_edn.c
@@ -1351,14 +1351,13 @@ static uint64_t ot_edn_regs_read(void *opaque, hwaddr addr, unsigned size)
     case R_SW_CMD_REQ:
     case R_RESEED_CMD:
     case R_GENERATE_CMD:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -1466,13 +1465,12 @@ static void ot_edn_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_SW_CMD_STS:
     case R_ERR_CODE:
     case R_MAIN_SM_STATE:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_entropy_src.c b/hw/opentitan/ot_entropy_src.c
index 0b94f6351a3d7..3acb7936a1335 100644
--- a/hw/opentitan/ot_entropy_src.c
+++ b/hw/opentitan/ot_entropy_src.c
@@ -1245,15 +1245,13 @@ ot_entropy_src_lo_regs_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_LO_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_LO_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -1281,9 +1279,8 @@ ot_entropy_src_rev_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->regs_rev[reg];
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr + REGS_REV_BASE);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr + REGS_REV_BASE);
         val32 = 0;
         break;
     }
@@ -1495,14 +1492,12 @@ static void ot_entropy_src_lo_regs_write(void *opaque, hwaddr addr,
         s->regs_lo[reg] &= val32; /* RW0C */
         break;
     case R_REGWEN:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_LO_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_LO_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
@@ -1522,15 +1517,13 @@ static void ot_entropy_src_rev_regs_write(void *opaque, hwaddr addr,
     /* NOLINTNEXTLINE(hicpp-multiway-paths-covered) */
     switch (reg) {
     case R_REV:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr + REGS_REV_BASE,
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr + REGS_REV_BASE,
                       REG_REV_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr + REGS_REV_BASE);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr + REGS_REV_BASE);
         break;
     }
 };
diff --git a/hw/opentitan/ot_flash.c b/hw/opentitan/ot_flash.c
index da7f1b7ddaa54..4558915138fd2 100644
--- a/hw/opentitan/ot_flash.c
+++ b/hw/opentitan/ot_flash.c
@@ -2364,15 +2364,13 @@ static uint64_t ot_flash_regs_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_ALERT_TEST:
     case R_PROG_FIFO:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%03" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -2400,11 +2398,10 @@ static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_INTR_STATE: {
         uint32_t rw1c_mask = INTR_CORR_ERR_MASK | INTR_OP_DONE_MASK;
         if (val32 & ~rw1c_mask) {
-            qemu_log_mask(
-                LOG_GUEST_ERROR,
-                "%s: %s: Write to R/O field in register 0x%03" HWADDR_PRIx
-                " (%s)\n",
-                __func__, s->ot_id, addr, REG_NAME(reg));
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Write to R/O field in register 0x%03x"
+                          " (%s)\n",
+                          __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         }
         val32 &= rw1c_mask;
         s->regs[reg] &= ~val32;
@@ -2701,11 +2698,10 @@ static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         uint32_t rw0c_mask = (R_FAULT_STATUS_PHY_RELBL_ERR_MASK |
                               R_FAULT_STATUS_PHY_STORAGE_ERR_MASK);
         if (val32 & ~rw0c_mask) {
-            qemu_log_mask(
-                LOG_GUEST_ERROR,
-                "%s: %s: Write to R/O field in register 0x%03" HWADDR_PRIx
-                " (%s)\n",
-                __func__, s->ot_id, addr, REG_NAME(reg));
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Write to R/O field in register 0x%03x"
+                          " (%s)\n",
+                          __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         }
         val32 &= rw0c_mask;
         val32 |= ~rw0c_mask;
@@ -2722,14 +2718,12 @@ static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_ECC_SINGLE_ERR_ADDR_1:
     case R_PHY_STATUS:
     case R_CURR_FIFO_LVL:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%03" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
@@ -2767,9 +2761,8 @@ static uint64_t ot_flash_csrs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->csrs[csr];
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -2863,9 +2856,8 @@ static void ot_flash_csrs_write(void *opaque, hwaddr addr, uint64_t val64,
         break;
     default:
         enable = false;
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 
@@ -3164,9 +3156,8 @@ static uint64_t ot_flash_mem_read(void *opaque, hwaddr addr, unsigned size)
         trace_ot_flash_mem_read_out((uint32_t)addr, size, val32, pc);
     } else {
         uint32_t pc = ibex_get_current_pc();
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx ", pc=0x%x\n",
-                      __func__, s->ot_id, addr, pc);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%06x, pc=0x%x\n",
+                      __func__, s->ot_id, (uint32_t)addr, pc);
         val32 = 0;
     }
 
diff --git a/hw/opentitan/ot_gpio_dj.c b/hw/opentitan/ot_gpio_dj.c
index 30e069eebe3c6..7eacd87e5a2a4 100644
--- a/hw/opentitan/ot_gpio_dj.c
+++ b/hw/opentitan/ot_gpio_dj.c
@@ -458,15 +458,13 @@ static uint64_t ot_gpio_dj_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0u;
         break;
     }
@@ -576,14 +574,12 @@ static void ot_gpio_dj_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_DATA_IN:
     case R_HW_STRAPS_DATA_IN:
     case R_HW_STRAPS_DATA_IN_VALID:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_gpio_eg.c b/hw/opentitan/ot_gpio_eg.c
index 60230ab4eb541..b5d97274f1356 100644
--- a/hw/opentitan/ot_gpio_eg.c
+++ b/hw/opentitan/ot_gpio_eg.c
@@ -363,15 +363,13 @@ static uint64_t ot_gpio_eg_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0u;
         break;
     }
@@ -477,14 +475,12 @@ static void ot_gpio_eg_write(void *opaque, hwaddr addr, uint64_t val64,
         s->regs[reg] = val32;
         break;
     case R_DATA_IN:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_hmac.c b/hw/opentitan/ot_hmac.c
index e6e1db210505c..bbe8152486af7 100644
--- a/hw/opentitan/ot_hmac.c
+++ b/hw/opentitan/ot_hmac.c
@@ -798,14 +798,13 @@ static uint64_t ot_hmac_regs_read(void *opaque, hwaddr addr, unsigned size)
     case R_KEY_29:
     case R_KEY_30:
     case R_KEY_31:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -1058,9 +1057,8 @@ static void ot_hmac_regs_write(void *opaque, hwaddr addr, uint64_t value,
         break;
     case R_STATUS:
     case R_ERR_CODE:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     case R_DIGEST_0:
     case R_DIGEST_1:
@@ -1081,15 +1079,14 @@ static void ot_hmac_regs_write(void *opaque, hwaddr addr, uint64_t value,
         /* ignore write and report error if engine is not idle */
         if (s->regs->cmd) {
             qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: Cannot W register 0x%02" HWADDR_PRIx
-                          " (%s) whilst non-idle\n",
-                          __func__, addr, REG_NAME(reg));
+                          "%s: Cannot W register 0x%02x (%s) whilst non-idle\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
             break;
         } else if (s->regs->cfg & R_CFG_SHA_EN_MASK) {
             qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: Cannot W register 0x%02" HWADDR_PRIx
-                          " (%s) whilst SHA Engine is enabled\n",
-                          __func__, addr, REG_NAME(reg));
+                          "%s: Cannot W register 0x%02x (%s) whilst SHA Engine "
+                          "is enabled\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
         }
 
         /*
@@ -1110,15 +1107,14 @@ static void ot_hmac_regs_write(void *opaque, hwaddr addr, uint64_t value,
         /* ignore write and report error if engine is not idle */
         if (s->regs->cmd) {
             qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: Cannot W register 0x%02" HWADDR_PRIx
-                          " (%s) whilst non-idle\n",
-                          __func__, addr, REG_NAME(reg));
+                          "%s: Cannot W register 0x%02x (%s) whilst non-idle\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
             break;
         } else if (s->regs->cfg & R_CFG_SHA_EN_MASK) {
             qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: Cannot W register 0x%02" HWADDR_PRIx
-                          " (%s) whilst SHA Engine is enabled\n",
-                          __func__, addr, REG_NAME(reg));
+                          "%s: Cannot W register 0x%02x (%s) whilst SHA Engine "
+                          "is enabled\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
         }
         s->regs->msg_length =
             (s->regs->msg_length & (0xFFFFFFFFull << 32u)) | val32;
@@ -1127,22 +1123,21 @@ static void ot_hmac_regs_write(void *opaque, hwaddr addr, uint64_t value,
         /* ignore write and report error if engine is not idle */
         if (s->regs->cmd) {
             qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: Cannot W register 0x%02" HWADDR_PRIx
-                          " (%s) whilst non-idle\n",
-                          __func__, addr, REG_NAME(reg));
+                          "%s: Cannot W register 0x%02x (%s) whilst non-idle\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
             break;
         } else if (s->regs->cfg & R_CFG_SHA_EN_MASK) {
             qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: Cannot W register 0x%02" HWADDR_PRIx
-                          " (%s) whilst SHA Engine is enabled\n",
-                          __func__, addr, REG_NAME(reg));
+                          "%s: Cannot W register 0x%02x (%s) whilst SHA Engine "
+                          "is enabled\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
         }
         s->regs->msg_length =
             ((uint64_t)val32 << 32u) | (s->regs->msg_length & 0xFFFFFFFFull);
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_i2c.c b/hw/opentitan/ot_i2c.c
index 9b43030644388..36dd02b36c5f7 100644
--- a/hw/opentitan/ot_i2c.c
+++ b/hw/opentitan/ot_i2c.c
@@ -814,15 +814,13 @@ static uint64_t ot_i2c_read(void *opaque, hwaddr addr, unsigned size)
     case R_ALERT_TEST:
     case R_FDATA:
     case R_TXDATA:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -1122,14 +1120,12 @@ static void ot_i2c_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_TARGET_FIFO_STATUS:
     case R_VAL:
     case R_ACQDATA:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_ibex_wrapper.c b/hw/opentitan/ot_ibex_wrapper.c
index e97a6847af059..1e7fc9b5340a7 100644
--- a/hw/opentitan/ot_ibex_wrapper.c
+++ b/hw/opentitan/ot_ibex_wrapper.c
@@ -1199,9 +1199,8 @@ ot_ibex_wrapper_regs_read(void *opaque, hwaddr addr, unsigned size)
     hwaddr reg = R32_OFF(addr);
 
     if (reg >= s->reg_count) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Invalid register 0x%03" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid register 0x%03x\n",
+                      __func__, s->ot_id, (uint32_t)addr);
         return 0;
     }
 
@@ -1229,9 +1228,8 @@ static void ot_ibex_wrapper_regs_write(void *opaque, hwaddr addr,
                                    val32, pc);
 
     if (reg >= s->reg_count) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Invalid register 0x%03" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid register 0x%03x\n",
+                      __func__, s->ot_id, (uint32_t)addr);
         return;
     }
 
diff --git a/hw/opentitan/ot_keymgr.c b/hw/opentitan/ot_keymgr.c
index e2dfb04e72d82..554d5cbb55ccb 100644
--- a/hw/opentitan/ot_keymgr.c
+++ b/hw/opentitan/ot_keymgr.c
@@ -2028,15 +2028,13 @@ static uint64_t ot_keymgr_read(void *opaque, hwaddr addr, unsigned size)
     }
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0u;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0u;
         break;
     }
@@ -2283,14 +2281,12 @@ static void ot_keymgr_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_SW_SHARE1_OUTPUT_6:
     case R_SW_SHARE1_OUTPUT_7:
     case R_FAULT_STATUS:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x02%" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x02%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_keymgr_dpe.c b/hw/opentitan/ot_keymgr_dpe.c
index bb99091e21347..212162bcffd13 100644
--- a/hw/opentitan/ot_keymgr_dpe.c
+++ b/hw/opentitan/ot_keymgr_dpe.c
@@ -1756,15 +1756,13 @@ static uint64_t ot_keymgr_dpe_read(void *opaque, hwaddr addr, unsigned size)
     }
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0u;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0u;
         break;
     }
@@ -1963,14 +1961,12 @@ static void ot_keymgr_dpe_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_SW_SHARE1_OUTPUT_6:
     case R_SW_SHARE1_OUTPUT_7:
     case R_FAULT_STATUS:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x02%" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x02%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_kmac.c b/hw/opentitan/ot_kmac.c
index 73be2730d291f..c072698b030c3 100644
--- a/hw/opentitan/ot_kmac.c
+++ b/hw/opentitan/ot_kmac.c
@@ -1326,15 +1326,13 @@ static uint64_t ot_kmac_regs_read(void *opaque, hwaddr addr, unsigned size)
     case R_KEY_SHARE1_14:
     case R_KEY_SHARE1_15:
     case R_KEY_LEN:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -1536,14 +1534,12 @@ static void ot_kmac_regs_write(void *opaque, hwaddr addr, uint64_t value,
     case R_STATUS:
     case R_ENTROPY_REFRESH_HASH_CNT:
     case R_ERR_CODE:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
@@ -1601,9 +1597,8 @@ static uint64_t ot_kmac_state_read(void *opaque, hwaddr addr, unsigned size)
             val32 = 0;
             break;
         default:
-            qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: %s: bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                          s->ot_id, addr);
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n",
+                          __func__, s->ot_id, (uint32_t)addr);
             val32 = 0;
             break;
         }
diff --git a/hw/opentitan/ot_lc_ctrl.c b/hw/opentitan/ot_lc_ctrl.c
index 8335850dfedfa..71ddd0f8d27d1 100644
--- a/hw/opentitan/ot_lc_ctrl.c
+++ b/hw/opentitan/ot_lc_ctrl.c
@@ -1767,15 +1767,13 @@ static uint32_t ot_lc_ctrl_regs_read(OtLcCtrlState *s, hwaddr addr,
         val32 = s->regs[reg];
         break;
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -1930,14 +1928,12 @@ static void ot_lc_ctrl_regs_write(OtLcCtrlState *s, hwaddr addr, uint32_t val32,
     case R_MANUF_STATE_5:
     case R_MANUF_STATE_6:
     case R_MANUF_STATE_7:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_mbx.c b/hw/opentitan/ot_mbx.c
index 971099d39ece9..0c7fcdeac92c0 100644
--- a/hw/opentitan/ot_mbx.c
+++ b/hw/opentitan/ot_mbx.c
@@ -323,14 +323,13 @@ static uint64_t ot_mbx_host_regs_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_HOST_INTR_TEST:
     case R_HOST_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(HOST, reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(HOST, reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -395,9 +394,8 @@ static void ot_mbx_host_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_HOST_OUT_READ_PTR:
     case R_HOST_INTR_MSG_ADDR:
     case R_HOST_INTR_MSG_DATA:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(HOST, reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(HOST, reg));
         break;
     case R_HOST_ADDRESS_RANGE_REGWEN:
         val32 &= R_HOST_ADDRESS_RANGE_REGWEN_EN_MASK;
@@ -425,9 +423,8 @@ static void ot_mbx_host_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             val32 &= ~0b11u; /*b1..b0 always 0 */
             hregs[reg] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: %s regwen protected 0x%02" HWADDR_PRIx "\n",
-                          __func__, s->ot_id, addr);
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s regwen protected 0x%02x\n",
+                          __func__, s->ot_id, (uint32_t)addr);
         }
         break;
     case R_HOST_OUT_OBJECT_SIZE:
@@ -456,8 +453,8 @@ static void ot_mbx_host_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         xtrace_ot_mbx_status(s);
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
@@ -530,9 +527,8 @@ static MemTxResult ot_mbx_sys_regs_read_with_attrs(
     switch (reg) {
     case R_DEPRECATED_MSG_ADDR:
     case R_DEPRECATED_MSG_DATA:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s deprecated reg %s 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, REG_NAME(SYS, reg), addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s deprecated reg %s 0x%02x\n",
+                      __func__, s->ot_id, REG_NAME(SYS, reg), (uint32_t)addr);
         val32 = 0;
         break;
     case R_SYS_CONTROL:
@@ -572,9 +568,8 @@ static MemTxResult ot_mbx_sys_regs_read_with_attrs(
         mres = address_space_rw(sys->ram_as, raddr, attrs, &val32,
                                 sizeof(val32), false);
         if (mres != MEMTX_OK) {
-            qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: %s Cannot read @ 0x%" HWADDR_PRIx ": %u\n",
-                          __func__, s->ot_id, raddr, mres);
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Cannot read @ 0x%x: %u\n",
+                          __func__, s->ot_id, (uint32_t)raddr, mres);
             ibex_irq_set(&s->host.alerts[ALERT_RECOVERABLE], 1);
             val32 = 0u;
         }
@@ -590,8 +585,8 @@ static MemTxResult ot_mbx_sys_regs_read_with_attrs(
         val32 = host->regs[R_HOST_INTR_MSG_DATA];
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -623,9 +618,8 @@ static MemTxResult ot_mbx_sys_regs_write_with_attrs(
     switch (reg) {
     case R_DEPRECATED_MSG_ADDR:
     case R_DEPRECATED_MSG_DATA:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s deprecated reg %s 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, REG_NAME(SYS, reg), addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s deprecated reg %s 0x%02x\n",
+                      __func__, s->ot_id, REG_NAME(SYS, reg), (uint32_t)addr);
         break;
     case R_SYS_CONTROL:
         if (ot_mbx_is_enabled(s)) {
@@ -681,9 +675,8 @@ static MemTxResult ot_mbx_sys_regs_write_with_attrs(
         mres = address_space_rw(sys->ram_as, waddr, attrs, &val32,
                                 sizeof(val32), true);
         if (mres != MEMTX_OK) {
-            qemu_log_mask(LOG_GUEST_ERROR,
-                          "%s: %s Cannot write @ 0x%" HWADDR_PRIx ": %u\n",
-                          __func__, s->ot_id, waddr, mres);
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Cannot write @ 0x%x: %u\n",
+                          __func__, s->ot_id, (uint32_t)waddr, mres);
             ot_mbx_set_error(s);
             xtrace_ot_mbx_status(s);
             ibex_irq_set(&s->host.alerts[ALERT_RECOVERABLE], 1);
@@ -721,8 +714,8 @@ static MemTxResult ot_mbx_sys_regs_write_with_attrs(
         host->regs[R_HOST_INTR_MSG_DATA] = val32;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 
diff --git a/hw/opentitan/ot_otbn.c b/hw/opentitan/ot_otbn.c
index 6200b2183c058..51d86512741bb 100644
--- a/hw/opentitan/ot_otbn.c
+++ b/hw/opentitan/ot_otbn.c
@@ -543,9 +543,8 @@ static uint64_t ot_otbn_regs_read(void *opaque, hwaddr addr, unsigned size)
                       s->ot_id, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -618,9 +617,8 @@ static void ot_otbn_regs_write(void *opaque, hwaddr addr, uint64_t val64,
                       s->ot_id, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_otp_dj.c b/hw/opentitan/ot_otp_dj.c
index eef487fd0a5f7..e1c9f231a7b31 100644
--- a/hw/opentitan/ot_otp_dj.c
+++ b/hw/opentitan/ot_otp_dj.c
@@ -654,15 +654,13 @@ static uint64_t ot_otp_dj_reg_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x02%" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -730,9 +728,8 @@ static void ot_otp_dj_reg_write(void *opaque, hwaddr addr, uint64_t value,
     case R_DIRECT_ACCESS_RDATA_0:
     case R_DIRECT_ACCESS_RDATA_1:
     case R_VENDOR_TEST_DIGEST_0 ... R_SECRET3_DIGEST_1:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%03" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         return;
     default:
         break;
@@ -801,9 +798,8 @@ static void ot_otp_dj_reg_write(void *opaque, hwaddr addr, uint64_t value,
                       s->ot_id, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_otp_eg.c b/hw/opentitan/ot_otp_eg.c
index dcabf32927c2b..1412bc6d9c67a 100644
--- a/hw/opentitan/ot_otp_eg.c
+++ b/hw/opentitan/ot_otp_eg.c
@@ -553,15 +553,13 @@ static uint64_t ot_otp_eg_reg_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x02%" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x03%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -629,9 +627,8 @@ static void ot_otp_eg_reg_write(void *opaque, hwaddr addr, uint64_t value,
     case R_DIRECT_ACCESS_RDATA_0:
     case R_DIRECT_ACCESS_RDATA_1:
     case R_VENDOR_TEST_DIGEST_0 ... R_SECRET2_DIGEST_1:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%03" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         return;
     default:
         break;
@@ -699,9 +696,8 @@ static void ot_otp_eg_reg_write(void *opaque, hwaddr addr, uint64_t value,
                       s->ot_id, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_otp_ot_be.c b/hw/opentitan/ot_otp_ot_be.c
index 05911a9059140..3940d363b8ebe 100644
--- a/hw/opentitan/ot_otp_ot_be.c
+++ b/hw/opentitan/ot_otp_ot_be.c
@@ -158,8 +158,8 @@ static uint64_t ot_otp_ot_be_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->regs[reg];
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -194,13 +194,12 @@ static void ot_otp_ot_be_write(void *opaque, hwaddr addr, uint64_t value,
         s->regs[reg] = val32;
         break;
     case R_CSR7:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x02%" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x02%x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_pinmux_dj.c b/hw/opentitan/ot_pinmux_dj.c
index 796b3debe27c6..9d2affcc791a8 100644
--- a/hw/opentitan/ot_pinmux_dj.c
+++ b/hw/opentitan/ot_pinmux_dj.c
@@ -286,14 +286,13 @@ static uint64_t ot_pinmux_dj_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = regs->wkup_cause;
         break;
     case CASE_SCALAR(ALERT_TEST):
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%03" HWADDR_PRIx "\n", __func__,
-                      addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%03x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -332,7 +331,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case CASE_RANGE(MIO_PERIPH_INSEL, PARAM_N_MIO_PERIPH_IN):
         if (OT_PINMUX_DJ_IS_REGWEN(reg, mio_periph_insel, MIO_PERIPH_INSEL)) {
             if (val32 >= PARAM_N_MIO_PERIPH_IN + 2u) {
-                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x too large: %u\n",
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
                               __func__, (unsigned)reg, val32);
                 uint32_t mask =
                     ot_pinmux_dj_sel_mask(PARAM_N_MIO_PERIPH_IN + 2u);
@@ -340,7 +339,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             }
             regs->mio_periph_insel[reg - R_MIO_PERIPH_INSEL] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -351,7 +350,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case CASE_RANGE(MIO_OUTSEL, PARAM_N_MIO_PADS):
         if (OT_PINMUX_DJ_IS_REGWEN(reg, mio_outsel, MIO_OUTSEL)) {
             if (val32 >= PARAM_N_MIO_PERIPH_OUT + 2u) {
-                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x too large: %u\n",
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
                               __func__, (unsigned)reg, val32);
                 uint32_t mask =
                     ot_pinmux_dj_sel_mask(PARAM_N_MIO_PERIPH_OUT + 2u);
@@ -359,7 +358,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             }
             regs->mio_outsel[reg - R_MIO_OUTSEL] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -375,7 +374,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             regs->mio_pad_attr[pad_no] = val32;
             ibex_irq_set(&s->mios[pad_no], PAD_ATTR_TO_IRQ(val32));
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -391,7 +390,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             regs->dio_pad_attr[pad_no] = val32;
             ibex_irq_set(&s->dios[pad_no], PAD_ATTR_TO_IRQ(val32));
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -413,7 +412,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             val32 &= R_MIO_PAD_SLEEP_EN_MASK;
             regs->mio_pad_sleep[reg - R_MIO_PAD_SLEEP] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -439,7 +438,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             val32 &= R_DIO_PAD_SLEEP_EN_MASK;
             regs->dio_pad_sleep[reg - R_DIO_PAD_SLEEP] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -456,7 +455,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             val32 &= R_WKUP_DETECTOR_EN_MASK;
             regs->wkup_detector[reg - R_WKUP_DETECTOR] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -470,7 +469,7 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         break;
     case CASE_RANGE(WKUP_DETECTOR_PADSEL, PARAM_N_WKUP_DETECT):
         if (val32 >= N_MAX_PADS) {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x too large: %u\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
                           __func__, (unsigned)reg, val32);
             uint32_t mask = ot_pinmux_dj_sel_mask(N_MAX_PADS);
             val32 &= mask;
@@ -482,8 +481,8 @@ static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         regs->wkup_cause = val32;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_pinmux_eg.c b/hw/opentitan/ot_pinmux_eg.c
index 86a350719ef0a..151643a431e2d 100644
--- a/hw/opentitan/ot_pinmux_eg.c
+++ b/hw/opentitan/ot_pinmux_eg.c
@@ -287,14 +287,13 @@ static uint64_t ot_pinmux_eg_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = regs->wkup_cause;
         break;
     case CASE_SCALAR(ALERT_TEST):
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%03" HWADDR_PRIx "\n", __func__,
-                      addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%03x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -334,7 +333,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case CASE_RANGE(MIO_PERIPH_INSEL, PARAM_N_MIO_PERIPH_IN):
         if (OT_PINMUX_EG_IS_REGWEN(reg, mio_periph_insel, MIO_PERIPH_INSEL)) {
             if (val32 >= PARAM_N_MIO_PERIPH_IN + 2u) {
-                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x too large: %u\n",
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
                               __func__, (unsigned)reg, val32);
                 uint32_t mask =
                     ot_pinmux_eg_sel_mask(PARAM_N_MIO_PERIPH_IN + 2u);
@@ -342,7 +341,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             }
             regs->mio_periph_insel[reg - R_MIO_PERIPH_INSEL] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -353,7 +352,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case CASE_RANGE(MIO_OUTSEL, PARAM_N_MIO_PADS):
         if (OT_PINMUX_EG_IS_REGWEN(reg, mio_outsel, MIO_OUTSEL)) {
             if (val32 >= PARAM_N_MIO_PERIPH_OUT + 2u) {
-                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x too large: %u\n",
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
                               __func__, (unsigned)reg, val32);
                 uint32_t mask =
                     ot_pinmux_eg_sel_mask(PARAM_N_MIO_PERIPH_OUT + 2u);
@@ -361,7 +360,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             }
             regs->mio_outsel[reg - R_MIO_OUTSEL] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -377,7 +376,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             regs->mio_pad_attr[pad_no] = val32;
             ibex_irq_set(&s->mios[pad_no], PAD_ATTR_TO_IRQ(val32));
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -393,7 +392,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             regs->dio_pad_attr[pad_no] = val32;
             ibex_irq_set(&s->dios[pad_no], PAD_ATTR_TO_IRQ(val32));
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -415,7 +414,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             val32 &= R_MIO_PAD_SLEEP_EN_MASK;
             regs->mio_pad_sleep[reg - R_MIO_PAD_SLEEP] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -441,7 +440,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             val32 &= R_DIO_PAD_SLEEP_EN_MASK;
             regs->dio_pad_sleep[reg - R_DIO_PAD_SLEEP] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -458,7 +457,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
             val32 &= R_WKUP_DETECTOR_EN_MASK;
             regs->wkup_detector[reg - R_WKUP_DETECTOR] = val32;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x access is disabled\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
                           __func__, (uint32_t)addr);
         }
         break;
@@ -472,7 +471,7 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         break;
     case CASE_RANGE(WKUP_DETECTOR_PADSEL, PARAM_N_WKUP_DETECT):
         if (val32 >= N_MAX_PADS) {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%04x too large: %u\n",
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
                           __func__, (unsigned)reg, val32);
             uint32_t mask = ot_pinmux_eg_sel_mask(N_MAX_PADS);
             val32 &= mask;
@@ -484,8 +483,8 @@ static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         regs->wkup_cause = val32;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_plic_ext.c b/hw/opentitan/ot_plic_ext.c
index 98a676e73f04d..3b15ce494209b 100644
--- a/hw/opentitan/ot_plic_ext.c
+++ b/hw/opentitan/ot_plic_ext.c
@@ -113,9 +113,8 @@ static uint64_t ot_plic_ext_msip_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->msip_regs[reg];
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%01x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -148,9 +147,8 @@ static void ot_plic_ext_msip_write(void *opaque, hwaddr addr, uint64_t val64,
         ibex_irq_set(&s->irq, (int)(bool)val32);
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%01x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
@@ -166,15 +164,13 @@ static uint64_t ot_plic_ext_alert_read(void *opaque, hwaddr addr, unsigned size)
     /* NOLINTNEXTLINE(hicpp-multiway-paths-covered) */
     switch (reg) {
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, ALERT_REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%01x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, ALERT_REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%01x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -206,9 +202,8 @@ static void ot_plic_ext_alert_write(void *opaque, hwaddr addr, uint64_t val64,
         ibex_irq_set(&s->alert, (int)(bool)val32);
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%01x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_pwrmgr.c b/hw/opentitan/ot_pwrmgr.c
index 075e7ba405647..03c95c94b048f 100644
--- a/hw/opentitan/ot_pwrmgr.c
+++ b/hw/opentitan/ot_pwrmgr.c
@@ -861,18 +861,16 @@ static uint64_t ot_pwrmgr_regs_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     case R_RESET_STATUS:
         val32 = s->regs[reg] & PWRMGR_CONFIG[s->version].reset_mask;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -973,14 +971,12 @@ static void ot_pwrmgr_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_RESET_STATUS:
     case R_ESCALATE_RESET_STATUS:
     case R_FAULT_STATUS:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_ref.log b/hw/opentitan/ot_ref.log
deleted file mode 100644
index d4017fd11a42f..0000000000000
--- a/hw/opentitan/ot_ref.log
+++ /dev/null
@@ -1,6 +0,0 @@
-# This implementation is based on the following OpenTitan RTL version:
-GIT_REPOS="https://github.com/lowRISC/opentitan"
-
-# This is Darjeeling
-# Darjeeling definition being an active WIP, reference is not yet tracked
-GIT_COMMIT="integrated_dev"
diff --git a/hw/opentitan/ot_rom_ctrl.c b/hw/opentitan/ot_rom_ctrl.c
index 746d5e19fe409..1b7af912042eb 100644
--- a/hw/opentitan/ot_rom_ctrl.c
+++ b/hw/opentitan/ot_rom_ctrl.c
@@ -984,14 +984,13 @@ static uint64_t ot_rom_ctrl_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->regs[reg];
         break;
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0u;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0u;
         break;
     }
@@ -1039,13 +1038,12 @@ static void ot_rom_ctrl_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_EXP_DIGEST_5:
     case R_EXP_DIGEST_6:
     case R_EXP_DIGEST_7:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
@@ -1072,9 +1070,8 @@ static void ot_rom_ctrl_mem_write(void *opaque, hwaddr addr, uint64_t value,
     if ((addr + size) <= s->size) {
         stn_le_p(&rom_ptr[addr], (int)size, value);
     } else {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx ", pc=0x%x\n",
-                      __func__, s->ot_id, addr, pc);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x, pc=0x%x\n",
+                      __func__, s->ot_id, (uint32_t)addr, pc);
     }
 }
 
diff --git a/hw/opentitan/ot_rstmgr.c b/hw/opentitan/ot_rstmgr.c
index 118795a3eb84d..621cae0747be5 100644
--- a/hw/opentitan/ot_rstmgr.c
+++ b/hw/opentitan/ot_rstmgr.c
@@ -429,15 +429,13 @@ static uint64_t ot_rstmgr_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->regs[reg];
         break;
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x02%" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x02%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -554,14 +552,12 @@ static void ot_rstmgr_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_CPU_INFO_ATTR:
     case R_CPU_INFO:
     case R_ERR_CODE:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x02%" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x02%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_sensor_eg.c b/hw/opentitan/ot_sensor_eg.c
index c90b9542cf311..29207eba402e4 100644
--- a/hw/opentitan/ot_sensor_eg.c
+++ b/hw/opentitan/ot_sensor_eg.c
@@ -250,14 +250,13 @@ static uint64_t ot_sensor_eg_regs_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -310,9 +309,8 @@ static void ot_sensor_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_ALERT_TRIG:
         val32 &= ALERT_SENSOR_MASK;
         s->regs[reg] = val32;
-        qemu_log_mask(LOG_UNIMP,
-                      "Unimplemented register 0x%02" HWADDR_PRIx " (%s)\n",
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
         break;
     case R_ALERT_EN_0 ... R_ALERT_EN_10:
         if (!s->regs[R_CFG_REGWEN]) {
@@ -323,9 +321,8 @@ static void ot_sensor_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         }
         val32 &= ALERT_EN_VAL_MASK;
         s->regs[reg] = val32;
-        qemu_log_mask(LOG_UNIMP,
-                      "Unimplemented register 0x%02" HWADDR_PRIx " (%s)\n",
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
         break;
     case R_FATAL_ALERT_EN:
         if (!s->regs[R_CFG_REGWEN]) {
@@ -336,28 +333,24 @@ static void ot_sensor_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         }
         val32 &= ALERT_SENSOR_MASK;
         s->regs[reg] = val32;
-        qemu_log_mask(LOG_UNIMP,
-                      "Unimplemented register 0x%02" HWADDR_PRIx " (%s)\n",
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
         break;
     case R_RECOV_ALERT:
         val32 &= ALERT_SENSOR_MASK;
         s->regs[reg] = val32;
-        qemu_log_mask(LOG_UNIMP,
-                      "Unimplemented register 0x%02" HWADDR_PRIx " (%s)\n",
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
         break;
     case R_FATAL_ALERT:
         val32 &= ALERT_SENSOR_MASK;
         s->regs[reg] = val32;
-        qemu_log_mask(LOG_UNIMP,
-                      "Unimplemented register 0x%02" HWADDR_PRIx " (%s)\n",
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
         break;
     case R_STATUS:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     case R_MANUAL_PAD_ATTR_REGWEN_0 ... R_MANUAL_PAD_ATTR_REGWEN_3:
         val32 &= MANUAL_PAD_ATTR_REGWEN_EN_MASK;
@@ -372,13 +365,12 @@ static void ot_sensor_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         }
         break;
         val32 &= MANUAL_PAD_ATTR_MASK;
-        qemu_log_mask(LOG_UNIMP,
-                      "Unimplemented register 0x%02" HWADDR_PRIx " (%s)\n",
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 };
diff --git a/hw/opentitan/ot_soc_proxy.c b/hw/opentitan/ot_soc_proxy.c
index 52a01fc6c3655..5a4632241f989 100644
--- a/hw/opentitan/ot_soc_proxy.c
+++ b/hw/opentitan/ot_soc_proxy.c
@@ -170,14 +170,13 @@ static uint64_t ot_soc_proxy_regs_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case R_INTR_TEST:
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -221,8 +220,8 @@ static void ot_soc_proxy_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         ot_soc_proxy_update_alerts(s);
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_spi_device.c b/hw/opentitan/ot_spi_device.c
index 37f80915708b5..72e34a1c863de 100644
--- a/hw/opentitan/ot_spi_device.c
+++ b/hw/opentitan/ot_spi_device.c
@@ -2005,7 +2005,7 @@ ot_spi_device_spi_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%x\n", __func__,
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
                       s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
@@ -2214,7 +2214,7 @@ static void ot_spi_device_spi_regs_write(void *opaque, hwaddr addr,
                       __func__, s->ot_id, (uint32_t)addr, SPI_REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%x\n", __func__,
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
                       s->ot_id, (uint32_t)addr);
         break;
     }
@@ -2250,12 +2250,12 @@ ot_spi_device_tpm_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->tpm_regs[reg];
         break;
     case R_TPM_READ_FIFO:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%x (%s)\n",
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
                       __func__, s->ot_id, (uint32_t)addr, TPM_REG_NAME(reg));
         val32 = 0u;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%x\n", __func__,
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
                       s->ot_id, (uint32_t)addr);
         val32 = 0u;
         break;
@@ -2312,7 +2312,7 @@ static void ot_spi_device_tpm_regs_write(void *opaque, hwaddr addr,
                       __func__, s->ot_id, (uint32_t)addr, TPM_REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%x\n", __func__,
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
                       s->ot_id, (uint32_t)addr);
         break;
     }
@@ -2329,7 +2329,7 @@ static MemTxResult ot_spi_device_buf_read_with_attrs(
 
     if (addr < SPI_SRAM_INGRESS_OFFSET) {
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: cannot read egress buffer 0x%x\n", __func__,
+                      "%s: %s: cannot read egress buffer 0x%03x\n", __func__,
                       s->ot_id, (uint32_t)addr);
         return MEMTX_DECODE_ERROR;
     }
@@ -2350,7 +2350,8 @@ static MemTxResult ot_spi_device_buf_read_with_attrs(
         val32 = s->flash.address_fifo.data[addr >> 2u];
     } else {
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Invalid ingress buffer access to 0x%x-0x%x\n",
+                      "%s: %s: Invalid ingress buffer access to "
+                      "0x%03x-0x%03x\n",
                       __func__, s->ot_id, (uint32_t)addr, (uint32_t)last);
         val32 = 0;
     }
@@ -2362,7 +2363,8 @@ static MemTxResult ot_spi_device_buf_read_with_attrs(
     val32 >>= addr_offset << 3u;
 
     uint32_t pc = ibex_get_current_pc();
-    trace_ot_spi_device_buf_read_out(s->ot_id, (uint32_t)addr, size, val32, pc);
+    trace_ot_spi_device_io_buf_read_out(s->ot_id, (uint32_t)addr, size, val32,
+                                        pc);
 
     *val64 = (uint64_t)val32;
 
@@ -2377,13 +2379,14 @@ static MemTxResult ot_spi_device_buf_write_with_attrs(
 
     uint32_t val32 = (uint32_t)val64;
     uint32_t pc = ibex_get_current_pc();
-    trace_ot_spi_device_buf_write_in(s->ot_id, (uint32_t)addr, size, val32, pc);
+    trace_ot_spi_device_io_buf_write_in(s->ot_id, (uint32_t)addr, size, val32,
+                                        pc);
 
     hwaddr last = addr + (hwaddr)(size - 1u);
 
     if (last >= SPI_SRAM_INGRESS_OFFSET) {
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: cannot write ingress buffer 0x%x\n", __func__,
+                      "%s: %s: cannot write ingress buffer 0x%03x\n", __func__,
                       s->ot_id, (uint32_t)addr);
         return MEMTX_DECODE_ERROR;
     }
diff --git a/hw/opentitan/ot_spi_host.c b/hw/opentitan/ot_spi_host.c
index 4e48ed37f7e54..6a1391d1db957 100644
--- a/hw/opentitan/ot_spi_host.c
+++ b/hw/opentitan/ot_spi_host.c
@@ -1059,9 +1059,8 @@ static uint64_t ot_spi_host_io_read(void *opaque, hwaddr addr,
     case R_ALERT_TEST:
     case R_COMMAND:
     case R_TXDATA:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0u;
         break;
     case R_INTR_STATE:
@@ -1117,9 +1116,8 @@ static uint64_t ot_spi_host_io_read(void *opaque, hwaddr addr,
     }
     default:
         val32 = 0u;
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
     }
 
     uint32_t pc = ibex_get_current_pc();
@@ -1293,9 +1291,8 @@ static void ot_spi_host_io_write(void *opaque, hwaddr addr, uint64_t val64,
         break;
     }
     case R_RXDATA:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     case R_TXDATA: {
         if (txfifo_is_full(s->tx_fifo)) {
@@ -1339,9 +1336,8 @@ static void ot_spi_host_io_write(void *opaque, hwaddr addr, uint64_t val64,
         ot_spi_host_update_event(s);
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: bad offset 0x%" HWADDR_PRIx "\n", __func__,
-                      s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_sram_ctrl.c b/hw/opentitan/ot_sram_ctrl.c
index 087363e3cac25..fc9f0b6d834e3 100644
--- a/hw/opentitan/ot_sram_ctrl.c
+++ b/hw/opentitan/ot_sram_ctrl.c
@@ -403,14 +403,13 @@ static uint64_t ot_sram_ctrl_regs_read(void *opaque, hwaddr addr, unsigned size)
         val32 = s->regs[reg];
         break;
     case R_ALERT_TEST:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -505,13 +504,12 @@ static void ot_sram_ctrl_regs_write(void *opaque, hwaddr addr, uint64_t val64,
         }
         break;
     case R_STATUS:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s R/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 };
@@ -567,7 +565,7 @@ static MemTxResult ot_sram_ctrl_mem_init_read_with_attrs(
             /* cell still flagged, i.e. not yet initialized */
             qemu_log_mask(
                 LOG_GUEST_ERROR,
-                "%s: %s: attempt to read from uninitialized cell @ 0x%08x\n",
+                "%s: %s: attempt to read from uninitialized cell @ 0x%06x\n",
                 __func__, s->ot_id, (uint32_t)addr);
 
             return MEMTX_ERROR;
diff --git a/hw/opentitan/ot_timer.c b/hw/opentitan/ot_timer.c
index ba85a1e3307b0..9f4d783beb763 100644
--- a/hw/opentitan/ot_timer.c
+++ b/hw/opentitan/ot_timer.c
@@ -266,14 +266,13 @@ static uint64_t ot_timer_read(void *opaque, hwaddr addr, unsigned size)
     }
     case R_ALERT_TEST:
     case R_INTR_TEST0:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%03x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -373,8 +372,8 @@ static void ot_timer_write(void *opaque, hwaddr addr, uint64_t value,
         ot_timer_rearm(s, false);
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
     }
 }
 
diff --git a/hw/opentitan/ot_uart.c b/hw/opentitan/ot_uart.c
index f3152935218a7..0086b2e57aebc 100644
--- a/hw/opentitan/ot_uart.c
+++ b/hw/opentitan/ot_uart.c
@@ -521,14 +521,13 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned size)
     case R_ALERT_TEST:
     case R_INTR_TEST:
     case R_WDATA:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         val32 = 0;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         val32 = 0;
         break;
     }
@@ -624,13 +623,12 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_RDATA:
     case R_FIFO_STATUS:
     case R_VAL:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
-                      addr, REG_NAME(reg));
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/ot_usbdev.c b/hw/opentitan/ot_usbdev.c
index a41ce13ba8dd3..ca1f50d6124b7 100644
--- a/hw/opentitan/ot_usbdev.c
+++ b/hw/opentitan/ot_usbdev.c
@@ -1916,13 +1916,13 @@ static uint64_t ot_usbdev_read(void *opaque, hwaddr addr, unsigned size)
     case R_USBDEV_INTR_TEST:
     case R_ALERT_TEST:
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s Read to W/O register 0x%02" HWADDR_PRIx " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+                      "%s: %s Read to W/O register 0x%02x (%s)\n", __func__,
+                      s->ot_id, (uint32_t)addr, REG_NAME(reg));
         val32 = 0u;
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         val32 = 0u;
         break;
     }
@@ -1986,9 +1986,9 @@ static void ot_usbdev_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_RXFIFO:
     case R_USBSTAT:
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: %s: write to R/O register 0x%02" HWADDR_PRIx
+                      "%s: %s: write to R/O register 0x%02x"
                       " (%s)\n",
-                      __func__, s->ot_id, addr, REG_NAME(reg));
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
         break;
     case R_PHY_CONFIG:
         /* @todo mask against actual fields? */
@@ -2075,8 +2075,8 @@ static void ot_usbdev_write(void *opaque, hwaddr addr, uint64_t val64,
                       s->ot_id, REG_NAME(reg));
         break;
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
-                      __func__, s->ot_id, addr);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
         break;
     }
 }
diff --git a/hw/opentitan/trace-events b/hw/opentitan/trace-events
index 923b41e87b6f5..3c5453f00e4f5 100644
--- a/hw/opentitan/trace-events
+++ b/hw/opentitan/trace-events
@@ -44,8 +44,8 @@ ot_aon_timer_update_clock(const char *id, int tid, uint32_t frequency) "%s: [%d]
 # ot_ast.c
 
 ot_ast_create_clock(const char *clock, unsigned frequency, const char *out) "%s @ %u Hz, out: %s"
-ot_ast_io_read_out(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_ast_io_write(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_ast_io_read_out(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_ast_io_write(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%03x (%s), val=0x%x, pc=0x%x"
 ot_ast_no_entropy(unsigned count) "only %u words available"
 ot_ast_upate_clock(const char *clock, unsigned frequency) "%s @ %u Hz"
 
@@ -138,8 +138,8 @@ ot_dma_abort(const char *id) "%s"
 ot_dma_change_state(const char *id, int line, const char *state, int stateval) "%s: @%d: %s [%d]"
 ot_dma_check_device(const char *id, const char *dir, const char *asname, uint64_t addr, uint64_t size, const char *rootname, bool ram) "%s: %s as=%s addr=0x%" PRIx64 " size:0x%" PRIx64 " %s ram:%u"
 ot_dma_complete(const char *id, int res) "%s: %d"
-ot_dma_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_dma_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_dma_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_dma_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
 ot_dma_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%01x msk:0x%01x eff:0x%01x"
 ot_dma_new_op(const char *id, const char *dir, const char *asname, const char *mname, uint64_t addr, uint64_t size) "%s: %s as:%s m:%s a:0x%" PRIx64 " s:0x%" PRIx64
 ot_dma_operation(const char *op, bool init) "%s: %u"
@@ -208,8 +208,8 @@ ot_flash_error(const char *id, const char *func, int line, const char *err) "%s:
 ot_flash_get_keymgr_secret(const char *id, const char *name, unsigned type) "%s: %s [%d]"
 ot_flash_info(const char *id, const char *func, int line, const char *msg, uint32_t value) "%s: %s:%d %s: 0x%08x"
 ot_flash_info_part(const char* id, unsigned op_addr, unsigned count, unsigned remaining, unsigned bank, unsigned infosel, unsigned addr) "%s: op_addr 0x%06x count %u remaining %u bank %u infosel %u addr 0x%06x"
-ot_flash_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_flash_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_flash_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_flash_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
 ot_flash_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%08x msk:0x%08x eff:0x%08x"
 ot_flash_lc_broadcast(const char* id, unsigned sig, bool level) "%s: bcast %u, level %u"
 ot_flash_mem_read_out(const char* id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%u), val=0x%08x, pc=0x%x"
@@ -275,8 +275,8 @@ ot_ibex_wrapper_escalate_rx(const char *id, bool level) "%s: %u"
 ot_ibex_wrapper_exit(const char *id, const char *msg, int val) "%s: %s (%d)"
 ot_ibex_wrapper_fill_entropy(const char *id, uint32_t bits, bool fips) "%s: 0x%08x fips:%u"
 ot_ibex_wrapper_info(const char *id, const char *func, int line, const char *msg) "%s: %s:%d %s"
-ot_ibex_wrapper_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%08x, pc=0x%x"
-ot_ibex_wrapper_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%08x, pc=0x%x"
+ot_ibex_wrapper_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%08x, pc=0x%x"
+ot_ibex_wrapper_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%08x, pc=0x%x"
 ot_ibex_wrapper_map(const char *id, unsigned slot, uint32_t src, uint32_t dst, uint32_t size, const char *name, uint32_t offset) "%s: region %u from 0x%08x to 0x%08x on 0x%x bytes (%s), off 0x%x"
 ot_ibex_wrapper_request_entropy(const char *id, bool again) "%s: %u"
 ot_ibex_wrapper_reset(const char *id, const char *phase) "%s: %s"
@@ -411,7 +411,7 @@ ot_otbn_proxy_push_entropy(const char * id, const char *kind, bool fips) "%s: %s
 ot_otbn_request_entropy(const char * id, unsigned ep) "%s: ep:%u"
 ot_otbn_update_alert(const char * id, int prev, int next) "%s: %d -> %d"
 
-# ot_otp.c
+# ot_otp.c, ot_otp_engine.c
 
 ot_otp_access_error_on(const char * id, int part, uint32_t addr, const char *msg) "%s: part #%d, addr 0x%04x: %s"
 ot_otp_addr_to_part(const char * id, uint32_t addr, const char *part, unsigned pix) "%s: addr %u partition %s (#%u)"
@@ -429,9 +429,9 @@ ot_otp_ecc_unrecoverable_error(const char * id, uint32_t d_i) "%s: 0x%04x"
 ot_otp_get_otp_key(const char * id, int type) "%s: type %d"
 ot_otp_initialize(const char * id) "%s"
 ot_otp_integrity_report(const char * id, const char* part, unsigned pix, const char *msg) "%s: partition %s (#%u) %s"
-ot_otp_io_reg_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_otp_io_reg_write(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_otp_io_swcfg_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_otp_io_reg_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_otp_io_reg_write(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_otp_io_swcfg_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%04x (%s), val=0x%x, pc=0x%x"
 ot_otp_keygen_entropy(const char * id, unsigned slot, bool resched) "%s: %u slots, resched: %u"
 ot_otp_lc_broadcast(const char * id, unsigned sig, bool level) "%s: bcast %u, level %u"
 ot_otp_lci_change_state(const char * id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
@@ -456,15 +456,15 @@ ot_otp_ot_be_write(uint32_t addr, const char * regname, uint32_t val, uint32_t p
 
 # ot_pinmux.c
 
-ot_pinmux_io_read_out(uint32_t addr, uint32_t val, uint32_t pc) "addr=0x%02x, val=0x%x, pc=0x%x"
-ot_pinmux_io_write(uint32_t addr, uint32_t val, uint32_t pc) "addr=0x%02x, val=0x%x, pc=0x%x"
+ot_pinmux_io_read_out(uint32_t addr, uint32_t val, uint32_t pc) "addr=0x%03x, val=0x%x, pc=0x%x"
+ot_pinmux_io_write(uint32_t addr, uint32_t val, uint32_t pc) "addr=0x%03x, val=0x%x, pc=0x%x"
 
 # ot_plic_ext.c
 
-ot_plic_ext_io_msip_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_plic_ext_io_msip_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_plic_ext_io_alert_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_plic_ext_io_alert_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_plic_ext_io_msip_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%01x (%s), val=0x%x, pc=0x%x"
+ot_plic_ext_io_msip_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%01x (%s), val=0x%x, pc=0x%x"
+ot_plic_ext_io_alert_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%01x (%s), val=0x%x, pc=0x%x"
+ot_plic_ext_io_alert_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%01x (%s), val=0x%x, pc=0x%x"
 
 # ot_pwrmgr.c
 
@@ -517,13 +517,6 @@ ot_rstmgr_sw_rst(const char *id, const char *path, bool reset) "%s: %s: reset:%u
 ot_sensor_io_read_out(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
 ot_sensor_io_write(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
 
-# ot_soc_proxy.c
-
-ot_soc_proxy_ingress_irq(const char * id, unsigned n, bool level) "%s: #%u: %u"
-ot_soc_proxy_io_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_soc_proxy_io_write(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_soc_proxy_update_irq(const char * id, unsigned n, int prev, int next) "%s: #%u %d -> %d"
-
 # ot_soc_dbg_ctrl.c
 
 ot_soc_dbg_ctrl_boot_status(const char *id, bool mclk, bool ioclk, bool otp, bool lc, bool cpu, unsigned rdone, unsigned rgood) "%s: mclk:%u ioclk:%u otp:%u lc:%u cpu_en:%u rom_done:0x%x rom_good:0x%x"
@@ -540,10 +533,15 @@ ot_soc_dbg_ctrl_soc_dbg_state(const char *id, const char *st) "%s: %s"
 ot_soc_dbg_ctrl_tick_fsm(const char *id, const char *st, uint16_t lc, bool dfti, bool lcd, bool hcb, bool bc) "%s: %s lc:0x%02x dfti:%u lcd:%u hcb:%u bc:%u"
 ot_soc_dbg_ctrl_update_policy(const char *id, const char *socdbgst, const char *fsmst, uint8_t cat_bm, bool relocked) "%s: [%s] fsm:%s cat_bm:0x%1x relocked:%u"
 
+# ot_soc_proxy.c
+
+ot_soc_proxy_ingress_irq(const char * id, unsigned n, bool level) "%s: #%u: %u"
+ot_soc_proxy_io_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_soc_proxy_io_write(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_soc_proxy_update_irq(const char * id, unsigned n, int prev, int next) "%s: #%u %d -> %d"
+
 # ot_spi_device.c
 
-ot_spi_device_buf_read_out(const char *id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%03x, sz=%u, val=0x%08x, pc=0x%x"
-ot_spi_device_buf_write_in(const char *id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%03x, sz=%u,  val=0x%08x, pc=0x%x"
 ot_spi_device_bus_change_state(const char *id, int line, const char *state, int stateval) "%s: @%d: %s [%d]"
 ot_spi_device_chr_handle_packet(const char *id, unsigned count, unsigned eot, char rx, char tx, const char *st) "%s: 0x%x bytes, eot: %u, rx: %csb, tx: %csb, mode:%s"
 ot_spi_device_chr_error(const char *id, const char *err) "%s: %s"
@@ -575,6 +573,8 @@ ot_spi_device_gen_fifo_error(const char *id, const char *msg) "%s: %s"
 ot_spi_device_gen_phase(const char *id, const char *func, unsigned off, unsigned lim, bool phase) "%s: %s off:0x%03x lim:0x%03x ph:%u"
 ot_spi_device_gen_rx_timeout(const char *id, unsigned count) "%s: %d"
 ot_spi_device_gen_update_fifo(const char *id, const char *fifo, int line, uint32_t val) "%s: %s@%d: 0x%08x"
+ot_spi_device_io_buf_read_out(const char *id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%03x, sz=%u, val=0x%08x, pc=0x%x"
+ot_spi_device_io_buf_write_in(const char *id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%03x, sz=%u,  val=0x%08x, pc=0x%x"
 ot_spi_device_io_spi_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
 ot_spi_device_io_spi_write_in(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
 ot_spi_device_set_irq(const char *id, const char *name, unsigned irq, bool level) "%s: %s [%u]: %u"
@@ -632,8 +632,8 @@ ot_sram_ctrl_update_exec(const char *id, bool cifetch, bool rifetch, bool oifetc
 
 # ot_timer.c
 
-ot_timer_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
-ot_timer_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_timer_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_timer_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
 ot_timer_timer_mod(const char *id, int64_t now, int64_t next, bool anticipate) "%s: @ %" PRId64 ": %" PRId64 " ant: %u"
 ot_timer_update_clock(const char *id, uint32_t frequency) "%s: @ %u Hz"
 ot_timer_update_irq(const char *id, bool level) "%s: %d"