*.mir contains one instruction but seems to need another one, llc bug?

[matsc-at-sics-se]

spi_get_float.mir.zip

uni import -f spi_get_float spi_get_float.mir -o spi_get_float.uni --target=X86 --explicitcallreg --maxblocksize=25 --goal=speed --copyremat --lint
consistentOperands: in operation o17, the inferred width of temporary t13 (8) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description

The culprit operation is:

    o17: [t20] <- VCVTSI2SD64rm [t19,t13,8,t18,-8,_] (mem: 0)

which indeed expects an FR64 operand. Had the code been:

    o17: [t20] <- Int_VCVTSI2SD64rm [t19,t13,8,t18,-8,_] (mem: 0)

then everything would have been fine. Does llc print the wrong instruction?

[matsc-at-sics-se]

See also GarbageCollect:

uni import -f GarbageCollect GarbageCollect.mir -o GarbageCollect.uni --target=X86 --explicitcallreg --maxblocksize=25 --goal=speed --copyremat --lint
consistentOperands: in operation o335, the inferred width of temporary t8 (8) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description
Makefile:7165: recipe for target 'GarbageCollect.uni' failed
make: [GarbageCollect.uni] Error 1 (ignored)
uni linearize GarbageCollect.uni -o GarbageCollect.lssa.uni --target=X86 --lint
consistentOperands: in operation o334, the inferred width of temporary t649 (8) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description
Makefile:7168: recipe for target 'GarbageCollect.lssa.uni' failed
make: [GarbageCollect.lssa.uni] Error 1 (ignored)
uni extend GarbageCollect.lssa.uni -o GarbageCollect.ext.uni --target=X86 --lint
consistentOperands: in operation o864, the inferred width of temporary t1159 (8) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description
Makefile:7171: recipe for target 'GarbageCollect.ext.uni' failed
make: [GarbageCollect.ext.uni] Error 1 (ignored)
uni augment GarbageCollect.ext.uni -o GarbageCollect.alt.uni --target=X86 --copyremat --lint
consistentOperands: in operation o864, the inferred width of temporary t1159 (8) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description
Makefile:7174: recipe for target 'GarbageCollect.alt.uni' failed
make: [GarbageCollect.alt.uni] Error 1 (ignored)

GarbageCollect.mir.zip

[matsc-at-sics-se]

Another, small, case is mesa.api.glNormal3d.mir, among the TOPLAS selected functions.

*.mir contains the lines:

  - { id: 0, class: fr128 }
  - { id: 1, class: fr128 }
  - { id: 2, class: fr128 }
  - { id: 3, class: vr128 }
  - { id: 4, class: vr128 }
  - { id: 5, class: vr128 }
  - { id: 6, class: fr64 }
  - { id: 7, class: fr128 }

    %2 = COPY %xmm2
    %1 = COPY %xmm1
    %0 = COPY %xmm0
    %4 = VMOVAPDrm %rip, 1, _, %const.0, _, <0x3465c00> = !{!"unison-memory-partition", i32 0} :: (load 16 from constant-pool)
    %5 = VFvXORPDrr %0, %4
    %6 = FsFLD0SD
    %7 = VCMPSDrr %0, %6, 1

x86.yaml says:

        - id:                 VCMPSDrr
          type:               linear
          operands:
           - dst:             [register, def, FR64]
           - src1:            [register, use, FR64]
           - src2:            [register, use, FR64]
           - cc:              bound
          uses:               [src1, src2, cc]
          defines:            [dst]
          size:               0
          affects:
          affected-by:
          itinerary:          IIC_SSE_ALU_F32S_RR

        - id:                 Int_VCMPSDrr
          type:               linear
          operands:
           - dst:             [register, def, VR128]
           - src1:            [register, use, VR128]
           - src:             [register, use, VR128]
           - cc:              bound
          uses:               [src1, src, cc]
          defines:            [dst]
          size:               0
          affects:
          affected-by:
          itinerary:          IIC_SSE_ALU_F32S_RR

So the *mir's VCMPSDrr instructions uses operand %6, whose width does not match the instruction description. That would seem to break a basic invariant. Work-around: detect this in uni import and insert adapter (define), (low), (combine) etc. operations?

[matsc-at-sics-se]

Fixed "well enough" in uni import, preprocess, see commit e1ed2e7..85fe370, but there is a left-over.

Summary:
Whenever a use operand whose width mismatches the target description, a "width cast" sequence of (low) or (define) + (combine) is inserted before the operation.
Whenever a def operand whose width mismatches the target description, a "width cast" sequence of (low) or (define) + (combine) is inserted after the operation.
A (copy) width mismatch is treated just like a use operand mismatch.
Left-over: (phi) width mismatches. An instance:

$ uni import --target=X86 ../experiments/x86/selected-functions/speed-toplas/mesa.polytest.tess_test_polygon.mir -o mesa.polytest.tess_test_polygon.uni  --maxblocksize=25 --explicitcallreg --goal=speed --copyremat --lint
consistentOperands: in operation o319, the inferred width of temporary t157 (16) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description
consistentOperands: in operation o325, the inferred width of temporary t160 (16) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description
consistentOperands: in operation o341, the inferred width of temporary t162 (16) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description
consistentOperands: in operation o341, the inferred width of temporary t162 (16) is inconsistent with corresponding register class (InfiniteRegisterClass M64) given in the target description
consistentOperands: in operation o356, the inferred width of temporary t179 (16) is inconsistent with corresponding register class (RegisterClass FR64) given in the target description

After preprocess:

  - { id: 42, class: fr64}
  - { id: 46, class: fr128}
  - { id: 205, class: fr64}

  bb.44 (freq 251975):
  
    PHI %41, %39, %bb.43, %44, %bb.44
    PHI %42, %205, %bb.43, %46, %bb.44
    PHI %43, %40, %bb.43, %45, %bb.44