Pausing work again. This will be completed after the Fault Configuration Pr is checked in

Author: gurasinghMS

vm/devices/pci/pci_core/src/spec.rs

@@ -433,7 +433,7 @@ pub mod caps {
 
         /// Device Control Register
         #[bitfield(u16)]
-        #[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
+        #[derive(IntoBytes, Immutable, KnownLayout, FromBytes, Inspect)]
         pub struct DeviceControl {
             pub correctable_error_reporting_enable: bool,
             pub non_fatal_error_reporting_enable: bool,

vm/devices/storage/nvme_resources/src/lib.rs

@@ -42,6 +42,8 @@ pub struct NvmeFaultControllerHandle {
     pub max_io_queues: u16,
     /// The initial set of namespaces.
     pub namespaces: Vec<NamespaceDefinition>,
+    /// Whether to enable flr support.
+    pub flr_support: bool,
 }
 
 impl ResourceId<PciDeviceHandleKind> for NvmeFaultControllerHandle {

vm/devices/storage/nvme_test/src/tests/flr_tests.rs

@@ -4,13 +4,13 @@
 //! Tests for Function Level Reset (FLR) functionality.
 
 use super::test_helpers::TestNvmeMmioRegistration;
-use crate::FaultConfiguration;
 use crate::NvmeFaultController;
 use crate::NvmeFaultControllerCaps;
 use crate::tests::test_helpers::find_pci_capability;
 use chipset_device::pci::PciConfigSpace;
 use guestmem::GuestMemory;
 use guid::Guid;
+use nvme_resources::fault::FaultConfiguration;
 use pal_async::DefaultDriver;
 use pal_async::async_test;
 use pci_core::capabilities::pci_express::PCI_EXPRESS_DEVICE_CAPS_FLR_BIT_MASK;