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1 parent 9c638ab commit a853fe1Copy full SHA for a853fe1
test/Makefile
@@ -5,7 +5,16 @@
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SIM ?= icarus
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TOPLEVEL_LANG ?= verilog
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SRC_DIR = $(PWD)/../src
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-PROJECT_SOURCES = jsilicon.v \alu.v \fsm.v \inst.v \pc.v \regfile.v \switch.v \uart.v
+
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+# 소스 지정 방법 변경 (+=)
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+PROJECT_SOURCES += jsilicon.v
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+PROJECT_SOURCES += alu.v
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+PROJECT_SOURCES += fsm.v
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+PROJECT_SOURCES += inst.v
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+PROJECT_SOURCES += pc.v
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+PROJECT_SOURCES += regfile.v
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+PROJECT_SOURCES += switch.v
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+PROJECT_SOURCES += uart.v
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ifneq ($(GATES),yes)
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