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Clarigggz OS Implementation Roadmap

Status key: [x] done · [~] partial · [ ] not started

Phase 1: Bare-Metal Foundation (RISC-V K1)

  • K1 Bootloader Integration: arch/riscv64/k1/boot.S, trap.S, switch.S
  • WFI Control: Idle loop uses wfi (RISC-V) / hlt (x86_64)
  • Vector Extension (RVV 1.0) Initialization: Boot enables VS in sstatus; core/rvv.zig verifies VLEN
  • Page Table Management: SV39 paging with identity map and MMIO mapping in kmain

Phase 2: Hexagonal Microkernel (The Core Broker)

  • Capability System: C-lists with derive, grant, and revoke
  • IPC Transport: Sync message passing with port queues and blocking send/recv
  • Scheduler: Priority queues with switch_context cooperative preemption
  • Interrupt Routing: PLIC/CLINT MMIO, IRQ router → adapter IPC delivery

Phase 3: Ports & Protocols

  • DisplayPort: Framebuffer layout and VSync event types
  • InputPort: Tactile and spatial event structures
  • NeuralPort: RVV-oriented tensor request protocol
  • Runtime Syscalls: protocols/runtime.zig yield, log, submit_intent stubs

Phase 4: Adapters (User-Space Servers)

  • Adapter Loader: core/adapter_loader.zig spawns compositor, neural, tactile threads
  • Waveguide Compositor: HW framebuffer at 0x81000000 + desktop fallback on host
  • Tactile ID Server: Intent submission via submit_intent syscall
  • Neural Engine: RVV f16 multiply in adapter loop
  • ELF Loader: core/elf_loader.zig + zig build embed-adapters blob staging
  • Agent Runtime Adapter: components/agent/main.zig + core/agent_runtime.zig tick scheduler

Phase 5: Security & "Intent-to-Unlock"

  • Physical Sequence Verifier: Tap-sequence logic in core/physical_intent.zig
  • Security Manager Wiring: handleTactileEventattemptUnlock → liability log
  • Liability Logger: Ring buffer + UART emit on unlock
  • [~] TrustZone / Secure Enclave: Clarigggz Keychain + TEE backend abstraction; Keystone SM integration WIP (KEYSTONE_INTEGRATION.md)

Phase 6: Simulator Parity (x86_64)

  • K1 Peripheral Mocks: MMIO and IRQ controller mocks in simulator/
  • End-to-End Protocol Loop: IRQ → IPC → adapter + security unlock demo
  • Agent / Enclave / Framebuffer Demos: Simulator exercises new Phase 2 subsystems
  • Keystone TEE native boot: SM reset vector + -Dtee_backend=keystone end-to-end on QEMU
  • Keychain secure enclave: Move seal/open into wallet-core / biometric enclaves
  • RVV Emulation Support: QEMU RVV or host-side vector mapping for neural tests