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pdp11_rq.c
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/* pdp11_rq.c: MSCP disk controller simulator
Copyright (c) 2002-2013, Robert M Supnik
Derived from work by Stephen F. Shirron
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
rq MSCP disk controller
23-Oct-13 RMS Revised for new boot setup routine
09-Dec-12 MB Added support for changing controller type.
24-Oct-12 MB Added mapped transfers for VAX
29-Jan-11 HUH Added RC25, RCF25 and RA80 disks
Not all disk parameters set yet
"KLESI" MSCP controller (3) / port (1) types for RC25
not yet implemented
Remarks on the RC25 disk drives:
In "real" life the RC25 drives exist in pairs only,
one RC25 (removable) and one RCF25 (fixed) in one housing.
The removable platter has always got an even drive number
(e.g. "0"), the fixed platter has always got the next (odd)
drive number (e.g. "1"). These two rules are not enforced
by the disk drive simulation.
07-Mar-11 MP Added working behaviors for removable device types.
This allows physical CDROM's to come online and be
ejected.
02-Mar-11 MP Fixed missing information from save/restore which
caused operations to not complete correctly after
a restore until the OS reset the controller.
02-Feb-11 MP Added Autosize support to rq_attach
28-Jan-11 MP Adopted use of sim_disk disk I/O library
- added support for the multiple formats sim_disk
provides (SimH, RAW, and VHD)
- adjusted to potentially leverage asynch I/O when
available
- Added differing detailed debug output via sim_debug
14-Jan-09 JH Added support for RD32 disc drive
18-Jun-07 RMS Added UNIT_IDLE flag to timer thread
31-Oct-05 RMS Fixed address width for large files
16-Aug-05 RMS Fixed C++ declaration and cast problems
22-Jul-05 RMS Fixed warning from Solaris C (Doug Gwyn)
17-Jan-05 RMS Added more RA and RD disks
31-Oct-04 RMS Added -L switch (LBNs) to RAUSER size specification
01-Oct-04 RMS Revised Unibus interface
Changed to identify as UDA50 in Unibus configurations
Changed width to be 16b in all configurations
Changed default timing for VAX
24-Jul-04 RMS VAX controllers luns start with 0 (Andreas Cejna)
05-Feb-04 RMS Revised for file I/O library
25-Jan-04 RMS Revised for device debug support
12-Jan-04 RMS Fixed bug in interrupt control (Tom Evans)
07-Oct-03 RMS Fixed problem with multiple RAUSER drives
17-Sep-03 RMS Fixed MB to LBN conversion to be more accurate
11-Jul-03 RMS Fixed bug in user disk size (Chaskiel M Grundman)
19-May-03 RMS Revised for new conditional compilation scheme
25-Apr-03 RMS Revised for extended file support
14-Mar-03 RMS Fixed variable size interaction with save/restore
27-Feb-03 RMS Added user-defined drive support
26-Feb-03 RMS Fixed bug in vector calculation for VAXen
22-Feb-03 RMS Fixed ordering bug in queue process
12-Oct-02 RMS Added multicontroller support
29-Sep-02 RMS Changed addressing to 18b in Unibus mode
Added variable address support to bootstrap
Added vector display support
Fixed status code in HBE error log
Consolidated MSCP/TMSCP header file
New data structures
16-Aug-02 RMS Removed unused variables (David Hittner)
04-May-02 RMS Fixed bug in polling loop for queued operations
26-Mar-02 RMS Fixed bug, reset routine cleared UF_WPH
09-Mar-02 RMS Adjusted delays for M+ timing bugs
04-Mar-02 RMS Added delays to initialization for M+, RSTS/E
16-Feb-02 RMS Fixed bugs in host timeout logic, boot
26-Jan-02 RMS Revised bootstrap to conform to M9312
06-Jan-02 RMS Revised enable/disable support
30-Dec-01 RMS Revised show routines
19-Dec-01 RMS Added bigger drives
17-Dec-01 RMS Added queue process
*/
#if defined (VM_PDP10) /* PDP10 version */
#error "RQDX3 not supported on PDP-10!"
#elif defined (VM_VAX) /* VAX version */
#include "vax_defs.h"
#define RQ_QTIME 100
#define RQ_XTIME 200
#define OLDPC fault_PC
extern int32 fault_PC;
#else /* PDP-11 version */
#include "pdp11_defs.h"
#define RQ_QTIME 200
#define RQ_XTIME 500
#define OLDPC MMR2
extern int32 MMR2;
#endif
#if !defined (RQ_NUMCT)
#define RQ_NUMCT 4
#elif (RQ_NUMCT > 4)
#error "Assertion failure: RQ_NUMCT exceeds 4"
#endif
#if defined (VAX_610)
#define MICROVAX1 1
#else
#define MICROVAX1 0
#endif
#include "pdp11_uqssp.h"
#include "pdp11_mscp.h"
#include "sim_disk.h"
#define UF_MSK (UF_CMR|UF_CMW) /* settable flags */
#define RQ_SH_MAX 24 /* max display wds */
#define RQ_SH_PPL 8 /* wds per line */
#define RQ_SH_DPL 4 /* desc per line */
#define RQ_SH_RI 001 /* show rings */
#define RQ_SH_FR 002 /* show free q */
#define RQ_SH_RS 004 /* show resp q */
#define RQ_SH_UN 010 /* show unit q's */
#define RQ_SH_ALL 017 /* show all */
#define RQ_CLASS 1 /* RQ class: Mass storage controllers */
#define RQ_HVER 1 /* hardware version */
#define RQ_SVER 3 /* software version */
#define RQ_DHTMO 60 /* def host timeout */
#define RQ_DCTMO 120 /* def ctrl timeout */
#define RQ_NUMDR 4 /* def # drives */
#define RQ_MAXDR 254 /* max # drives */
#define RQ_NUMBY 512 /* bytes per block */
#define RQ_MAXFR (1 << 16) /* max xfer */
#define RQ_MAPXFER (1u << 31) /* mapped xfer */
#define RQ_M_PFN 0x1FFFFF /* map entry PFN */
#define UNIT_V_ONL (DKUF_V_UF + 0) /* online */
#define UNIT_V_ATP (UNIT_V_ONL + 1) /* attn pending */
#define UNIT_V_DTYPE (UNIT_V_ATP + 1) /* drive type */
#define UNIT_W_DTYPE 6 /* 6b drive type encode */
#define UNIT_M_DTYPE ((1u << UNIT_W_DTYPE) - 1)
#define UNIT_ONL (1 << UNIT_V_ONL)
#define UNIT_ATP (1 << UNIT_V_ATP)
#define UNIT_NOAUTO DKUF_NOAUTOSIZE /* noautosize */
#define UNIT_DTYPE (UNIT_M_DTYPE << UNIT_V_DTYPE)
#define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE)
#define cpkt us9 /* current packet */
#define pktq us10 /* packet queue */
#define uf buf /* settable unit flags */
#define cnum wait /* controller index */
#define unit_plug u4 /* drive unit plug value */
#define io_status u5 /* io status from callback */
#define io_complete u6 /* io completion flag */
/* we can re-use filebuf because we don't set UNIT_BUFABLE in flags */
#define rqxb filebuf /* xfer buffer */
#define RQ_RMV(u) ((drv_tab[GET_DTYPE (u->flags)].flgs & RQDF_RMV)? \
UF_RMV: 0)
#define RQ_WPH(u) (((drv_tab[GET_DTYPE (u->flags)].flgs & RQDF_RO) || \
(u->flags & UNIT_WPRT) || sim_disk_wrp (u))? UF_WPH: 0)
#define CST_S1 0 /* init stage 1 */
#define CST_S1_WR 1 /* stage 1 wrap */
#define CST_S2 2 /* init stage 2 */
#define CST_S3 3 /* init stage 3 */
#define CST_S3_PPA 4 /* stage 3 sa wait */
#define CST_S3_PPB 5 /* stage 3 ip wait */
#define CST_S4 6 /* stage 4 */
#define CST_UP 7 /* online */
#define CST_DEAD 8 /* fatal error */
#define ERR 0 /* must be SCPE_OK! */
#define OK 1
#define RQ_TIMER (RQ_MAXDR)
#define RQ_QUEUE (RQ_MAXDR + 1)
/* Internal packet management. The real RQDX3 manages its packets as true
linked lists. However, use of actual addresses in structures won't work
with save/restore. Accordingly, the packets are an arrayed structure,
and links are actually subscripts. To minimize complexity, packet[0]
is not used (0 = end of list), and the number of packets must be a power
of two.
*/
#define RQ_NPKTS 32 /* # packets (pwr of 2) */
#define RQ_M_NPKTS (RQ_NPKTS - 1) /* mask */
#define RQ_PKT_SIZE_W 32 /* payload size (wds) */
#define RQ_PKT_SIZE (RQ_PKT_SIZE_W * sizeof (int16))
struct rqpkt {
uint16 link; /* link to next */
uint16 d[RQ_PKT_SIZE_W]; /* data */
};
/* Packet payload extraction and insertion; cp defines controller */
#define GETP(p,w,f) ((cp->pak[p].d[w] >> w##_V_##f) & w##_M_##f)
#define GETP32(p,w) (((uint32) cp->pak[p].d[w]) | \
(((uint32) cp->pak[p].d[(w)+1]) << 16))
#define PUTP32(p,w,x) cp->pak[p].d[w] = (x) & 0xFFFF; \
cp->pak[p].d[(w)+1] = ((x) >> 16) & 0xFFFF
/* Disk formats. An RQDX3 disk consists of the following regions:
XBNs Extended blocks - contain information about disk format,
also holds track being reformatted during bad block repl.
Size = sectors/track + 1, replicated 3 times.
DBNs Diagnostic blocks - used by diagnostics. Sized to pad
out the XBNs to a cylinder boundary.
LBNs Logical blocks - contain user information.
RCT Replacement control table - first block contains status,
second contains data from block being replaced, remaining
contain information about replaced bad blocks.
Size = RBNs/128 + 3, replicated 4-8 times.
RBNs Replacement blocks - used to replace bad blocks.
The simulator does not need to perform bad block replacement; the
information below is for simulating RCT reads, if required.
Note that an RA drive has a different order: LBNs, RCT, XBN, DBN;
the RBNs are spare blocks at the end of every track.
*/
#define RCT_OVHD 2 /* #ovhd blks */
#define RCT_ENTB 128 /* entries/blk */
#define RCT_END 0x80000000 /* marks RCT end */
/* The RQDX3 supports multiple disk drive types (x = not implemented):
type sec surf cyl tpg gpc RCT LBNs notes
RX18 9 1 40 9 1 - 360
RX50 10 1 80 5 16 - 800
RX33 15 2 80 2 1 - 2400
x RD50 17 4 153 ? ? ? ? Seagate ST-506
RD51 18 4 306 4 1 36*4 21600 Seagate ST-412
RD31 17 4 615 4 1 3*8 41560 Seagate ST-225
RD52 17 8 512 8 1 4*8 60480 Quantum 540, ATASI 3046, Evotek ET3540
RD32 17 6 820 6 1 4*8 83204 Seagate ST-251
RD33 17 7 1170 7 1 5*8 138565 Microscience HH-1090
RD53 17 8 1024 8 1 5*8 138672 Micropolis 1325, Micropolis 1335
RD54 17 15 1225 15 1 7*8 311200 Maxtor XT-2190
The simulator also supports larger drives that only existed
on SDI controllers (UDA50/UDA50A, KDA50, KDB50).
type sec surf cyl tpg gpc RCT LBNs
RA60 42+ 6 1600 6 1 1008 400176
RA80 31 14 546 ? ? ? 237212
RA81 51+ 14 1258 14 1 2856 891072
RA82 57+ 15 1435 15 1 3420 1216665
RA70 33+ 11 >1507 11 1 ? 547041
RA71 51+ 14 1921 14 1 1428 1367310
RA72 51+ 20 1921 20 1 2040 1953300
RA73 70+ 21 >2667 21 1 ? 3920490
RA90 69+ 13 2656 13 1 1794 2376153
RA92 73+ 13 3101 13 1 949 2940951
ESE20 4 128 480 ? ? ? 245760
ESE52 4 128 465 ? ? ? 238080
ESE56 4 128 465 ? ? ? 1196544
ESE58 4 128 465 ? ? ? 1915392
LESI attached RC25 disks (one removable, one fixed)
type sec surf cyl tpg gpc RCT LBNs
RC25 31 2 821 ? ? ? 50902
RCF25 31 2 821 ? ? ? 50902
DSSI attached ISEs, as the simulation currently stands the DSSI
devices are accessed in a pseudo-KFQSA manner -- the ISEs are
accessed as Storage System Port (SSP) devices, like the RQDX3 or
UDA50/KDA50; however the exact function of the KFQSA is not, neither
are the SHAC or EDA640 controllers.
type sec surf cyl tpg gpc RCT LBNs
RF30 37 6 1320 ? ? ? 293040
RF31 50 8 1861 ? ? ? 744400
RF35 57 14 1861 ? ? ? 1485078
x RF36 ? ? ? ? ? ? ?
RF71 37 16 1320 ? ? ? 781440
RF72 50 21 1861 ? ? ? 1954050
RF73 71 21 2621 ? ? ? 3907911
x RF74 ? ? ? ? ? ? ?
x RF75 ? ? ? ? ? ? ?
Each drive can be a different type. The drive field in the
unit flags specified the drive type and thus, indirectly,
the drive size.
*/
#define RQDF_RMV 001 /* removable */
#define RQDF_RO 002 /* read only */
#define RQDF_SDI 004 /* SDI drive */
#define RQDF_DSSI 010 /* DSSI drive */
#define RX50_DTYPE 0
#define RX50_SECT 10
#define RX50_SURF 1
#define RX50_CYL 80
#define RX50_TPG 5
#define RX50_GPC 16
#define RX50_XBN 0
#define RX50_DBN 0
#define RX50_LBN 800
#define RX50_RCTS 0
#define RX50_RCTC 0
#define RX50_RBN 0
#define RX50_MOD 7
#define RX50_MED 0x25658032
#define RX50_FLGS RQDF_RMV
#define RX33_DTYPE 1
#define RX33_SECT 15
#define RX33_SURF 2
#define RX33_CYL 80
#define RX33_TPG 2
#define RX33_GPC 1
#define RX33_XBN 0
#define RX33_DBN 0
#define RX33_LBN 2400
#define RX33_RCTS 0
#define RX33_RCTC 0
#define RX33_RBN 0
#define RX33_MOD 10
#define RX33_MED 0x25658021
#define RX33_FLGS RQDF_RMV
#define RD51_DTYPE 2
#define RD51_SECT 18
#define RD51_SURF 4
#define RD51_CYL 306
#define RD51_TPG 4
#define RD51_GPC 1
#define RD51_XBN 57
#define RD51_DBN 87
#define RD51_LBN 21600
#define RD51_RCTS 36
#define RD51_RCTC 4
#define RD51_RBN 144
#define RD51_MOD 6
#define RD51_MED 0x25644033
#define RD51_FLGS 0
#define RD31_DTYPE 3
#define RD31_SECT 17
#define RD31_SURF 4
#define RD31_CYL 615 /* last unused */
#define RD31_TPG RD31_SURF
#define RD31_GPC 1
#define RD31_XBN 54
#define RD31_DBN 14
#define RD31_LBN 41560
#define RD31_RCTS 3
#define RD31_RCTC 8
#define RD31_RBN 100
#define RD31_MOD 12
#define RD31_MED 0x2564401F
#define RD31_FLGS 0
#define RD52_DTYPE 4
#define RD52_SECT 17
#define RD52_SURF 8
#define RD52_CYL 512
#define RD52_TPG RD52_SURF
#define RD52_GPC 1
#define RD52_XBN 54
#define RD52_DBN 82
#define RD52_LBN 60480
#define RD52_RCTS 4
#define RD52_RCTC 8
#define RD52_RBN 168
#define RD52_MOD 8
#define RD52_MED 0x25644034
#define RD52_FLGS 0
#define RD53_DTYPE 5
#define RD53_SECT 17
#define RD53_SURF 8
#define RD53_CYL 1024 /* last unused */
#define RD53_TPG RD53_SURF
#define RD53_GPC 1
#define RD53_XBN 54
#define RD53_DBN 82
#define RD53_LBN 138672
#define RD53_RCTS 5
#define RD53_RCTC 8
#define RD53_RBN 280
#define RD53_MOD 9
#define RD53_MED 0x25644035
#define RD53_FLGS 0
#define RD54_DTYPE 6
#define RD54_SECT 17
#define RD54_SURF 15
#define RD54_CYL 1225 /* last unused */
#define RD54_TPG RD54_SURF
#define RD54_GPC 1
#define RD54_XBN 54
#define RD54_DBN 201
#define RD54_LBN 311200
#define RD54_RCTS 7
#define RD54_RCTC 8
#define RD54_RBN 609
#define RD54_MOD 13
#define RD54_MED 0x25644036
#define RD54_FLGS 0
#define RA82_DTYPE 7 /* SDI drive */
#define RA82_SECT 57 /* +1 spare/track */
#define RA82_SURF 15
#define RA82_CYL 1435 /* 0-1422 user */
#define RA82_TPG RA82_SURF
#define RA82_GPC 1
#define RA82_XBN 3480 /* cyl 1427-1430 */
#define RA82_DBN 3480 /* cyl 1431-1434 */
#define RA82_LBN 1216665 /* 57*15*1423 */
#define RA82_RCTS 3420 /* cyl 1423-1426 */
#define RA82_RCTC 1
#define RA82_RBN 21345 /* 1 *15*1423 */
#define RA82_MOD 11
#define RA82_MED 0x25641052
#define RA82_FLGS RQDF_SDI
#define RRD40_DTYPE 8
#define RRD40_SECT 128
#define RRD40_SURF 1
#define RRD40_CYL 10400
#define RRD40_TPG RRD40_SURF
#define RRD40_GPC 1
#define RRD40_XBN 0
#define RRD40_DBN 0
#define RRD40_LBN 1331200
#define RRD40_RCTS 0
#define RRD40_RCTC 0
#define RRD40_RBN 0
#define RRD40_MOD 26
#define RRD40_MED 0x25652228
#define RRD40_FLGS (RQDF_RMV | RQDF_RO)
#define RA72_DTYPE 9 /* SDI drive */
#define RA72_SECT 51 /* +1 spare/trk */
#define RA72_SURF 20
#define RA72_CYL 1921 /* 0-1914 user */
#define RA72_TPG RA72_SURF
#define RA72_GPC 1
#define RA72_XBN 2080 /* cyl 1917-1918? */
#define RA72_DBN 2080 /* cyl 1920-1921? */
#define RA72_LBN 1953300 /* 51*20*1915 */
#define RA72_RCTS 2040 /* cyl 1915-1916? */
#define RA72_RCTC 1
#define RA72_RBN 38300 /* 1 *20*1915 */
#define RA72_MOD 37
#define RA72_MED 0x25641048
#define RA72_FLGS RQDF_SDI
#define RA90_DTYPE 10 /* SDI drive */
#define RA90_SECT 69 /* +1 spare/trk */
#define RA90_SURF 13
#define RA90_CYL 2656 /* 0-2648 user */
#define RA90_TPG RA90_SURF
#define RA90_GPC 1
#define RA90_XBN 1820 /* cyl 2651-2652? */
#define RA90_DBN 1820 /* cyl 2653-2654? */
#define RA90_LBN 2376153 /* 69*13*2649 */
#define RA90_RCTS 1794 /* cyl 2649-2650? */
#define RA90_RCTC 1
#define RA90_RBN 34437 /* 1 *13*2649 */
#define RA90_MOD 19
#define RA90_MED 0x2564105A
#define RA90_FLGS RQDF_SDI
#define RA92_DTYPE 11 /* SDI drive */
#define RA92_SECT 73 /* +1 spare/trk */
#define RA92_SURF 13
#define RA92_CYL 3101 /* 0-3098 user */
#define RA92_TPG RA92_SURF
#define RA92_GPC 1
#define RA92_XBN 174 /* cyl 3100? */
#define RA92_DBN 788
#define RA92_LBN 2940951 /* 73*13*3099 */
#define RA92_RCTS 949 /* cyl 3099? */
#define RA92_RCTC 1
#define RA92_RBN 40287 /* 1 *13*3099 */
#define RA92_MOD 29
#define RA92_MED 0x2564105C
#define RA92_FLGS RQDF_SDI
#define RA8U_DTYPE 12 /* user defined */
#define RA8U_SECT 57 /* from RA82 */
#define RA8U_SURF 15
#define RA8U_CYL 1435 /* from RA82 */
#define RA8U_TPG RA8U_SURF
#define RA8U_GPC 1
#define RA8U_XBN 0
#define RA8U_DBN 0
#define RA8U_LBN 1216665 /* from RA82 */
#define RA8U_RCTS 400
#define RA8U_RCTC 8
#define RA8U_RBN 21345
#define RA8U_MOD 11 /* RA82 */
#define RA8U_MED 0x25641052 /* RA82 */
#define RA8U_FLGS RQDF_SDI
#define RA8U_MINC 10000 /* min cap LBNs */
#define RA8U_MAXC 4194303 /* max cap LBNs */
#define RA8U_EMAXC 2147483647 /* ext max cap */
#define RA60_DTYPE 13 /* SDI drive */
#define RA60_SECT 42 /* +1 spare/track */
#define RA60_SURF 6
#define RA60_CYL 1600 /* 0-1587 user */
#define RA60_TPG RA60_SURF
#define RA60_GPC 1
#define RA60_XBN 1032 /* cyl 1592-1595 */
#define RA60_DBN 1032 /* cyl 1596-1599 */
#define RA60_LBN 400176 /* 42*6*1588 */
#define RA60_RCTS 1008 /* cyl 1588-1591 */
#define RA60_RCTC 1
#define RA60_RBN 9528 /* 1 *6*1588 */
#define RA60_MOD 4
#define RA60_MED 0x22A4103C
#define RA60_FLGS (RQDF_RMV | RQDF_SDI)
#define RA81_DTYPE 14 /* SDI drive */
#define RA81_SECT 51 /* +1 spare/track */
#define RA81_SURF 14
#define RA81_CYL 1258 /* 0-1247 user */
#define RA81_TPG RA81_SURF
#define RA81_GPC 1
#define RA81_XBN 2436 /* cyl 1252-1254? */
#define RA81_DBN 2436 /* cyl 1255-1256? */
#define RA81_LBN 891072 /* 51*14*1248 */
#define RA81_RCTS 2856 /* cyl 1248-1251? */
#define RA81_RCTC 1
#define RA81_RBN 17472 /* 1 *14*1248 */
#define RA81_MOD 5
#define RA81_MED 0x25641051
#define RA81_FLGS RQDF_SDI
#define RA71_DTYPE 15 /* SDI drive */
#define RA71_SECT 51 /* +1 spare/track */
#define RA71_SURF 14
#define RA71_CYL 1921 /* 0-1914 user */
#define RA71_TPG RA71_SURF
#define RA71_GPC 1
#define RA71_XBN 1456 /* cyl 1917-1918? */
#define RA71_DBN 1456 /* cyl 1919-1920? */
#define RA71_LBN 1367310 /* 51*14*1915 */
#define RA71_RCTS 1428 /* cyl 1915-1916? */
#define RA71_RCTC 1
#define RA71_RBN 26810 /* 1 *14*1915 */
#define RA71_MOD 40
#define RA71_MED 0x25641047
#define RA71_FLGS RQDF_SDI
#define RD32_DTYPE 16
#define RD32_SECT 17
#define RD32_SURF 6
#define RD32_CYL 820
#define RD32_TPG RD32_SURF
#define RD32_GPC 1
#define RD32_XBN 54
#define RD32_DBN 48
#define RD32_LBN 83236
#define RD32_RCTS 4
#define RD32_RCTC 8
#define RD32_RBN 200
#define RD32_MOD 15
#define RD32_MED 0x25644020
#define RD32_FLGS 0
#define RC25_DTYPE 17 /* */
#define RC25_SECT 50 /* */
#define RC25_SURF 8
#define RC25_CYL 1260 /* */
#define RC25_TPG RC25_SURF
#define RC25_GPC 1
#define RC25_XBN 0 /* */
#define RC25_DBN 0 /* */
#define RC25_LBN 50902 /* ? 50*8*1260 ? */
#define RC25_RCTS 0 /* */
#define RC25_RCTC 1
#define RC25_RBN 0 /* */
#define RC25_MOD 2
#define RC25_MED 0x20643019
#define RC25_FLGS RQDF_RMV
#define RCF25_DTYPE 18 /* */
#define RCF25_SECT 50 /* */
#define RCF25_SURF 8
#define RCF25_CYL 1260 /* */
#define RCF25_TPG RCF25_SURF
#define RCF25_GPC 1
#define RCF25_XBN 0 /* */
#define RCF25_DBN 0 /* */
#define RCF25_LBN 50902 /* ? 50*8*1260 ? */
#define RCF25_RCTS 0 /* */
#define RCF25_RCTC 1
#define RCF25_RBN 0 /* */
#define RCF25_MOD 3
#define RCF25_MED 0x20643319
#define RCF25_FLGS 0
#define RA80_DTYPE 19 /* SDI drive */
#define RA80_SECT 31 /* +1 spare/track */
#define RA80_SURF 14
#define RA80_CYL 546 /* */
#define RA80_TPG RA80_SURF
#define RA80_GPC 1
#define RA80_XBN 0 /* */
#define RA80_DBN 0 /* */
#define RA80_LBN 237212 /* 31*14*546 */
#define RA80_RCTS 0 /* */
#define RA80_RCTC 1
#define RA80_RBN 0 /* */
#define RA80_MOD 1
#define RA80_MED 0x25641050
#define RA80_FLGS RQDF_SDI
// [RLA] Most of these RA70 parameters came from doing a DUSTAT on a real
// [RLA] RA70 drive. The remainder are just educated guesses...
#define RA70_DTYPE 20 /* SDI drive */
#define RA70_SECT 33 /* +1 spare/track */
#define RA70_SURF 11 /* tracks/cylinder */
#define RA70_CYL 1507 /* 0-1506 user */
#define RA70_TPG RA70_SURF
#define RA70_GPC 1
#define RA70_XBN 0 /* ??? */
#define RA70_DBN 0 /* ??? */
#define RA70_LBN 547041 /* 33*11*1507 */
#define RA70_RCTS 198 /* Size of the RCT */
#define RA70_RCTC 7 /* Number of RCT copies */
#define RA70_RBN 16577 /* 1*11*1507 */
#define RA70_MOD 18 /* ??? */
#define RA70_MED 0x25641046 /* RA70 MEDIA ID */
#define RA70_FLGS RQDF_SDI
// [RLA] Likewise for the RA73 ...
#define RA73_DTYPE 21 /* SDI drive */
#define RA73_SECT 70 /* +1 spare/track */
#define RA73_SURF 21 /* tracks/cylinder */
#define RA73_CYL 2667 /* 0-2666 user */
#define RA73_TPG RA73_SURF
#define RA73_GPC 1
#define RA73_XBN 0 /* ??? */
#define RA73_DBN 0 /* ??? */
#define RA73_LBN 3920490 /* 70*21*2667 */
#define RA73_RCTS 198 /* Size of the RCT ??????*/
#define RA73_RCTC 7 /* Number of RCT copies */
#define RA73_RBN 56007 /* 1*21*2667 */
#define RA73_MOD 47 /* ??? */
#define RA73_MED 0x25641049 /* RA73 MEDIA ID */
#define RA73_FLGS RQDF_SDI
/* The RF drives don't have any useful error parameters. */
/* These entries are derived from basic geometry and size */
/* info in Ultrix 4.5 disktab entries. */
#define RF30_DTYPE 22 /* DSSI drive */
#define RF30_SECT 37 /* +1 spare/track */
#define RF30_SURF 6
#define RF30_CYL 1320 /* 0-1914 user */
#define RF30_TPG RF30_SURF
#define RF30_GPC 1
#define RF30_XBN 1456 /* cyl 1917-1918? */
#define RF30_DBN 1456 /* cyl 1919-1920? */
#define RF30_LBN 293040 /* 37*6*1320 */
#define RF30_RCTS 1428 /* cyl 1915-1916? */
#define RF30_RCTC 1
#define RF30_RBN 26810 /* 1 *14*1915 */
#define RF30_MOD 21
#define RF30_MED 0x2264601E
#define RF30_FLGS RQDF_DSSI
#define RF31_DTYPE 23 /* DSSI drive */
#define RF31_SECT 50 /* +1 spare/track */
#define RF31_SURF 8
#define RF31_CYL 1861 /* 0-1860 user */
#define RF31_TPG RF31_SURF
#define RF31_GPC 1
#define RF31_XBN 1456 /* cyl 1917-1918? */
#define RF31_DBN 1456 /* cyl 1919-1920? */
#define RF31_LBN 744400 /* 50*8*1861 */
#define RF31_RCTS 1428 /* cyl 1915-1916? */
#define RF31_RCTC 1
#define RF31_RBN 26810 /* 1 *14*1915 */
#define RF31_MOD 27
#define RF31_MED 0x2264601F
#define RF31_FLGS RQDF_DSSI
#define RF35_DTYPE 24 /* DSSI drive */
#define RF35_SECT 57 /* +1 spare/track */
#define RF35_SURF 14
#define RF35_CYL 1861 /* 0-1860 user */
#define RF35_TPG RF35_SURF
#define RF35_GPC 1
#define RF35_XBN 1456 /* cyl 1917-1918? */
#define RF35_DBN 1456 /* cyl 1919-1920? */
#define RF35_LBN 1664628 /* 57*14*1861 */
#define RF35_RCTS 1428 /* cyl 1915-1916? */
#define RF35_RCTC 1
#define RF35_RBN 26810 /* 1 *14*1915 */
#define RF35_MOD 27
#define RF35_MED 0x2264601F
#define RF35_FLGS RQDF_DSSI
#define RF71_DTYPE 25 /* DSSI drive */
#define RF71_SECT 37 /* +1 spare/track */
#define RF71_SURF 16
#define RF71_CYL 1320 /* 0-1914 user */
#define RF71_TPG RF71_SURF
#define RF71_GPC 1
#define RF71_XBN 1456 /* cyl 1917-1918? */
#define RF71_DBN 1456 /* cyl 1919-1920? */
#define RF71_LBN 781440 /* 37*16*1320 */
#define RF71_RCTS 1428 /* cyl 1915-1916? */
#define RF71_RCTC 1
#define RF71_RBN 26810 /* 1 *14*1915 */
#define RF71_MOD 40
#define RF71_MED 0x22646047
#define RF71_FLGS RQDF_DSSI
#define RF72_DTYPE 26 /* DSSI drive */
#define RF72_SECT 50 /* +1 spare/track */
#define RF72_SURF 21
#define RF72_CYL 1861 /* 0-1860 user */
#define RF72_TPG RF72_SURF
#define RF72_GPC 1
#define RF72_XBN 1456 /* cyl 1917-1918? */
#define RF72_DBN 1456 /* cyl 1919-1920? */
#define RF72_LBN 1954050 /* 50*21*1861 */
#define RF72_RCTS 1428 /* cyl 1915-1916? */
#define RF72_RCTC 1
#define RF72_RBN 26810 /* 1 *14*1915 */
#define RF72_MOD 28
#define RF72_MED 0x22646048
#define RF72_FLGS RQDF_DSSI
#define RF73_DTYPE 27 /* DSSI drive */
#define RF73_SECT 71 /* +1 spare/track */
#define RF73_SURF 21
#define RF73_CYL 2621 /* 0-2620 user */
#define RF73_TPG RF73_SURF
#define RF73_GPC 1
#define RF73_XBN 1456 /* cyl 1917-1918? */
#define RF73_DBN 1456 /* cyl 1919-1920? */
#define RF73_LBN 3907911 /* 71*21*2621 */
#define RF73_RCTS 1428 /* cyl 1915-1916? */
#define RF73_RCTC 1
#define RF73_RBN 26810 /* 1 *14*1915 */
#define RF73_MOD 35
#define RF73_MED 0x22646049
#define RF73_FLGS RQDF_DSSI
/* The ESE20 and the ESE5x information comes from the "ESE50 Solid State
* Disk User Guide" (EK-ESE50-UG.B01), and the "ESE20 Solid State Disk"
* brochure.
*
* The ESE5x models are named using their "media name" from the MSCP
* reference document.
*/
#define ESE20_DTYPE 28
#define ESE20_SECT 4
#define ESE20_SURF 128
#define ESE20_CYL 480
#define ESE20_TPG ESE20_SURF
#define ESE20_GPC 1
#define ESE20_XBN 0
#define ESE20_DBN 0
#define ESE20_LBN 245760
#define ESE20_RCTS 0
#define ESE20_RCTC 1
#define ESE20_RBN 0
#define ESE20_MOD 25
#define ESE20_MED 0x254B3294
#define ESE20_FLGS RQDF_SDI
#define ESE52_DTYPE 29
#define ESE52_SECT 4
#define ESE52_SURF 128
#define ESE52_CYL 465
#define ESE52_TPG ESE52_SURF
#define ESE52_GPC 1
#define ESE52_XBN 0
#define ESE52_DBN 0
#define ESE52_LBN 238080
#define ESE52_RCTS 0
#define ESE52_RCTC 1
#define ESE52_RBN 0
#define ESE52_MOD 31
#define ESE52_MED 0x254B32B4
#define ESE52_FLGS RQDF_SDI
#define ESE56_DTYPE 30
#define ESE56_SECT 4
#define ESE56_SURF 128
#define ESE56_CYL 2337
#define ESE56_TPG ESE56_SURF
#define ESE56_GPC 1
#define ESE56_XBN 0
#define ESE56_DBN 0
#define ESE56_LBN 1196544
#define ESE56_RCTS 0
#define ESE56_RCTC 1
#define ESE56_RBN 0
#define ESE56_MOD 48
#define ESE56_MED 0x254B32B8
#define ESE56_FLGS RQDF_SDI
#define ESE58_DTYPE 31
#define ESE58_SECT 4
#define ESE58_SURF 128
#define ESE58_CYL 3741
#define ESE58_TPG ESE58_SURF
#define ESE58_GPC 1
#define ESE58_XBN 0
#define ESE58_DBN 0
#define ESE58_LBN 1915392
#define ESE58_RCTS 0
#define ESE58_RCTC 1
#define ESE58_RBN 0
#define ESE58_MOD 49
#define ESE58_MED 0x254B32BA
#define ESE58_FLGS RQDF_SDI
/* The RD33 information comes from the Ultrix-32 v4.5 disktab file and
* from Phil Budne's "dec.disks" file.
*/
#define RD33_DTYPE 32
#define RD33_SECT 17
#define RD33_SURF 7
#define RD33_CYL 1170
#define RD33_TPG RD33_SURF
#define RD33_GPC 1
#define RD33_XBN 54
#define RD33_DBN 65
#define RD33_LBN 138635
#define RD33_RCTS 5
#define RD33_RCTC 8
#define RD33_RBN 317
#define RD33_MOD 24
#define RD33_MED 0x25644021
#define RD33_FLGS 0
/* The RX18 information comes from the VT-180 Series Technical Manual
* (EK-VT18X-TM-001) and from the MSCP specification document as well as
* references in the RSX-11/M+ documentation to the RX18 existing as a
* device attachable to the RUX50.
*/
#define RX18_DTYPE 33
#define RX18_SECT 9
#define RX18_SURF 1
#define RX18_CYL 40
#define RX18_TPG RD33_SURF
#define RX18_GPC 1
#define RX18_XBN 0
#define RX18_DBN 0
#define RX18_LBN 360
#define RX18_RCTS 0
#define RX18_RCTC 0
#define RX18_RBN 0
#define RX18_MOD 17
#define RX18_MED 0x25658012
#define RX18_FLGS RQDF_RMV
/* Controller parameters */
#define DEFAULT_CTYPE 0
// AFAIK the UNIBUS KLESI and QBUS KLESI used the same controller type ...
#define KLESI_CTYPE 1 // RC25 controller (UNIBUS and QBUS both)
#define KLESI_UQPM 3
#define KLESI_MODEL 3
#define RUX50_CTYPE 2 // UNIBUS RX50-only controller
#define RUX50_UQPM 10 // this should be 10 according to the MSCP spec
#define RUX50_MODEL 10
#define UDA50A_CTYPE 3 // UNIBUS SDI (RAxx) controller
#define UDA50A_UQPM 6 // The new model - SIMH default model
#define UDA50A_MODEL 6
#define RQDX1_CTYPE 4 // QBUS RX50/RDxx controller,
#define RQDX1_UQPM 7 // first version; RQDX2 has the same id
#define RQDX1_MODEL 7
#define RQDX3_CTYPE 5 // QBUS RX50/RDxx controller
#define RQDX3_UQPM 19
#define RQDX3_MODEL 19
#define KDA50_CTYPE 6 // QBUS SDI (RAxx) controller
#define KDA50_UQPM 13 // KDA50-Q
#define KDA50_MODEL 13
#define KRQ50_CTYPE 7 // QBUS RRD40/50 CDROM controller
#define KRQ50_UQPM 16
#define KRQ50_MODEL 16
#define KRU50_CTYPE 8 // UNIBUS RRD40/50 CDROM controller
#define KRU50_UQPM 26 // unassigned in appendix C
#define KRU50_MODEL 26
#define RQDX4_CTYPE 9 // QBUS RXxx/RDxx controller
#define RQDX4_UQPM 20 // CSS, Reading Special
#define RQDX4_MODEL 20
#define UDA50_CTYPE 10 // Old UNIBUS SDI (RAxx) controller
#define UDA50_UQPM 2
#define UDA50_MODEL 2
struct drvtyp {
uint16 sect; /* sectors */
int32 surf; /* surfaces */
int32 cyl; /* cylinders */
uint16 tpg; /* trk/grp */
uint16 gpc; /* grp/cyl */
int32 xbn; /* XBN size */
int32 dbn; /* DBN size */
uint32 lbn; /* LBN size */
uint16 rcts; /* RCT size */
int32 rctc; /* RCT copies */
int32 rbn; /* RBNs */
uint16 mod; /* MSCP model */
int32 MediaId; /* MSCP media */
int32 flgs; /* flags */
const char *name; /* name */
};
#define RQ_DRV(d) \
{ d##_SECT, d##_SURF, d##_CYL, d##_TPG, \
d##_GPC, d##_XBN, d##_DBN, d##_LBN, \
d##_RCTS, d##_RCTC, d##_RBN, d##_MOD, \
d##_MED, d##_FLGS, #d }
#define RQ_SIZE(d) d##_LBN
static struct drvtyp drv_tab[] = {
RQ_DRV (RX50),
RQ_DRV (RX33),
RQ_DRV (RD51),
RQ_DRV (RD31),
RQ_DRV (RD52),
RQ_DRV (RD53),
RQ_DRV (RD54),
RQ_DRV (RA82),
RQ_DRV (RRD40),
RQ_DRV (RA72),
RQ_DRV (RA90),
RQ_DRV (RA92),
RQ_DRV (RA8U),
RQ_DRV (RA60),
RQ_DRV (RA81),
RQ_DRV (RA71),
RQ_DRV (RD32),
RQ_DRV (RC25),
RQ_DRV (RCF25),
RQ_DRV (RA80),
RQ_DRV (RA70),
RQ_DRV (RA73),
RQ_DRV (RF30),
RQ_DRV (RF31),
RQ_DRV (RF35),
RQ_DRV (RF71),
RQ_DRV (RF72),
RQ_DRV (RF73),
RQ_DRV (ESE20),
RQ_DRV (ESE52),
RQ_DRV (ESE56),
RQ_DRV (ESE58),
RQ_DRV (RD33),
RQ_DRV (RX18),
{ 0 }
};
#undef RQ_DRV
#define RQ_DRV(d) #d
static const char *drv_types[] = {
RQ_DRV (RX50),
RQ_DRV (RX33),
RQ_DRV (RD51),
RQ_DRV (RD31),