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    41 repositories

    • HighTide

      Public
      Verilog
      •
      Other
      •13•36•27•2•Updated Aug 13, 2026Aug 13, 2026

    • OpenRAM

      Public
      An open-source static random access memory (SRAM) compiler.
      pythonmagicsram
      pythonmagicsramgdsnetgenngspicenetlists
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •277•1.1k•52•10•Updated Aug 13, 2026Aug 13, 2026

    • OpenROAD-flow-scripts

      Public
      OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
      Verilog
      •
      Other
      •521•1•0•0•Updated Jul 21, 2026Jul 21, 2026

    • OpenROAD

      Public
      OpenROAD's unified application implementing an RTL-to-GDS Flow
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •985•7•0•0•Updated Jul 19, 2026Jul 19, 2026

    • vlsida-skills

      Public
      Claude Code skills for EDA tooling, cloud infrastructure, and research computing
      Tcl
      •
      BSD 3-Clause "New" or "Revised" License
      •1•1•0•0•Updated Jul 9, 2026Jul 9, 2026

    • chip-tutorials

      Public
      Python
      •
      Apache License 2.0
      •10•28•0•1•Updated Jul 8, 2026Jul 8, 2026

    • gf180mcu-project-template

      Public template
      All-Digital PLL for GF180MCU using standard cells
      Python
      •
      Apache License 2.0
      •0•3•0•0•Updated May 19, 2026May 19, 2026

    • bsg_fakeram

      Public
      fakeram generator for use by researchers who do not have access to commercial ram generators
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •22•2•0•1•Updated May 15, 2026May 15, 2026

    • sky130_fd_bd_sram

      Public
      Apache License 2.0
      •0•0•0•0•Updated Apr 22, 2026Apr 22, 2026

    • skillz

      Public
      Claude SKILL files for project and research review.
      Makefile
      •
      BSD 3-Clause "New" or "Revised" License
      •0•1•0•0•Updated Apr 21, 2026Apr 21, 2026

    • lithosim

      Public
      This is a very basic lithography simulation and pixel-based OPC tool.
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •12•54•0•0•Updated Mar 19, 2026Mar 19, 2026

    • cocotbext-ams

      Public
      An analog simulator bridge for cocotb — open-source mixed-signal co-simulation
      simulationanalogverilog
      simulationanalogverilogmixed-signal
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •3•11•1•1•Updated Mar 19, 2026Mar 19, 2026

    • asap7_bb_pdk

      Public
      Modified ASAP7 PDK with Buried Power Rail (BPR) and Backside Metal (BSM) technologies.
      HCL
      •
      Other
      •1•0•0•0•Updated Feb 23, 2026Feb 23, 2026

    • vlsida-codespace

      Public
      Shell
      •0•0•0•0•Updated Oct 4, 2025Oct 4, 2025

    • tt25a_openram_testchip

      Public
      Verilog
      •
      Apache License 2.0
      •2•2•0•0•Updated Sep 15, 2025Sep 15, 2025

    • FakeRAM2.0

      Public
      Python
      •19•1•0•0•Updated Aug 7, 2025Aug 7, 2025

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      Python
      •
      Apache License 2.0
      •79•0•0•0•Updated Feb 26, 2025Feb 26, 2025

    • vlsida-openroad

      Public
      Dockerfile
      •0•0•0•0•Updated Nov 21, 2024Nov 21, 2024

    • openram_testchip

      Public
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •368•9•0•1•Updated Aug 7, 2024Aug 7, 2024

    • sky130_sram_macros

      Public
      SourcePawn
      •
      Apache License 2.0
      •17•21•1•0•Updated Jul 12, 2024Jul 12, 2024

    • OpenCache

      Public
      An open-source custom cache generator.
      pythoncache
      pythoncache
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •5•37•1•0•Updated Mar 14, 2024Mar 14, 2024

    • vlsida-eda

      Public
      Conda recipes for VLSIDA projects.
      Shell
      •
      BSD 3-Clause "New" or "Revised" License
      •0•5•0•0•Updated Dec 20, 2023Dec 20, 2023

    • openram_testchip2

      Public
      Verilog
      •
      Apache License 2.0
      •0•3•0•0•Updated Sep 12, 2023Sep 12, 2023

    • OpenLane

      Public
      OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design explor…
      SourcePawn
      •
      Apache License 2.0
      •441•1•0•0•Updated Jun 6, 2023Jun 6, 2023

    • sky130_klayout_pdk

      Public
      Skywater 130nm Klayout Device Generators PDK
      Python
      •
      GNU Affero General Public License v3.0
      •10•1•0•0•Updated Apr 27, 2023Apr 27, 2023

    • sky130-validation

      Public
      Silicon validation projects for SKY130 stuff
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •1•0•0•0•Updated Nov 18, 2022Nov 18, 2022

    • gf180_fd_bd_sram

      Public
      0•1•0•0•Updated Oct 31, 2022Oct 31, 2022

    • klayout

      Public
      klayout tech files
      Ruby
      •1•0•0•0•Updated Aug 3, 2022Aug 3, 2022

    • SKY130_for_KLayout

      Public
      KLayout technology files for Skywater SKY130
      Ruby
      •
      BSD 2-Clause "Simplified" License
      •13•2•0•0•Updated Dec 16, 2021Dec 16, 2021

    • skywater-pdk-libs-sky130_fd_pr_reram

      Public
      SKY130 ReRAM and examples (SkyWater Provided)
      Apache License 2.0
      •11•0•0•0•Updated Dec 6, 2021Dec 6, 2021
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