kernel+x86_64: implement token extraction at page fault time

Author: Qix-

oro-arch-x86_64/src/interrupt/isr_page_fault.rs

@@ -2,11 +2,13 @@
 
 use core::arch::asm;
 use oro_kernel::scheduler::PageFaultType;
+use oro_mem::mapper::AddressSpace;
 use oro_sync::Lock;
+use crate::mem::address_space::AddressSpaceLayout;
 
 crate::isr! {
 	/// The ISR (Interrupt Service Routine) for page fault exceptions.
-	unsafe fn isr_page_fault(kernel, _user_task, err_code) -> Option<Switch> {
+	unsafe fn isr_page_fault(kernel, user_task, err_code) -> Option<Switch> {
 		let cr2: usize;
 		// SAFETY: `cr2` is a register that holds the faulting address. It is safe to read.
 		unsafe {
@@ -31,9 +33,30 @@ crate::isr! {
 			PageFaultType::Read
 		};
 
-		// SAFETY: `event_page_fault` specifies that, in the event we return back to the task,
-		// SAFETY: that the task has been instructed to re-try the memory operation. x86_64
-		// SAFETY: does this by design, so we must do no special handling here.
-		Some(unsafe { kernel.scheduler().lock().event_page_fault(err_type, cr2) })
+		// Try to fetch the page table entry for the faulting address.
+		user_task
+			.as_ref()
+			.and_then(|t| t.with(|task|
+				AddressSpaceLayout::user_data()
+					.try_get_nonpresent_bits(&task.handle().mapper, cr2)
+			))
+			.and_then(|nonpresent_bits| {
+				if nonpresent_bits > 0 {
+					// NOTE(qix-): Page table entries' present bit is bit 0.
+					// NOTE(qix-): We can thus shift the non-present bits to the right
+					// NOTE(qix-): and set the highest bit (63) to 1 to get the token ID.
+					// NOTE(qix-): This follows the guaranteed spec of Tab IDs, which are in turn
+					// NOTE(qix-): token IDs (as specified by the kernel).
+					let token_id = (nonpresent_bits >> 1) | (1 << 63);
+					Some(unsafe { kernel.scheduler().lock().event_page_fault_token(err_type, cr2, token_id) })
+				} else {
+					None
+				}
+			}).or_else(|| {
+				// SAFETY: `event_page_fault` specifies that, in the event we return back to the task,
+				// SAFETY: that the task has been instructed to re-try the memory operation. x86_64
+				// SAFETY: does this by design, so we must do no special handling here.
+				Some(unsafe { kernel.scheduler().lock().event_page_fault(err_type, cr2) })
+			})
 	}
 }

oro-arch-x86_64/src/mem/paging.rs

@@ -117,6 +117,10 @@ impl PageTableEntry {
 	/// Resets the entry to its default state.
 	#[inline]
 	pub fn reset(&mut self) {
+		// NOTE(qix-): It is IMPERATIVE that this is set to 0 and not some other
+		// NOTE(qix-): value, even if it's not marked "present". We use non-present
+		// NOTE(qix-): page table entries as a way to mark lazy-allocated pages, the
+		// NOTE(qix-): unused bits referring to a token ID.
 		self.0 = 0;
 	}
 

oro-arch-x86_64/src/mem/segment.rs

@@ -128,6 +128,45 @@ impl AddressSegment {
 		Ok(entry)
 	}
 
+	/// Attempts to fetch the token data for the given virtual address.
+	///
+	/// If the page table entry is not present, returns the non-present bits
+	/// of the entry. If the entry is present, or if any intermediate page table
+	/// entries are missing, returns `None`.
+	///
+	/// Also returns `None` if the virtual address falls outside of the segment.
+	///
+	/// **Does not allocate** anything for intermediate page tables.
+	pub(crate) fn try_get_nonpresent_bits(
+		&self,
+		space: &AddressSpaceHandle,
+		virt: usize,
+	) -> Option<u64> {
+		// SAFETY: We know that the base physical address is a valid page table.
+		let mut current_page_table = unsafe { space.base_phys().as_ref_unchecked::<PageTable>() };
+
+		for level in (1..space.paging_level().as_usize()).rev() {
+			let index = (virt >> (12 + level * 9)) & 0x1FF;
+			let entry = &current_page_table[index];
+
+			if !entry.present() {
+				return None;
+			}
+
+			// SAFETY: Barring a bug, we know that the physical address is valid.
+			current_page_table =
+				unsafe { Phys::from_address_unchecked(entry.address()).as_ref_unchecked() };
+		}
+
+		let entry = (*current_page_table)[(virt >> 12) & 0x1FF];
+
+		if entry.present() {
+			None
+		} else {
+			Some(entry.into())
+		}
+	}
+
 	/// Attempts to unmap a virtual address from the segment, returning the
 	/// physical address that was previously mapped. Assumes that the CPU
 	/// is in a 4-level paging mode.

oro-kernel/src/scheduler.rs

@@ -273,6 +273,37 @@ impl<A: Arch> Scheduler<A> {
 		self.kernel.handle().schedule_timer(1000);
 		switch
 	}
+
+	/// Indicates to the kernel that a page fault has occurred whereby a reserved
+	/// page table entry token was used.
+	///
+	/// If the token is valid, the kernel will handle issuing mapping requests
+	/// or other asynchronous operations to (eventually) resolve the fault.
+	///
+	/// # Safety
+	/// Calling architectures **must** treat "return back to same task"
+	/// [`Switch`]es as to mean "retry the faulting memory operation". The
+	/// kernel will NOT attempt to recover from fatal or unexpected page faults.
+	///
+	/// **No locks may be held at this boundary.** The architecture **MUST**
+	/// free up any task- or memory-related locks before calling this function.
+	/// The exception, of course, is the scheduler lock itself, which is held
+	/// by the architecture.
+	#[expect(clippy::missing_panics_doc)]
+	#[must_use]
+	pub unsafe fn event_page_fault_token(
+		&mut self,
+		fault_type: PageFaultType,
+		vaddr: usize,
+		token_id: u64,
+	) -> Switch<A> {
+		if let Some(_token) = crate::tab::get().lookup::<crate::token::Token>(token_id) {
+			todo!("handle page fault token: {token_id:#016X}");
+		} else {
+			// Normal page fault; forward it on.
+			self.event_page_fault(fault_type, vaddr)
+		}
+	}
 }
 
 impl<A: Arch> Drop for Scheduler<A> {