Fix typo

Author: pConst

debounce_v1.v

@@ -7,7 +7,7 @@
 // INFO ------------------------------------------------------------------------
 // Button debounce v1
 //
-// - sampling inputs using configurable divided clock (ithis is the
+// - sampling inputs using configurable divided clock (this is the
 //   simplest form of low-pass filter)
 // - switching output only when both samples have equal level
 //   (this gives some form of hysteresis in case we sample unstable data)

debounce_v2.sv

@@ -7,7 +7,7 @@
 // INFO ------------------------------------------------------------------------
 // Button debounce v2, SystemVerilog version
 //
-// - sampling inputs using configurable divided clock (ithis is the
+// - sampling inputs using configurable divided clock (this is the
 //   simplest form of low-pass filter)
 //
 // - in contrast with debounce_v1.v this implementation is switching output only

debounce_v2.v

@@ -7,7 +7,7 @@
 // INFO ------------------------------------------------------------------------
 // Button debounce v2
 //
-// - sampling inputs using configurable divided clock (ithis is the
+// - sampling inputs using configurable divided clock (this is the
 //   simplest form of low-pass filter)
 //
 // - in contrast with debounce_v1.v this implementation is switching output only