Skip to content

Commit 66733fa

Browse files
committed
Added benchmark_projects dir README
1 parent f6a5726 commit 66733fa

File tree

1 file changed

+22
-0
lines changed

1 file changed

+22
-0
lines changed

benchmark_projects/README.md

+22
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
readme for "benchmark_projects" directory
2+
published as part of https://github.com/pConst/basic_verilog
3+
Konstantin Pavlov, [email protected]
4+
5+
6+
The directory contains single reference System Verilog codebase, compiled consistently for multiple FPGA platforms and vendors.
7+
8+
Supported and committed IDE projects include
9+
* Xilinx ISE
10+
* Xilinx Vivado
11+
* Intel Quartus
12+
* Gowin IDE
13+
14+
Currently working on
15+
* Microsemi Libero
16+
* Lattice iCEcube
17+
* Lattice FOSS toolchain
18+
19+
See comparative compile time results in ./benchmark_results.txt
20+
21+
22+

0 commit comments

Comments
 (0)