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1 | | -The RISC-V implementation is by Zhengyang Gu |
| 1 | +# RISC-V floating-point support for Sunflower |
| 2 | +Author: Ryan Jay Leong Voo (based on original RISC-V implementation from Zhengyang Gu) |
2 | 3 |
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3 | | -The following changes are made in each commit from the incoming pull request to merge into phillipstanleymarbell/sunflower-simulator: |
4 | | -* Modify makefiles and setup.conf for riscv-toolchain 147f500 |
5 | | - * Upgrade gcc and binutils to versions that support RISV-V |
6 | | - * Change the directory of gcc from $(TOOLS)/bin to $(TOOLS)/riscv/bin to avoid gcc errors where cc1 cannot be found |
7 | | - * A few other changes in compilation options to make the compilation work on my laptop |
8 | | -* Make cache access little endian 0923d28 |
9 | | - * Inverse the order of bytes in superH(read|write)(word|long) to make memory access little endian |
10 | | -* Add riscv support to sunflower f68f15f |
11 | | - * sim/devsunflower.c |
12 | | - * Create RISC-V node (using riscvnewstate) instead of SuperH node by default |
13 | | - * sim/main.c |
14 | | - * Create RISC-V node (using riscvnewstate) instead of SuperH node by default |
15 | | - * Initialize the RISC-V node and set x2 (register 2, stack pointer by convension) accordingly. |
16 | | - * Remove decode cache generation. RISC-V uses 64 bits instructions, it is not possible to store the decode result of all 2^64 inputs |
17 | | - * sim/main.h |
18 | | - * Add RISC-V state to State type. |
19 | | - * Specify PC to be uint32\_t |
20 | | - * sim/machine-riscv.[ch] |
21 | | - * Define the type RiscvState to store the register readings and decoded instruction in pipeline |
22 | | - * Define riscvnewstate function to initialize the RISC-V node |
23 | | - * We call superHnewstate to initialize memory, as we use functions from superH for memory access |
24 | | - * Set the step funtion in global state to be riscvstep |
25 | | - * Set the dumpregs function in global state to be riscvdumpregs |
26 | | - * Define riscvdumpregs |
27 | | - * sim/instr-riscv.h |
28 | | - * Define the bit fields of different RISC-V instruction types |
29 | | - * Define a universal struct for decoding, which marks all opcode and funct fields |
30 | | - * sim/decode-riscv.c |
31 | | - * Define a function to decode RISC-V instructions |
32 | | - * sim/op-riscv.c |
33 | | - * Defien one funtions for each RV32I instruction that emulates its effect on RiscvState |
34 | | - * sim/regaccess-riscv.[ch] |
35 | | - * Functions to read/write from general purpose registers |
36 | | - * Enumerators for RISC-V register names |
37 | | - * sim/pipeline-riscv.[ch] |
38 | | - * Define the pipeline stage struct to store the instruction, decoded instruction type and the corresponding function from op-riscv.c |
39 | | -* Add bubble sort test for riscv 7519e1c |
40 | | - * Add a test bubblesort program to benchmarks |
41 | | - * Add corresponding Makefile and run.m |
42 | | -* Add dumppipe support for RISC-V f4d8b5e |
43 | | - * sim/decode-riscv.[ch] |
44 | | - * Add enumerator for each RISC-V instruction |
45 | | - * Store an enumerator reference to the decoded instruction in the pipeline |
46 | | - * sim/pipeline-riscv.c |
47 | | - * Define riscvdumppipe to print out the pipeline content |
48 | | - * Set dumppipe in universal state to riscvdumppipe |
49 | | - * Update riscvstep funtion to support showpipe |
50 | | - * sim/mkopstr-riscv |
51 | | - * Shell script to generate a mapping from instruction enumerator to string for printing |
52 | | - * sim/Makefile |
53 | | - * Call mkopstr-riscv at compile time |
| 4 | +## To build and run |
| 5 | +In sunflower-toolchain, make sure to set OSTYPE and MACHTYPE appropriately. TARGET should be set to **riscv** and TARGET-ARCH should be set to **riscv32-elf**. Make sure ADDITIONAL_ARCH_FLAGS is uncommented and set to **--with-arch=rv32ifd**. Continue following the instructions in README.md at the root of the repository. |
| 6 | + |
| 7 | +After building Sunflower, go to `sunflower-simulator/benchmarks/source/riscv_newton-raphson` and run `make`. To load the program into sunflower, run `../../../sim/sf run.m`. |
| 8 | + |
| 9 | +## Files Modified |
| 10 | +Files from the RV32I base integer implementation were modified to integrate the RV32FD architecture. Changes include the following. |
| 11 | + |
| 12 | +For RV32F support: |
| 13 | +1. cache-hitachi-sh.c: Fixed endian problem in memory access. |
| 14 | +2. decode-riscv.h: Added new constants for instructions. |
| 15 | +3. decode-riscv.c: In riscvdecode function, added new switch cases for decoding. |
| 16 | +4. op-riscv.c: Added functions to emulate instruction operations. |
| 17 | +5. machine-riscv.h: Added floating-point registers, added 1 FCSR. |
| 18 | +6. regs-riscv.h: Added enum for floating-point registers, added union type for float and uint32_t. |
| 19 | +7. instr-riscv.h: Include new R4 type. |
| 20 | +8. regaccess-riscv.c: Included new functions to read floating point registers. |
| 21 | +9. mkopstr-riscv: Updated rule to create opstr-riscv.h. |
| 22 | +10. pipeline-riscv.c: Add new support for R4 type instructions. |
| 23 | +11. mfns.h: added function prototypes. |
| 24 | + |
| 25 | +For RV32D support: |
| 26 | +1. regs-riscv.h: Modified union type for fp registers |
| 27 | +2. machine-riscv.h: Widened floating point registers |
| 28 | +3. decode-riscv.h: New constants for instructions |
| 29 | +4. decode-riscv.c: Added new switch cases for decoding. |
| 30 | +5. regaccess-riscv.c: Added new typedef union for read/write to uint64_t, changed freg read write to uint64_t |
| 31 | +6. op-riscv.c: Added new rv32D instructions |
| 32 | +7. mkopstr-riscv: updated to create opstr-riscv.h |
| 33 | +8. mfns.h: Added function prototypes |
| 34 | + |
| 35 | +Test file: |
| 36 | + |
| 37 | +Also added a test file called `riscv_newton-raphson` in `benchmarks/source/`. |
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