From f19ff5d07ee6935cf772faa6c06c812e0fd67402 Mon Sep 17 00:00:00 2001 From: Max Wipfli Date: Fri, 20 Jun 2025 17:46:20 +0200 Subject: [PATCH 1/2] cva6_tlb_sv39x4: Replace (2 ** X) with (1 << X) for Verilator Verilator does not include a special case for (2 ** X), making this very slow. This change increases simulation speed with Verilator by around 2 percent for the entire Cheshire SoC. --- core/mmu_sv39x4/cva6_tlb_sv39x4.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/core/mmu_sv39x4/cva6_tlb_sv39x4.sv b/core/mmu_sv39x4/cva6_tlb_sv39x4.sv index f9cf01cb18..8cf7c8a48a 100644 --- a/core/mmu_sv39x4/cva6_tlb_sv39x4.sv +++ b/core/mmu_sv39x4/cva6_tlb_sv39x4.sv @@ -91,7 +91,7 @@ module cva6_tlb_sv39x4 //------------- always_comb begin : translation automatic logic [riscv::GPPN2:0] mask_pn2; - mask_pn2 = s_st_enbl_i ? ((2 ** (riscv::VPN2 + 1)) - 1) : ((2 ** (riscv::GPPN2 + 1)) - 1); + mask_pn2 = s_st_enbl_i ? ((1 << (riscv::VPN2 + 1)) - 1) : ((1 << (riscv::GPPN2 + 1)) - 1); vpn0 = lu_vaddr_i[20:12]; vpn1 = lu_vaddr_i[29:21]; vpn2 = lu_vaddr_i[30+riscv::GPPN2:30] & mask_pn2; @@ -312,7 +312,7 @@ module cva6_tlb_sv39x4 if (lu_hit[i] & lu_access_i) begin // Set the nodes to the values we would expect for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin - idx_base = $unsigned((2 ** lvl) - 1); + idx_base = $unsigned((1 << lvl) - 1); // lvl0 <=> MSB, lvl1 <=> MSB-1, ... shift = $clog2(TLB_ENTRIES) - lvl; // to circumvent the 32 bit integer arithmetic assignment @@ -340,7 +340,7 @@ module cva6_tlb_sv39x4 automatic int unsigned idx_base, shift, new_index; en = 1'b1; for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin - idx_base = $unsigned((2 ** lvl) - 1); + idx_base = $unsigned((1 << lvl) - 1); // lvl0 <=> MSB, lvl1 <=> MSB-1, ... shift = $clog2(TLB_ENTRIES) - lvl; From 2565f6dad38bb5630beac3d0043d9742c55d1ce2 Mon Sep 17 00:00:00 2001 From: Max Wipfli Date: Thu, 10 Jul 2025 10:18:35 +0200 Subject: [PATCH 2/2] Add `ifndef to allow disabling instruction tracer --- core/cva6.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/core/cva6.sv b/core/cva6.sv index 42285e1b02..770707cb91 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1442,6 +1442,7 @@ module cva6 ); `endif // PITON_ARIANE +`ifndef CVA6_NO_TRACE `ifndef VERILATOR instr_tracer_if tracer_if (clk_i); // assign instruction tracer interface @@ -1540,6 +1541,7 @@ module cva6 $fclose(f); end `endif // VERILATOR +`endif // CVA6_NO_TRACE //pragma translate_on