diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml index cdee362..4381672 100644 --- a/.github/workflows/gitlab-ci.yml +++ b/.github/workflows/gitlab-ci.yml @@ -18,7 +18,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Check Gitlab CI - uses: pulp-platform/pulp-actions/gitlab-ci@v2 + uses: pulp-platform/pulp-actions/gitlab-ci@v2.4.1 if: > github.repository == 'pulp-platform/memory_island' && (github.event_name != 'pull_request' || diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index df2a7dd..9d11c02 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -27,3 +27,32 @@ jobs: extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal" github_token: ${{ secrets.GITHUB_TOKEN }} reviewdog_reporter: github-check + + lint-sv-format: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + ref: ${{ github.event.pull_request.head.sha }} + - name: Install Bender + uses: pulp-platform/pulp-actions/bender-install@v2 + with: + version: 0.28.2 + - name: Get files + run: | + bender_files=$(bender script flist -n -t test -t memory_island_standalone_synth) + bender_files=$(echo $bender_files | tr '\n' ' ') + echo $bender_files + echo "BENDER_FILES=$bender_files" >> $GITHUB_ENV + - name: Print fix + run: | + echo "Fix with \`make format\`" + - name: Run Verible formatter action + uses: chipsalliance/verible-formatter-action@main + with: + github_token: ${{ secrets.GITHUB_TOKEN }} + files: + $BENDER_FILES + parameters: + --flagfile .verilog_format + fail_on_formatting_suggestions: true diff --git a/.verilog_format b/.verilog_format new file mode 100644 index 0000000..444c19d --- /dev/null +++ b/.verilog_format @@ -0,0 +1,26 @@ +--column_limit=100 +--indentation_spaces=2 +--line_break_penalty=2 +--over_column_limit_penalty=10000 +--wrap_spaces=4 +--assignment_statement_alignment=align +--case_items_alignment=align +--class_member_variable_alignment=align +--distribution_items_alignment=align +--enum_assignment_statement_alignment=align +--formal_parameters_alignment=align +--formal_parameters_indentation=indent +--module_net_variable_alignment=align +--named_parameter_alignment=align +--named_parameter_indentation=indent +--named_port_alignment=align +--named_port_indentation=indent +--port_declarations_alignment=align +--port_declarations_indentation=indent +--struct_union_members_alignment=align +--try_wrap_long_lines=false +--wrap_end_else_clauses=false +--port_declarations_right_align_packed_dimensions=false +--port_declarations_right_align_unpacked_dimensions=false +--expand_coverpoints=false +--compact_indexing_and_selections=true diff --git a/Bender.lock b/Bender.lock index 25bc5a0..d5cf9de 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,7 +1,7 @@ packages: axi: - revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7 - version: 0.39.4 + revision: f07498d53ecd5518b277c7d213ec3b71ca4df93c + version: 0.39.7 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -9,23 +9,23 @@ packages: - common_verification - tech_cells_generic cluster_interconnect: - revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27 - version: 1.2.1 + revision: 2967d8d17be0a6139229ca8d3d4956e182aec3de + version: 1.3.0 source: Git: https://github.com/pulp-platform/cluster_interconnect.git dependencies: - common_cells common_cells: - revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb - version: 1.37.0 + revision: 9afda9abb565971649c2aa0985639c096f351171 + version: 1.38.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: - common_verification - tech_cells_generic common_verification: - revision: 9c07fa860593b2caabd9b5681740c25fac04b878 - version: 0.2.3 + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] diff --git a/Makefile b/Makefile index c248a01..f0eaeca 100644 --- a/Makefile +++ b/Makefile @@ -32,3 +32,9 @@ nonfree-init: cd nonfree && git checkout $(NONFREE_COMMIT) -include $(MEMORY_ISLAND_ROOT)/nonfree/nonfree.mk + +BENDER_FILES := $(shell $(BENDER) script flist -n -t test -t memory_island_standalone_synth) + +.PHONY: format +format: + verible-verilog-format $(BENDER_FILES) --inplace --flagfile .verilog_format diff --git a/src/axi_memory_island_wrap.sv b/src/axi_memory_island_wrap.sv index 2f59461..97bd5a1 100644 --- a/src/axi_memory_island_wrap.sv +++ b/src/axi_memory_island_wrap.sv @@ -6,30 +6,30 @@ module axi_memory_island_wrap #( /// Address Width - parameter int unsigned AddrWidth = 0, + parameter int unsigned AddrWidth = 0, /// Data Width for the Narrow Ports - parameter int unsigned NarrowDataWidth = 0, + parameter int unsigned NarrowDataWidth = 0, /// Data Width for the Wide Ports - parameter int unsigned WideDataWidth = 0, + parameter int unsigned WideDataWidth = 0, - parameter int unsigned AxiNarrowIdWidth = 0, - parameter int unsigned AxiWideIdWidth = 0, + parameter int unsigned AxiNarrowIdWidth = 0, + parameter int unsigned AxiWideIdWidth = 0, - parameter type axi_narrow_req_t = logic, - parameter type axi_narrow_rsp_t = logic, + parameter type axi_narrow_req_t = logic, + parameter type axi_narrow_rsp_t = logic, - parameter type axi_wide_req_t = logic, - parameter type axi_wide_rsp_t = logic, + parameter type axi_wide_req_t = logic, + parameter type axi_wide_rsp_t = logic, /// Number of Narrow Ports - parameter int unsigned NumNarrowReq = 0, + parameter int unsigned NumNarrowReq = 0, /// Number of Wide Ports - parameter int unsigned NumWideReq = 0, + parameter int unsigned NumWideReq = 0, /// Indicates corresponding narrow requestor supports read/write (0 for read-only/write-only) - parameter bit [NumNarrowReq-1:0] NarrowRW = '1, + parameter bit [NumNarrowReq-1:0] NarrowRW = '1, /// Indicates corresponding narrow requestor supports read/write (0 for read-only/write-only) - parameter bit [NumWideReq-1:0] WideRW = '1, + parameter bit [ NumWideReq-1:0] WideRW = '1, /// Spill Narrow parameter int unsigned SpillNarrowReqEntry = 0, @@ -48,32 +48,32 @@ module axi_memory_island_wrap #( parameter int unsigned SpillRspBank = 0, /// Relinquish narrow priority after x cycles, 0 for never. Requires SpillNarrowReqRouted==0. - parameter int unsigned WidePriorityWait = 1, + parameter int unsigned WidePriorityWait = 1, /// Banking Factor for the Wide Ports (power of 2) - parameter int unsigned NumWideBanks = (1<<$clog2(NumWideReq))*2*2, + parameter int unsigned NumWideBanks = (1 << $clog2(NumWideReq)) * 2 * 2, /// Extra multiplier for the Narrow banking factor (baseline is WideWidth/NarrowWidth) (power of 2) - parameter int unsigned NarrowExtraBF = 1, + parameter int unsigned NarrowExtraBF = 1, /// Words per memory bank. (Total number of banks is (WideWidth/NarrowWidth)*NumWideBanks) - parameter int unsigned WordsPerBank = 1024, + parameter int unsigned WordsPerBank = 1024, // verilog_lint: waive explicit-parameter-storage-type - parameter MemorySimInit = "none" + parameter MemorySimInit = "none" ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, input axi_narrow_req_t [NumNarrowReq-1:0] axi_narrow_req_i, output axi_narrow_rsp_t [NumNarrowReq-1:0] axi_narrow_rsp_o, - input axi_wide_req_t [ NumWideReq-1:0] axi_wide_req_i, - output axi_wide_rsp_t [ NumWideReq-1:0] axi_wide_rsp_o + input axi_wide_req_t [NumWideReq-1:0] axi_wide_req_i, + output axi_wide_rsp_t [NumWideReq-1:0] axi_wide_rsp_o ); - localparam int unsigned NarrowStrbWidth = NarrowDataWidth/8; - localparam int unsigned WideStrbWidth = WideDataWidth/8; + localparam int unsigned NarrowStrbWidth = NarrowDataWidth / 8; + localparam int unsigned WideStrbWidth = WideDataWidth / 8; localparam int unsigned InternalNumNarrow = NumNarrowReq + $countones(NarrowRW); - localparam int unsigned InternalNumWide = NumWideReq + $countones(WideRW); + localparam int unsigned InternalNumWide = NumWideReq + $countones(WideRW); localparam int unsigned NarrowMemRspLatency = SpillNarrowReqEntry + SpillNarrowReqRouted + @@ -115,58 +115,58 @@ module axi_memory_island_wrap #( localparam int unsigned Id = i + $countones(NarrowRW[i:0]); if (NarrowRW[i]) begin : gen_split_conv axi_to_mem_split #( - .axi_req_t ( axi_narrow_req_t ), - .axi_resp_t ( axi_narrow_rsp_t ), - .AddrWidth ( AddrWidth ), - .AxiDataWidth ( NarrowDataWidth ), - .IdWidth ( AxiNarrowIdWidth ), - .MemDataWidth ( NarrowDataWidth ), - .BufDepth ( 1 + NarrowMemRspLatency ), - .HideStrb ( 1'b0 ), - .OutFifoDepth ( 1 ) + .axi_req_t (axi_narrow_req_t), + .axi_resp_t (axi_narrow_rsp_t), + .AddrWidth (AddrWidth), + .AxiDataWidth(NarrowDataWidth), + .IdWidth (AxiNarrowIdWidth), + .MemDataWidth(NarrowDataWidth), + .BufDepth (1 + NarrowMemRspLatency), + .HideStrb (1'b0), + .OutFifoDepth(1) ) i_narrow_conv ( .clk_i, .rst_ni, - .test_i ( '0 ), - .busy_o (), - .axi_req_i ( axi_narrow_req_i[i ] ), - .axi_resp_o ( axi_narrow_rsp_o[i ] ), - .mem_req_o ( narrow_req [Id-:2] ), - .mem_gnt_i ( narrow_gnt [Id-:2] ), - .mem_addr_o ( narrow_addr [Id-:2] ), - .mem_wdata_o ( narrow_wdata [Id-:2] ), - .mem_strb_o ( narrow_strb [Id-:2] ), - .mem_atop_o (), - .mem_we_o ( narrow_we [Id-:2] ), - .mem_rvalid_i ( narrow_rvalid [Id-:2] ), - .mem_rdata_i ( narrow_rdata [Id-:2] ) + .test_i ('0), + .busy_o (), + .axi_req_i (axi_narrow_req_i[i]), + .axi_resp_o (axi_narrow_rsp_o[i]), + .mem_req_o (narrow_req[Id-:2]), + .mem_gnt_i (narrow_gnt[Id-:2]), + .mem_addr_o (narrow_addr[Id-:2]), + .mem_wdata_o (narrow_wdata[Id-:2]), + .mem_strb_o (narrow_strb[Id-:2]), + .mem_atop_o (), + .mem_we_o (narrow_we[Id-:2]), + .mem_rvalid_i(narrow_rvalid[Id-:2]), + .mem_rdata_i (narrow_rdata[Id-:2]) ); end else begin : gen_single_conv axi_to_mem #( - .axi_req_t ( axi_narrow_req_t ), - .axi_resp_t ( axi_narrow_rsp_t ), - .AddrWidth ( AddrWidth ), - .DataWidth ( NarrowDataWidth ), - .IdWidth ( AxiNarrowIdWidth ), - .NumBanks ( 1 ), - .BufDepth ( 1 + NarrowMemRspLatency ), - .HideStrb ( 1'b0 ), - .OutFifoDepth ( 1 ) + .axi_req_t (axi_narrow_req_t), + .axi_resp_t (axi_narrow_rsp_t), + .AddrWidth (AddrWidth), + .DataWidth (NarrowDataWidth), + .IdWidth (AxiNarrowIdWidth), + .NumBanks (1), + .BufDepth (1 + NarrowMemRspLatency), + .HideStrb (1'b0), + .OutFifoDepth(1) ) i_narrow_conv ( .clk_i, .rst_ni, - .busy_o (), - .axi_req_i ( axi_narrow_req_i[i ] ), - .axi_resp_o ( axi_narrow_rsp_o[i ] ), - .mem_req_o ( narrow_req [Id] ), - .mem_gnt_i ( narrow_gnt [Id] ), - .mem_addr_o ( narrow_addr [Id] ), - .mem_wdata_o ( narrow_wdata [Id] ), - .mem_strb_o ( narrow_strb [Id] ), - .mem_atop_o (), - .mem_we_o ( narrow_we [Id] ), - .mem_rvalid_i ( narrow_rvalid [Id] ), - .mem_rdata_i ( narrow_rdata [Id] ) + .busy_o (), + .axi_req_i (axi_narrow_req_i[i]), + .axi_resp_o (axi_narrow_rsp_o[i]), + .mem_req_o (narrow_req[Id]), + .mem_gnt_i (narrow_gnt[Id]), + .mem_addr_o (narrow_addr[Id]), + .mem_wdata_o (narrow_wdata[Id]), + .mem_strb_o (narrow_strb[Id]), + .mem_atop_o (), + .mem_we_o (narrow_we[Id]), + .mem_rvalid_i(narrow_rvalid[Id]), + .mem_rdata_i (narrow_rdata[Id]) ); end end @@ -175,106 +175,106 @@ module axi_memory_island_wrap #( localparam int unsigned Id = i + $countones(WideRW[i:0]); if (WideRW[i]) begin : gen_split_conv axi_to_mem_split #( - .axi_req_t ( axi_wide_req_t ), - .axi_resp_t ( axi_wide_rsp_t ), - .AddrWidth ( AddrWidth ), - .AxiDataWidth ( WideDataWidth ), - .IdWidth ( AxiWideIdWidth ), - .MemDataWidth ( WideDataWidth ), - .BufDepth ( 1 + WideMemRspLatency ), - .HideStrb ( 1'b0 ), - .OutFifoDepth ( 1 ) + .axi_req_t (axi_wide_req_t), + .axi_resp_t (axi_wide_rsp_t), + .AddrWidth (AddrWidth), + .AxiDataWidth(WideDataWidth), + .IdWidth (AxiWideIdWidth), + .MemDataWidth(WideDataWidth), + .BufDepth (1 + WideMemRspLatency), + .HideStrb (1'b0), + .OutFifoDepth(1) ) i_wide_conv ( .clk_i, .rst_ni, - .test_i ( '0 ), - .busy_o (), - .axi_req_i ( axi_wide_req_i[i ] ), - .axi_resp_o ( axi_wide_rsp_o[i ] ), - .mem_req_o ( wide_req [Id-:2] ), - .mem_gnt_i ( wide_gnt [Id-:2] ), - .mem_addr_o ( wide_addr [Id-:2] ), - .mem_wdata_o ( wide_wdata [Id-:2] ), - .mem_strb_o ( wide_strb [Id-:2] ), - .mem_atop_o (), - .mem_we_o ( wide_we [Id-:2] ), - .mem_rvalid_i ( wide_rvalid [Id-:2] ), - .mem_rdata_i ( wide_rdata [Id-:2] ) + .test_i ('0), + .busy_o (), + .axi_req_i (axi_wide_req_i[i]), + .axi_resp_o (axi_wide_rsp_o[i]), + .mem_req_o (wide_req[Id-:2]), + .mem_gnt_i (wide_gnt[Id-:2]), + .mem_addr_o (wide_addr[Id-:2]), + .mem_wdata_o (wide_wdata[Id-:2]), + .mem_strb_o (wide_strb[Id-:2]), + .mem_atop_o (), + .mem_we_o (wide_we[Id-:2]), + .mem_rvalid_i(wide_rvalid[Id-:2]), + .mem_rdata_i (wide_rdata[Id-:2]) ); end else begin : gen_single_conv axi_to_mem #( - .axi_req_t ( axi_wide_req_t ), - .axi_resp_t ( axi_wide_rsp_t ), - .AddrWidth ( AddrWidth ), - .AxiDataWidth ( WideDataWidth ), - .IdWidth ( AxiWideIdWidth ), - .NumBanks ( 1 ), - .BufDepth ( 1 + WideMemRspLatency ), - .HideStrb ( 1'b0 ), - .OutFifoDepth ( 1 ) + .axi_req_t (axi_wide_req_t), + .axi_resp_t (axi_wide_rsp_t), + .AddrWidth (AddrWidth), + .AxiDataWidth(WideDataWidth), + .IdWidth (AxiWideIdWidth), + .NumBanks (1), + .BufDepth (1 + WideMemRspLatency), + .HideStrb (1'b0), + .OutFifoDepth(1) ) i_wide_conv ( .clk_i, .rst_ni, - .busy_o (), - .axi_req_i ( axi_wide_req_i[i ] ), - .axi_resp_o ( axi_wide_rsp_o[i ] ), - .mem_req_o ( wide_req [Id] ), - .mem_gnt_i ( wide_gnt [Id] ), - .mem_addr_o ( wide_addr [Id] ), - .mem_wdata_o ( wide_wdata [Id] ), - .mem_strb_o ( wide_strb [Id] ), - .mem_atop_o (), - .mem_we_o ( wide_we [Id] ), - .mem_rvalid_i ( wide_rvalid [Id] ), - .mem_rdata_i ( wide_rdata [Id] ) + .busy_o (), + .axi_req_i (axi_wide_req_i[i]), + .axi_resp_o (axi_wide_rsp_o[i]), + .mem_req_o (wide_req[Id]), + .mem_gnt_i (wide_gnt[Id]), + .mem_addr_o (wide_addr[Id]), + .mem_wdata_o (wide_wdata[Id]), + .mem_strb_o (wide_strb[Id]), + .mem_atop_o (), + .mem_we_o (wide_we[Id]), + .mem_rvalid_i(wide_rvalid[Id]), + .mem_rdata_i (wide_rdata[Id]) ); end end memory_island_core #( - .AddrWidth ( AddrWidth ), - .NarrowDataWidth ( NarrowDataWidth ), - .WideDataWidth ( WideDataWidth ), - .NumNarrowReq ( 2*NumNarrowReq ), - .NumWideReq ( 2*NumWideReq ), - .NumWideBanks ( NumWideBanks ), - .NarrowExtraBF ( NarrowExtraBF ), - .WordsPerBank ( WordsPerBank ), - .SpillNarrowReqEntry ( SpillNarrowReqEntry ), - .SpillNarrowRspEntry ( SpillNarrowRspEntry ), - .SpillNarrowReqRouted ( SpillNarrowReqRouted ), - .SpillNarrowRspRouted ( SpillNarrowRspRouted ), - .SpillWideReqEntry ( SpillWideReqEntry ), - .SpillWideRspEntry ( SpillWideRspEntry ), - .SpillWideReqRouted ( SpillWideReqRouted ), - .SpillWideRspRouted ( SpillWideRspRouted ), - .SpillWideReqSplit ( SpillWideReqSplit ), - .SpillWideRspSplit ( SpillWideRspSplit ), - .SpillReqBank ( SpillReqBank ), - .SpillRspBank ( SpillRspBank ), - .WidePriorityWait ( WidePriorityWait ), - .MemorySimInit ( MemorySimInit ) + .AddrWidth (AddrWidth), + .NarrowDataWidth (NarrowDataWidth), + .WideDataWidth (WideDataWidth), + .NumNarrowReq (2 * NumNarrowReq), + .NumWideReq (2 * NumWideReq), + .NumWideBanks (NumWideBanks), + .NarrowExtraBF (NarrowExtraBF), + .WordsPerBank (WordsPerBank), + .SpillNarrowReqEntry (SpillNarrowReqEntry), + .SpillNarrowRspEntry (SpillNarrowRspEntry), + .SpillNarrowReqRouted(SpillNarrowReqRouted), + .SpillNarrowRspRouted(SpillNarrowRspRouted), + .SpillWideReqEntry (SpillWideReqEntry), + .SpillWideRspEntry (SpillWideRspEntry), + .SpillWideReqRouted (SpillWideReqRouted), + .SpillWideRspRouted (SpillWideRspRouted), + .SpillWideReqSplit (SpillWideReqSplit), + .SpillWideRspSplit (SpillWideRspSplit), + .SpillReqBank (SpillReqBank), + .SpillRspBank (SpillRspBank), + .WidePriorityWait (WidePriorityWait), + .MemorySimInit (MemorySimInit) ) i_memory_island ( .clk_i, .rst_ni, - .narrow_req_i ( narrow_req ), - .narrow_gnt_o ( narrow_gnt ), - .narrow_addr_i ( narrow_addr ), - .narrow_we_i ( narrow_we ), - .narrow_wdata_i ( narrow_wdata ), - .narrow_strb_i ( narrow_strb ), - .narrow_rvalid_o ( narrow_rvalid ), - .narrow_rdata_o ( narrow_rdata ), - .wide_req_i ( wide_req ), - .wide_gnt_o ( wide_gnt ), - .wide_addr_i ( wide_addr ), - .wide_we_i ( wide_we ), - .wide_wdata_i ( wide_wdata ), - .wide_strb_i ( wide_strb ), - .wide_rvalid_o ( wide_rvalid ), - .wide_rdata_o ( wide_rdata ) + .narrow_req_i (narrow_req), + .narrow_gnt_o (narrow_gnt), + .narrow_addr_i (narrow_addr), + .narrow_we_i (narrow_we), + .narrow_wdata_i (narrow_wdata), + .narrow_strb_i (narrow_strb), + .narrow_rvalid_o(narrow_rvalid), + .narrow_rdata_o (narrow_rdata), + .wide_req_i (wide_req), + .wide_gnt_o (wide_gnt), + .wide_addr_i (wide_addr), + .wide_we_i (wide_we), + .wide_wdata_i (wide_wdata), + .wide_strb_i (wide_strb), + .wide_rvalid_o (wide_rvalid), + .wide_rdata_o (wide_rdata) ); endmodule diff --git a/src/mem_req_multicut.sv b/src/mem_req_multicut.sv index 8b2beb5..e2f3d1f 100644 --- a/src/mem_req_multicut.sv +++ b/src/mem_req_multicut.sv @@ -12,10 +12,10 @@ module mem_req_multicut #( /// Number of cuts parameter int unsigned NumCuts = 0, // Derived, DO NOT OVERRIDE - parameter int unsigned StrbWidth = DataWidth/8 + parameter int unsigned StrbWidth = DataWidth / 8 ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // mem interface inputs input logic req_i, @@ -34,38 +34,38 @@ module mem_req_multicut #( output logic [StrbWidth-1:0] strb_o ); - localparam int unsigned AggDataWidth = 1+StrbWidth+AddrWidth+DataWidth; + localparam int unsigned AggDataWidth = 1 + StrbWidth + AddrWidth + DataWidth; if (NumCuts == 0) begin : gen_passthrough - assign req_o = req_i; - assign gnt_o = gnt_i; - assign addr_o = addr_i; - assign we_o = we_i; - assign wdata_o = wdata_i; - assign strb_o = strb_i; + assign req_o = req_i; + assign gnt_o = gnt_i; + assign addr_o = addr_i; + assign we_o = we_i; + assign wdata_o = wdata_i; + assign strb_o = strb_i; end else begin : gen_cuts - logic [NumCuts:0][AggDataWidth-1:0] data_agg; + logic [NumCuts:0][AggDataWidth-1:0] data_agg; logic [NumCuts:0] req, gnt; - assign data_agg[0] = {we_i, strb_i, addr_i, wdata_i}; - assign req [0] = req_i; - assign gnt_o = gnt[0]; - assign gnt[NumCuts] = gnt_i; - assign req_o = req [NumCuts]; + assign data_agg[0] = {we_i, strb_i, addr_i, wdata_i}; + assign req[0] = req_i; + assign gnt_o = gnt[0]; + assign gnt[NumCuts] = gnt_i; + assign req_o = req[NumCuts]; assign {we_o, strb_o, addr_o, wdata_o} = data_agg[NumCuts]; for (genvar i = 0; i < NumCuts; i++) begin : gen_cut spill_register #( - .T (logic[AggDataWidth-1:0]), + .T (logic [AggDataWidth-1:0]), .Bypass(1'b0) ) i_cut ( .clk_i, .rst_ni, - .valid_i ( req [i ] ), - .ready_o ( gnt [i ] ), - .data_i ( data_agg[i ] ), - .valid_o ( req [i+1] ), - .ready_i ( gnt [i+1] ), - .data_o ( data_agg[i+1] ) + .valid_i(req[i]), + .ready_o(gnt[i]), + .data_i (data_agg[i]), + .valid_o(req[i+1]), + .ready_i(gnt[i+1]), + .data_o (data_agg[i+1]) ); end end diff --git a/src/mem_rsp_multicut.sv b/src/mem_rsp_multicut.sv index 2e2f23b..988e241 100644 --- a/src/mem_rsp_multicut.sv +++ b/src/mem_rsp_multicut.sv @@ -10,8 +10,8 @@ module mem_rsp_multicut #( /// Number of cuts parameter int unsigned NumCuts = 0 ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // mem interface inputs input logic rvalid_i, @@ -29,29 +29,29 @@ module mem_rsp_multicut #( assign rready_o = rready_i; assign rdata_o = rdata_i; end else begin : gen_cuts - logic [NumCuts:0][DataWidth-1:0] data_agg; + logic [NumCuts:0][DataWidth-1:0] data_agg; logic [NumCuts:0] rvalid, rready; - assign data_agg [0] = rdata_i; - assign rvalid [0] = rvalid_i; + assign data_agg[0] = rdata_i; + assign rvalid[0] = rvalid_i; assign rready_o = rready[0]; assign rready[NumCuts] = rready_i; - assign rvalid_o = rvalid [NumCuts]; - assign rdata_o = data_agg [NumCuts]; + assign rvalid_o = rvalid[NumCuts]; + assign rdata_o = data_agg[NumCuts]; for (genvar i = 0; i < NumCuts; i++) begin : gen_cut spill_register #( - .T (logic[DataWidth-1:0]), + .T (logic [DataWidth-1:0]), .Bypass(1'b0) ) i_cut ( .clk_i, .rst_ni, - .valid_i ( rvalid [i ] ), - .ready_o ( rready [i ] ), - .data_i ( data_agg[i ] ), - .valid_o ( rvalid [i+1] ), - .ready_i ( rready [i+1] ), - .data_o ( data_agg[i+1] ) + .valid_i(rvalid[i]), + .ready_o(rready[i]), + .data_i (data_agg[i]), + .valid_o(rvalid[i+1]), + .ready_i(rready[i+1]), + .data_o (data_agg[i+1]) ); end end diff --git a/src/memory_island_core.sv b/src/memory_island_core.sv index 6c4907d..756463a 100644 --- a/src/memory_island_core.sv +++ b/src/memory_island_core.sv @@ -6,23 +6,23 @@ module memory_island_core #( /// Address Width - parameter int unsigned AddrWidth = 0, + parameter int unsigned AddrWidth = 0, /// Data Width for the Narrow Ports - parameter int unsigned NarrowDataWidth = 0, + parameter int unsigned NarrowDataWidth = 0, /// Data Width for the Wide Ports - parameter int unsigned WideDataWidth = 0, + parameter int unsigned WideDataWidth = 0, /// Number of Narrow Ports - parameter int unsigned NumNarrowReq = 0, + parameter int unsigned NumNarrowReq = 0, /// Number of Wide Ports - parameter int unsigned NumWideReq = 0, + parameter int unsigned NumWideReq = 0, /// Banking Factor for the Wide Ports (power of 2) - parameter int unsigned NumWideBanks = (1<<$clog2(NumWideReq))*2, + parameter int unsigned NumWideBanks = (1 << $clog2(NumWideReq)) * 2, /// Extra multiplier for the Narrow banking factor (baseline is WideWidth/NarrowWidth) (power of 2) - parameter int unsigned NarrowExtraBF = 1, + parameter int unsigned NarrowExtraBF = 1, /// Words per memory bank. (Total number of banks is (WideWidth/NarrowWidth)*NumWideBanks) - parameter int unsigned WordsPerBank = 1024, + parameter int unsigned WordsPerBank = 1024, /// Spill Narrow parameter int unsigned SpillNarrowReqEntry = 0, @@ -41,18 +41,18 @@ module memory_island_core #( parameter int unsigned SpillRspBank = 0, // verilog_lint: waive explicit-parameter-storage-type - parameter MemorySimInit = "none", + parameter MemorySimInit = "none", /// Relinquish narrow priority after x cycles, 0 for never. Requires SpillNarrowReqRouted==0. - parameter int unsigned WidePriorityWait = 1, + parameter int unsigned WidePriorityWait = 1, // Derived, DO NOT OVERRIDE - parameter int unsigned NarrowStrbWidth = NarrowDataWidth/8, - parameter int unsigned WideStrbWidth = WideDataWidth/8, - parameter int unsigned NWDivisor = WideDataWidth/NarrowDataWidth + parameter int unsigned NarrowStrbWidth = NarrowDataWidth / 8, + parameter int unsigned WideStrbWidth = WideDataWidth / 8, + parameter int unsigned NWDivisor = WideDataWidth / NarrowDataWidth ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // Narrow inputs input logic [NumNarrowReq-1:0] narrow_req_i, @@ -65,14 +65,14 @@ module memory_island_core #( output logic [NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_rdata_o, // Wide inputs - input logic [ NumWideReq-1:0] wide_req_i, - output logic [ NumWideReq-1:0] wide_gnt_o, - input logic [ NumWideReq-1:0][ AddrWidth-1:0] wide_addr_i, - input logic [ NumWideReq-1:0] wide_we_i, - input logic [ NumWideReq-1:0][ WideDataWidth-1:0] wide_wdata_i, - input logic [ NumWideReq-1:0][ WideStrbWidth-1:0] wide_strb_i, - output logic [ NumWideReq-1:0] wide_rvalid_o, - output logic [ NumWideReq-1:0][ WideDataWidth-1:0] wide_rdata_o + input logic [NumWideReq-1:0] wide_req_i, + output logic [NumWideReq-1:0] wide_gnt_o, + input logic [NumWideReq-1:0][ AddrWidth-1:0] wide_addr_i, + input logic [NumWideReq-1:0] wide_we_i, + input logic [NumWideReq-1:0][WideDataWidth-1:0] wide_wdata_i, + input logic [NumWideReq-1:0][WideStrbWidth-1:0] wide_strb_i, + output logic [NumWideReq-1:0] wide_rvalid_o, + output logic [NumWideReq-1:0][WideDataWidth-1:0] wide_rdata_o ); initial begin @@ -97,14 +97,14 @@ module memory_island_core #( // Wide interco: AddrWideBankBit -> AddrWideWordBit for routing // Narrow interco: AddrNarrowWideBit -> AddrNarrowWordBit for routing - localparam int unsigned AddrNarrowWordBit = $clog2(NarrowDataWidth/8); - localparam int unsigned AddrWideWordBit = $clog2(WideDataWidth/8); + localparam int unsigned AddrNarrowWordBit = $clog2(NarrowDataWidth / 8); + localparam int unsigned AddrWideWordBit = $clog2(WideDataWidth / 8); localparam int unsigned AddrNarrowWideBit = AddrWideWordBit + $clog2(NarrowExtraBF); - localparam int unsigned AddrWideBankBit = AddrWideWordBit + $clog2(NumWideBanks); - localparam int unsigned AddrTopBit = AddrWideBankBit + $clog2(WordsPerBank); + localparam int unsigned AddrWideBankBit = AddrWideWordBit + $clog2(NumWideBanks); + localparam int unsigned AddrTopBit = AddrWideBankBit + $clog2(WordsPerBank); - localparam int unsigned NarrowAddrMemWidth = AddrTopBit-AddrNarrowWideBit; - localparam int unsigned BankAddrMemWidth = $clog2(WordsPerBank); + localparam int unsigned NarrowAddrMemWidth = AddrTopBit - AddrNarrowWideBit; + localparam int unsigned BankAddrMemWidth = $clog2(WordsPerBank); localparam int unsigned NarrowIntcBankLat = 1 + SpillNarrowReqRouted + @@ -114,276 +114,273 @@ module memory_island_core #( localparam int unsigned PriorityWaitWidth = cf_math_pkg::idx_width(WidePriorityWait); - logic [ NumNarrowReq-1:0] narrow_req_entry_spill; - logic [ NumNarrowReq-1:0] narrow_gnt_entry_spill; - logic [ NumNarrowReq-1:0] [ AddrWidth-1:0] narrow_addr_entry_spill; - logic [ NumNarrowReq-1:0] narrow_we_entry_spill; - logic [ NumNarrowReq-1:0] [ NarrowDataWidth-1:0] narrow_wdata_entry_spill; - logic [ NumNarrowReq-1:0] [ NarrowStrbWidth-1:0] narrow_strb_entry_spill; - logic [ NumNarrowReq-1:0] narrow_rvalid_entry_spill; - logic [ NumNarrowReq-1:0] [ NarrowDataWidth-1:0] narrow_rdata_entry_spill; - - logic [ NumWideReq-1:0] wide_req_entry_spill; - logic [ NumWideReq-1:0] wide_gnt_entry_spill; - logic [ NumWideReq-1:0] [ AddrWidth-1:0] wide_addr_entry_spill; - logic [ NumWideReq-1:0] wide_we_entry_spill; - logic [ NumWideReq-1:0] [ WideDataWidth-1:0] wide_wdata_entry_spill; - logic [ NumWideReq-1:0] [ WideStrbWidth-1:0] wide_strb_entry_spill; - logic [ NumWideReq-1:0] wide_rvalid_entry_spill; - logic [ NumWideReq-1:0] [ WideDataWidth-1:0] wide_rdata_entry_spill; - - logic [WidePseudoBanks-1:0] narrow_req_routed; - logic [WidePseudoBanks-1:0] narrow_gnt_routed; - logic [WidePseudoBanks-1:0] [NarrowAddrMemWidth-1:0] narrow_addr_routed; - logic [WidePseudoBanks-1:0] narrow_we_routed; - logic [WidePseudoBanks-1:0] [ NarrowDataWidth-1:0] narrow_wdata_routed; - logic [WidePseudoBanks-1:0] [ NarrowStrbWidth-1:0] narrow_strb_routed; - logic [WidePseudoBanks-1:0] [ NarrowDataWidth-1:0] narrow_rdata_routed; - - logic [WidePseudoBanks-1:0] narrow_req_routed_spill; - logic [WidePseudoBanks-1:0] narrow_gnt_routed_spill; - logic [WidePseudoBanks-1:0] [NarrowAddrMemWidth-1:0] narrow_addr_routed_spill; - logic [WidePseudoBanks-1:0] narrow_we_routed_spill; - logic [WidePseudoBanks-1:0] [ NarrowDataWidth-1:0] narrow_wdata_routed_spill; - logic [WidePseudoBanks-1:0] [ NarrowStrbWidth-1:0] narrow_strb_routed_spill; - logic [WidePseudoBanks-1:0] [ NarrowDataWidth-1:0] narrow_rdata_routed_spill; - - logic [ NumWideBanks-1:0] wide_req_routed; - logic [ NumWideBanks-1:0] wide_gnt_routed; - logic [ NumWideBanks-1:0] [ BankAddrMemWidth-1:0] wide_addr_routed; - logic [ NumWideBanks-1:0] wide_we_routed; - logic [ NumWideBanks-1:0] [ WideDataWidth-1:0] wide_wdata_routed; - logic [ NumWideBanks-1:0] [ WideStrbWidth-1:0] wide_strb_routed; - logic [ NumWideBanks-1:0] wide_rvalid_routed; - logic [ NumWideBanks-1:0] wide_rready_routed; - logic [ NumWideBanks-1:0] [ WideDataWidth-1:0] wide_rdata_routed; - - logic [ NumWideBanks-1:0] wide_req_routed_spill; - logic [ NumWideBanks-1:0] wide_gnt_routed_spill; - logic [ NumWideBanks-1:0] [ BankAddrMemWidth-1:0] wide_addr_routed_spill; - logic [ NumWideBanks-1:0] wide_we_routed_spill; - logic [ NumWideBanks-1:0] [ WideDataWidth-1:0] wide_wdata_routed_spill; - logic [ NumWideBanks-1:0] [ WideStrbWidth-1:0] wide_strb_routed_spill; - logic [ NumWideBanks-1:0] wide_rvalid_routed_spill; - logic [ NumWideBanks-1:0] wide_rready_routed_spill; - logic [ NumWideBanks-1:0] [ WideDataWidth-1:0] wide_rdata_routed_spill; - - logic [ NumWideBanks-1:0][NWDivisor-1:0] narrow_req_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0] narrow_gnt_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ BankAddrMemWidth-1:0] narrow_addr_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0] narrow_we_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] narrow_wdata_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowStrbWidth-1:0] narrow_strb_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] narrow_rdata_bank; - - logic [ NumWideBanks-1:0][NWDivisor-1:0] wide_req_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0] wide_gnt_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ BankAddrMemWidth-1:0] wide_addr_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0] wide_we_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] wide_wdata_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowStrbWidth-1:0] wide_strb_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0] wide_rvalid_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] wide_rdata_bank; - - logic [ NumWideBanks-1:0][NWDivisor-1:0] wide_req_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0] wide_gnt_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ BankAddrMemWidth-1:0] wide_addr_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0] wide_we_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] wide_wdata_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowStrbWidth-1:0] wide_strb_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0] wide_rvalid_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] wide_rdata_bank_spill; - - logic [ NumWideBanks-1:0][NWDivisor-1:0] req_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ BankAddrMemWidth-1:0] addr_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0] we_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] wdata_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowStrbWidth-1:0] strb_bank; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] rdata_bank; - - logic [ NumWideBanks-1:0][NWDivisor-1:0] req_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ BankAddrMemWidth-1:0] addr_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0] we_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] wdata_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowStrbWidth-1:0] strb_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] rdata_bank_spill; - - logic [ NumWideBanks-1:0][NWDivisor-1:0] narrow_priority_req; - logic [ NumWideBanks-1:0][NWDivisor-1:0][ PriorityWaitWidth-1:0] wide_priority_d, - wide_priority_q; + logic [NumNarrowReq-1:0] narrow_req_entry_spill; + logic [NumNarrowReq-1:0] narrow_gnt_entry_spill; + logic [NumNarrowReq-1:0][AddrWidth-1:0] narrow_addr_entry_spill; + logic [NumNarrowReq-1:0] narrow_we_entry_spill; + logic [NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_wdata_entry_spill; + logic [NumNarrowReq-1:0][NarrowStrbWidth-1:0] narrow_strb_entry_spill; + logic [NumNarrowReq-1:0] narrow_rvalid_entry_spill; + logic [NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_rdata_entry_spill; + + logic [NumWideReq-1:0] wide_req_entry_spill; + logic [NumWideReq-1:0] wide_gnt_entry_spill; + logic [NumWideReq-1:0][AddrWidth-1:0] wide_addr_entry_spill; + logic [NumWideReq-1:0] wide_we_entry_spill; + logic [NumWideReq-1:0][WideDataWidth-1:0] wide_wdata_entry_spill; + logic [NumWideReq-1:0][WideStrbWidth-1:0] wide_strb_entry_spill; + logic [NumWideReq-1:0] wide_rvalid_entry_spill; + logic [NumWideReq-1:0][WideDataWidth-1:0] wide_rdata_entry_spill; + + logic [WidePseudoBanks-1:0] narrow_req_routed; + logic [WidePseudoBanks-1:0] narrow_gnt_routed; + logic [WidePseudoBanks-1:0][NarrowAddrMemWidth-1:0] narrow_addr_routed; + logic [WidePseudoBanks-1:0] narrow_we_routed; + logic [WidePseudoBanks-1:0][NarrowDataWidth-1:0] narrow_wdata_routed; + logic [WidePseudoBanks-1:0][NarrowStrbWidth-1:0] narrow_strb_routed; + logic [WidePseudoBanks-1:0][NarrowDataWidth-1:0] narrow_rdata_routed; + + logic [WidePseudoBanks-1:0] narrow_req_routed_spill; + logic [WidePseudoBanks-1:0] narrow_gnt_routed_spill; + logic [WidePseudoBanks-1:0][NarrowAddrMemWidth-1:0] narrow_addr_routed_spill; + logic [WidePseudoBanks-1:0] narrow_we_routed_spill; + logic [WidePseudoBanks-1:0][NarrowDataWidth-1:0] narrow_wdata_routed_spill; + logic [WidePseudoBanks-1:0][NarrowStrbWidth-1:0] narrow_strb_routed_spill; + logic [WidePseudoBanks-1:0][NarrowDataWidth-1:0] narrow_rdata_routed_spill; + + logic [NumWideBanks-1:0] wide_req_routed; + logic [NumWideBanks-1:0] wide_gnt_routed; + logic [NumWideBanks-1:0][BankAddrMemWidth-1:0] wide_addr_routed; + logic [NumWideBanks-1:0] wide_we_routed; + logic [NumWideBanks-1:0][WideDataWidth-1:0] wide_wdata_routed; + logic [NumWideBanks-1:0][WideStrbWidth-1:0] wide_strb_routed; + logic [NumWideBanks-1:0] wide_rvalid_routed; + logic [NumWideBanks-1:0] wide_rready_routed; + logic [NumWideBanks-1:0][WideDataWidth-1:0] wide_rdata_routed; + + logic [NumWideBanks-1:0] wide_req_routed_spill; + logic [NumWideBanks-1:0] wide_gnt_routed_spill; + logic [NumWideBanks-1:0][BankAddrMemWidth-1:0] wide_addr_routed_spill; + logic [NumWideBanks-1:0] wide_we_routed_spill; + logic [NumWideBanks-1:0][WideDataWidth-1:0] wide_wdata_routed_spill; + logic [NumWideBanks-1:0][WideStrbWidth-1:0] wide_strb_routed_spill; + logic [NumWideBanks-1:0] wide_rvalid_routed_spill; + logic [NumWideBanks-1:0] wide_rready_routed_spill; + logic [NumWideBanks-1:0][WideDataWidth-1:0] wide_rdata_routed_spill; + + logic [NumWideBanks-1:0][NWDivisor-1:0] narrow_req_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0] narrow_gnt_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][BankAddrMemWidth-1:0] narrow_addr_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0] narrow_we_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] narrow_wdata_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowStrbWidth-1:0] narrow_strb_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] narrow_rdata_bank; + + logic [NumWideBanks-1:0][NWDivisor-1:0] wide_req_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0] wide_gnt_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][BankAddrMemWidth-1:0] wide_addr_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0] wide_we_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] wide_wdata_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowStrbWidth-1:0] wide_strb_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0] wide_rvalid_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] wide_rdata_bank; + + logic [NumWideBanks-1:0][NWDivisor-1:0] wide_req_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0] wide_gnt_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0][BankAddrMemWidth-1:0] wide_addr_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0] wide_we_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] wide_wdata_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowStrbWidth-1:0] wide_strb_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0] wide_rvalid_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] wide_rdata_bank_spill; + + logic [NumWideBanks-1:0][NWDivisor-1:0] req_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][BankAddrMemWidth-1:0] addr_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0] we_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] wdata_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowStrbWidth-1:0] strb_bank; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] rdata_bank; + + logic [NumWideBanks-1:0][NWDivisor-1:0] req_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0][BankAddrMemWidth-1:0] addr_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0] we_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] wdata_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowStrbWidth-1:0] strb_bank_spill; + logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] rdata_bank_spill; + + logic [NumWideBanks-1:0][NWDivisor-1:0] narrow_priority_req; + logic [NumWideBanks-1:0][NWDivisor-1:0][PriorityWaitWidth-1:0] wide_priority_d, wide_priority_q; for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_entry_cuts mem_req_multicut #( - .DataWidth ( NarrowDataWidth ), - .AddrWidth ( AddrWidth ), - .NumCuts ( SpillNarrowReqEntry ) + .DataWidth(NarrowDataWidth), + .AddrWidth(AddrWidth), + .NumCuts (SpillNarrowReqEntry) ) i_spill_narrow_req_entry ( .clk_i, .rst_ni, - .req_i ( narrow_req_i [i] ), - .gnt_o ( narrow_gnt_o [i] ), - .addr_i ( narrow_addr_i [i] ), - .we_i ( narrow_we_i [i] ), - .wdata_i ( narrow_wdata_i [i] ), - .strb_i ( narrow_strb_i [i] ), - - .req_o ( narrow_req_entry_spill [i] ), - .gnt_i ( narrow_gnt_entry_spill [i] ), - .addr_o ( narrow_addr_entry_spill [i] ), - .we_o ( narrow_we_entry_spill [i] ), - .wdata_o ( narrow_wdata_entry_spill[i] ), - .strb_o ( narrow_strb_entry_spill [i] ) + .req_i (narrow_req_i[i]), + .gnt_o (narrow_gnt_o[i]), + .addr_i (narrow_addr_i[i]), + .we_i (narrow_we_i[i]), + .wdata_i(narrow_wdata_i[i]), + .strb_i (narrow_strb_i[i]), + + .req_o (narrow_req_entry_spill[i]), + .gnt_i (narrow_gnt_entry_spill[i]), + .addr_o (narrow_addr_entry_spill[i]), + .we_o (narrow_we_entry_spill[i]), + .wdata_o(narrow_wdata_entry_spill[i]), + .strb_o (narrow_strb_entry_spill[i]) ); mem_rsp_multicut #( - .DataWidth ( NarrowDataWidth ), - .NumCuts ( SpillNarrowRspEntry ) + .DataWidth(NarrowDataWidth), + .NumCuts (SpillNarrowRspEntry) ) i_spill_narrow_rsp_entry ( .clk_i, .rst_ni, - .rvalid_i ( narrow_rvalid_entry_spill[i] ), - .rready_o (), - .rdata_i ( narrow_rdata_entry_spill [i] ), + .rvalid_i(narrow_rvalid_entry_spill[i]), + .rready_o(), + .rdata_i (narrow_rdata_entry_spill[i]), - .rvalid_o ( narrow_rvalid_o [i] ), - .rready_i ( 1'b1 ), - .rdata_o ( narrow_rdata_o [i] ) + .rvalid_o(narrow_rvalid_o[i]), + .rready_i(1'b1), + .rdata_o (narrow_rdata_o[i]) ); end for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_entry_cuts mem_req_multicut #( - .DataWidth ( WideDataWidth ), - .AddrWidth ( AddrWidth ), - .NumCuts ( SpillWideReqEntry ) + .DataWidth(WideDataWidth), + .AddrWidth(AddrWidth), + .NumCuts (SpillWideReqEntry) ) i_spill_wide_req_entry ( .clk_i, .rst_ni, - .req_i ( wide_req_i [i] ), - .gnt_o ( wide_gnt_o [i] ), - .addr_i ( wide_addr_i [i] ), - .we_i ( wide_we_i [i] ), - .wdata_i ( wide_wdata_i [i] ), - .strb_i ( wide_strb_i [i] ), - - .req_o ( wide_req_entry_spill [i] ), - .gnt_i ( wide_gnt_entry_spill [i] ), - .addr_o ( wide_addr_entry_spill [i] ), - .we_o ( wide_we_entry_spill [i] ), - .wdata_o ( wide_wdata_entry_spill[i] ), - .strb_o ( wide_strb_entry_spill [i] ) + .req_i (wide_req_i[i]), + .gnt_o (wide_gnt_o[i]), + .addr_i (wide_addr_i[i]), + .we_i (wide_we_i[i]), + .wdata_i(wide_wdata_i[i]), + .strb_i (wide_strb_i[i]), + + .req_o (wide_req_entry_spill[i]), + .gnt_i (wide_gnt_entry_spill[i]), + .addr_o (wide_addr_entry_spill[i]), + .we_o (wide_we_entry_spill[i]), + .wdata_o(wide_wdata_entry_spill[i]), + .strb_o (wide_strb_entry_spill[i]) ); mem_rsp_multicut #( - .DataWidth ( WideDataWidth ), - .NumCuts ( SpillWideRspEntry ) + .DataWidth(WideDataWidth), + .NumCuts (SpillWideRspEntry) ) i_spill_wide_rsp_entry ( .clk_i, .rst_ni, - .rvalid_i ( wide_rvalid_entry_spill[i] ), - .rready_o (), - .rdata_i ( wide_rdata_entry_spill [i] ), + .rvalid_i(wide_rvalid_entry_spill[i]), + .rready_o(), + .rdata_i (wide_rdata_entry_spill[i]), - .rvalid_o ( wide_rvalid_o [i] ), - .rready_i ( 1'b1 ), - .rdata_o ( wide_rdata_o [i] ) + .rvalid_o(wide_rvalid_o[i]), + .rready_i(1'b1), + .rdata_o (wide_rdata_o[i]) ); end // Narrow interconnect // Fixed latency as higher priority for narrow accesses tcdm_interconnect #( - .NumIn ( NumNarrowReq ), - .NumOut ( WidePseudoBanks ), - .AddrWidth ( AddrWidth ), - .DataWidth ( NarrowDataWidth ), - .BeWidth ( NarrowStrbWidth ), - .AddrMemWidth ( NarrowAddrMemWidth ), - .WriteRespOn ( 1 ), - .RespLat ( NarrowIntcBankLat ), - .Topology ( tcdm_interconnect_pkg::LIC ) + .NumIn (NumNarrowReq), + .NumOut (WidePseudoBanks), + .AddrWidth (AddrWidth), + .DataWidth (NarrowDataWidth), + .BeWidth (NarrowStrbWidth), + .AddrMemWidth(NarrowAddrMemWidth), + .WriteRespOn (1), + .RespLat (NarrowIntcBankLat), + .Topology (tcdm_interconnect_pkg::LIC) ) i_narrow_interco ( .clk_i, .rst_ni, - .req_i ( narrow_req_entry_spill ), - .add_i ( narrow_addr_entry_spill ), - .wen_i ( narrow_we_entry_spill ), - .wdata_i ( narrow_wdata_entry_spill ), - .be_i ( narrow_strb_entry_spill ), - .gnt_o ( narrow_gnt_entry_spill ), - .vld_o ( narrow_rvalid_entry_spill ), - .rdata_o ( narrow_rdata_entry_spill ), - - .req_o ( narrow_req_routed ), - .gnt_i ( narrow_gnt_routed ), - .add_o ( narrow_addr_routed ), - .wen_o ( narrow_we_routed ), - .wdata_o ( narrow_wdata_routed ), - .be_o ( narrow_strb_routed ), - .rdata_i ( narrow_rdata_routed ) + .req_i (narrow_req_entry_spill), + .add_i (narrow_addr_entry_spill), + .wen_i (narrow_we_entry_spill), + .wdata_i(narrow_wdata_entry_spill), + .be_i (narrow_strb_entry_spill), + .gnt_o (narrow_gnt_entry_spill), + .vld_o (narrow_rvalid_entry_spill), + .rdata_o(narrow_rdata_entry_spill), + + .req_o (narrow_req_routed), + .gnt_i (narrow_gnt_routed), + .add_o (narrow_addr_routed), + .wen_o (narrow_we_routed), + .wdata_o(narrow_wdata_routed), + .be_o (narrow_strb_routed), + .rdata_i(narrow_rdata_routed) ); for (genvar i = 0; i < WidePseudoBanks; i++) begin : gen_spill_narrow_routed mem_req_multicut #( - .AddrWidth ( NarrowAddrMemWidth ), - .DataWidth ( NarrowDataWidth ), - .NumCuts ( SpillNarrowReqRouted ) + .AddrWidth(NarrowAddrMemWidth), + .DataWidth(NarrowDataWidth), + .NumCuts (SpillNarrowReqRouted) ) i_spill_narrow_req_routed ( .clk_i, .rst_ni, - .req_i ( narrow_req_routed [i] ), - .gnt_o ( narrow_gnt_routed [i] ), - .addr_i ( narrow_addr_routed [i] ), - .we_i ( narrow_we_routed [i] ), - .wdata_i ( narrow_wdata_routed [i] ), - .strb_i ( narrow_strb_routed [i] ), - - .req_o ( narrow_req_routed_spill [i] ), - .gnt_i ( narrow_gnt_routed_spill [i] ), - .addr_o ( narrow_addr_routed_spill [i] ), - .we_o ( narrow_we_routed_spill [i] ), - .wdata_o ( narrow_wdata_routed_spill[i] ), - .strb_o ( narrow_strb_routed_spill [i] ) + .req_i (narrow_req_routed[i]), + .gnt_o (narrow_gnt_routed[i]), + .addr_i (narrow_addr_routed[i]), + .we_i (narrow_we_routed[i]), + .wdata_i(narrow_wdata_routed[i]), + .strb_i (narrow_strb_routed[i]), + + .req_o (narrow_req_routed_spill[i]), + .gnt_i (narrow_gnt_routed_spill[i]), + .addr_o (narrow_addr_routed_spill[i]), + .we_o (narrow_we_routed_spill[i]), + .wdata_o(narrow_wdata_routed_spill[i]), + .strb_o (narrow_strb_routed_spill[i]) ); mem_rsp_multicut #( - .DataWidth ( NarrowDataWidth ), - .NumCuts ( SpillNarrowRspRouted ) + .DataWidth(NarrowDataWidth), + .NumCuts (SpillNarrowRspRouted) ) i_spill_narrow_rsp_routed ( .clk_i, .rst_ni, - .rvalid_i ( 1'b1 ), // Static latency, signal not used - .rready_o (), - .rdata_i ( narrow_rdata_routed_spill[i] ), + .rvalid_i(1'b1), // Static latency, signal not used + .rready_o(), + .rdata_i (narrow_rdata_routed_spill[i]), - .rvalid_o (), - .rready_i ( 1'b1 ), - .rdata_o ( narrow_rdata_routed [i] ) + .rvalid_o(), + .rready_i(1'b1), + .rdata_o (narrow_rdata_routed[i]) ); end - localparam int unsigned NarrowWideBankSelWidth = AddrWideBankBit-AddrNarrowWideBit; + localparam int unsigned NarrowWideBankSelWidth = AddrWideBankBit - AddrNarrowWideBit; if (WidePriorityWait == 0) begin : gen_narrow_static_gnt // narrow gnt always set assign narrow_gnt_routed_spill = '1; end else begin : gen_narrow_gnt - for (genvar extraFactor = 0; - extraFactor < NarrowExtraBF; - extraFactor++) begin : gen_narrow_gnt_l1 - for (genvar subBank = 0; - subBank < NWDivisor; - subBank++) begin : gen_narrow_gnt_l2 - localparam int unsigned PseudoIdx = (extraFactor*NWDivisor) + subBank; + for ( + genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++ + ) begin : gen_narrow_gnt_l1 + for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_gnt_l2 + localparam int unsigned PseudoIdx = (extraFactor * NWDivisor) + subBank; always_comb begin - narrow_gnt_routed_spill[(extraFactor*NWDivisor) + subBank] = '0; - for (int wideBank = 0; wideBank < TotalBanks/WidePseudoBanks; wideBank++) begin - if (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank) begin + narrow_gnt_routed_spill[(extraFactor*NWDivisor)+subBank] = '0; + for (int wideBank = 0; wideBank < TotalBanks / WidePseudoBanks; wideBank++) begin + if (narrow_addr_routed_spill[PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank) begin narrow_gnt_routed_spill[PseudoIdx] = narrow_gnt_bank [(wideBank*NarrowExtraBF)+extraFactor][subBank]; end @@ -394,45 +391,41 @@ module memory_island_core #( end // Route narrow requests to the correct bank, only requesting from the necessary banks - for (genvar wideBank = 0; - wideBank < TotalBanks/WidePseudoBanks; - wideBank++) begin : gen_narrow_routed_bank_l1 - for (genvar extraFactor = 0; - extraFactor < NarrowExtraBF; - extraFactor++) begin : gen_narrow_routed_bank_l2 - for (genvar subBank = 0; - subBank < NWDivisor; - subBank++) begin : gen_narrow_routed_bank_l3 - localparam int unsigned WideBankIdx = (wideBank*NarrowExtraBF) + extraFactor; - localparam int unsigned PseudoIdx = (extraFactor*NWDivisor) + subBank; + for ( + genvar wideBank = 0; wideBank < TotalBanks / WidePseudoBanks; wideBank++ + ) begin : gen_narrow_routed_bank_l1 + for ( + genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++ + ) begin : gen_narrow_routed_bank_l2 + for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_routed_bank_l3 + localparam int unsigned WideBankIdx = (wideBank * NarrowExtraBF) + extraFactor; + localparam int unsigned PseudoIdx = (extraFactor * NWDivisor) + subBank; assign narrow_req_bank [WideBankIdx][subBank] = narrow_req_routed_spill [PseudoIdx] & (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank); assign narrow_addr_bank [WideBankIdx][subBank] = narrow_addr_routed_spill [PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth]; - assign narrow_we_bank [WideBankIdx][subBank] = narrow_we_routed_spill [PseudoIdx]; + assign narrow_we_bank[WideBankIdx][subBank] = narrow_we_routed_spill[PseudoIdx]; assign narrow_wdata_bank[WideBankIdx][subBank] = narrow_wdata_routed_spill[PseudoIdx]; - assign narrow_strb_bank [WideBankIdx][subBank] = narrow_strb_routed_spill [PseudoIdx]; + assign narrow_strb_bank[WideBankIdx][subBank] = narrow_strb_routed_spill[PseudoIdx]; end end end // Shift registers to properly select response data - for (genvar extraFactor = 0; - extraFactor < NarrowExtraBF; - extraFactor++) begin : gen_narrow_routed_bank_rdata_l1 - for (genvar subBank = 0; - subBank < NWDivisor; - subBank++) begin : gen_narrow_routed_bank_rdata_l2 - localparam int unsigned PseudoIdx = (extraFactor*NWDivisor) + subBank; + for ( + genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++ + ) begin : gen_narrow_routed_bank_rdata_l1 + for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_routed_bank_rdata_l2 + localparam int unsigned PseudoIdx = (extraFactor * NWDivisor) + subBank; logic [NarrowWideBankSelWidth-1:0] narrow_rdata_sel; shift_reg #( - .dtype ( logic [NarrowWideBankSelWidth-1:0] ), - .Depth ( NarrowIntcBankLat ) + .dtype(logic [NarrowWideBankSelWidth-1:0]), + .Depth(NarrowIntcBankLat) ) i_narrow_rdata_sel ( .clk_i, .rst_ni, - .d_i ( narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] ), - .d_o ( narrow_rdata_sel ) + .d_i(narrow_addr_routed_spill[PseudoIdx][NarrowWideBankSelWidth-1:0]), + .d_o(narrow_rdata_sel) ); assign narrow_rdata_routed_spill[PseudoIdx] = narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF) + extraFactor][subBank]; @@ -441,187 +434,187 @@ module memory_island_core #( // Wide interconnect varlat_inorder_interco #( - .NumIn ( NumWideReq ), - .NumOut ( NumWideBanks ), - .AddrWidth ( AddrWidth ), - .DataWidth ( WideDataWidth ), - .BeWidth ( WideStrbWidth ), - .AddrMemWidth ( BankAddrMemWidth ), - .WriteRespOn ( 1 ), - .NumOutstanding ( 3 ), - .Topology ( tcdm_interconnect_pkg::LIC ) + .NumIn (NumWideReq), + .NumOut (NumWideBanks), + .AddrWidth (AddrWidth), + .DataWidth (WideDataWidth), + .BeWidth (WideStrbWidth), + .AddrMemWidth (BankAddrMemWidth), + .WriteRespOn (1), + .NumOutstanding(3), + .Topology (tcdm_interconnect_pkg::LIC) ) i_wide_interco ( .clk_i, .rst_ni, - .req_i ( wide_req_entry_spill ), - .add_i ( wide_addr_entry_spill ), - .we_i ( wide_we_entry_spill ), - .wdata_i ( wide_wdata_entry_spill ), - .be_i ( wide_strb_entry_spill ), - .gnt_o ( wide_gnt_entry_spill ), - .vld_o ( wide_rvalid_entry_spill ), - .rdata_o ( wide_rdata_entry_spill ), - - .req_o ( wide_req_routed ), - .gnt_i ( wide_gnt_routed ), - .add_o ( wide_addr_routed ), - .we_o ( wide_we_routed ), - .wdata_o ( wide_wdata_routed ), - .be_o ( wide_strb_routed ), - .rvalid_i ( wide_rvalid_routed ), - .rready_o ( wide_rready_routed ), - .rdata_i ( wide_rdata_routed ) + .req_i (wide_req_entry_spill), + .add_i (wide_addr_entry_spill), + .we_i (wide_we_entry_spill), + .wdata_i(wide_wdata_entry_spill), + .be_i (wide_strb_entry_spill), + .gnt_o (wide_gnt_entry_spill), + .vld_o (wide_rvalid_entry_spill), + .rdata_o(wide_rdata_entry_spill), + + .req_o (wide_req_routed), + .gnt_i (wide_gnt_routed), + .add_o (wide_addr_routed), + .we_o (wide_we_routed), + .wdata_o (wide_wdata_routed), + .be_o (wide_strb_routed), + .rvalid_i(wide_rvalid_routed), + .rready_o(wide_rready_routed), + .rdata_i (wide_rdata_routed) ); for (genvar i = 0; i < NumWideBanks; i++) begin : gen_wide_banks mem_req_multicut #( - .DataWidth ( WideDataWidth ), - .AddrWidth ( BankAddrMemWidth ), - .NumCuts ( SpillWideReqRouted ) + .DataWidth(WideDataWidth), + .AddrWidth(BankAddrMemWidth), + .NumCuts (SpillWideReqRouted) ) i_spill_wide_req_routed ( .clk_i, .rst_ni, - .req_i ( wide_req_routed [i] ), - .gnt_o ( wide_gnt_routed [i] ), - .addr_i ( wide_addr_routed [i] ), - .we_i ( wide_we_routed [i] ), - .wdata_i ( wide_wdata_routed [i] ), - .strb_i ( wide_strb_routed [i] ), - - .req_o ( wide_req_routed_spill [i] ), - .gnt_i ( wide_gnt_routed_spill [i] ), - .addr_o ( wide_addr_routed_spill [i] ), - .we_o ( wide_we_routed_spill [i] ), - .wdata_o ( wide_wdata_routed_spill[i] ), - .strb_o ( wide_strb_routed_spill [i] ) + .req_i (wide_req_routed[i]), + .gnt_o (wide_gnt_routed[i]), + .addr_i (wide_addr_routed[i]), + .we_i (wide_we_routed[i]), + .wdata_i(wide_wdata_routed[i]), + .strb_i (wide_strb_routed[i]), + + .req_o (wide_req_routed_spill[i]), + .gnt_i (wide_gnt_routed_spill[i]), + .addr_o (wide_addr_routed_spill[i]), + .we_o (wide_we_routed_spill[i]), + .wdata_o(wide_wdata_routed_spill[i]), + .strb_o (wide_strb_routed_spill[i]) ); mem_rsp_multicut #( - .DataWidth ( WideDataWidth ), - .NumCuts ( SpillWideRspRouted ) + .DataWidth(WideDataWidth), + .NumCuts (SpillWideRspRouted) ) i_spill_wide_rsp_routed ( .clk_i, .rst_ni, - .rvalid_i ( wide_rvalid_routed_spill[i] ), - .rready_o ( wide_rready_routed_spill[i] ), - .rdata_i ( wide_rdata_routed_spill [i] ), + .rvalid_i(wide_rvalid_routed_spill[i]), + .rready_o(wide_rready_routed_spill[i]), + .rdata_i (wide_rdata_routed_spill[i]), - .rvalid_o ( wide_rvalid_routed [i] ), - .rready_i ( wide_rready_routed [i] ), - .rdata_o ( wide_rdata_routed [i] ) + .rvalid_o(wide_rvalid_routed[i]), + .rready_i(wide_rready_routed[i]), + .rdata_o (wide_rdata_routed[i]) ); logic [NWDivisor-1:0][BankAddrMemWidth + AddrWideWordBit-1:0] bank_addr_tmp; for (genvar j = 0; j < NWDivisor; j++) begin : gen_wide_addr_assign - assign wide_addr_bank[i][j] = bank_addr_tmp [j][AddrWideWordBit+:BankAddrMemWidth]; + assign wide_addr_bank[i][j] = bank_addr_tmp[j][AddrWideWordBit+:BankAddrMemWidth]; end // Split wide requests to banks stream_mem_to_banks_det #( - .AddrWidth ( BankAddrMemWidth + AddrWideWordBit ), - .DataWidth ( WideDataWidth ), - .WUserWidth ( 1 ), - .RUserWidth ( 1 ), - .NumBanks ( NWDivisor ), - .HideStrb ( 1'b1 ), - .MaxTrans ( 2 ), // TODO tune? - .FifoDepth ( 3 ) // TODO tune? + .AddrWidth (BankAddrMemWidth + AddrWideWordBit), + .DataWidth (WideDataWidth), + .WUserWidth(1), + .RUserWidth(1), + .NumBanks (NWDivisor), + .HideStrb (1'b1), + .MaxTrans (2), // TODO tune? + .FifoDepth (3) // TODO tune? ) i_wide_to_banks ( .clk_i, .rst_ni, - .req_i ( wide_req_routed_spill [i] ), - .gnt_o ( wide_gnt_routed_spill [i] ), - .addr_i ( {wide_addr_routed_spill [i], {AddrWideWordBit{1'b0}}} ), - .wdata_i ( wide_wdata_routed_spill [i] ), - .strb_i ( wide_strb_routed_spill [i] ), - .wuser_i ( '0 ), - .we_i ( wide_we_routed_spill [i] ), - .rvalid_o ( wide_rvalid_routed_spill[i] ), - .rready_i ( wide_rready_routed_spill[i] ), - .ruser_o (), - .rdata_o ( wide_rdata_routed_spill [i] ), - - .bank_req_o ( wide_req_bank [i] ), - .bank_gnt_i ( wide_gnt_bank [i] ), - .bank_addr_o ( bank_addr_tmp ), - .bank_wdata_o ( wide_wdata_bank [i] ), - .bank_strb_o ( wide_strb_bank [i] ), - .bank_wuser_o (), - .bank_we_o ( wide_we_bank [i] ), - .bank_rvalid_i ( wide_rvalid_bank[i] ), - .bank_rdata_i ( wide_rdata_bank [i] ), - .bank_ruser_i ( '0 ) + .req_i (wide_req_routed_spill[i]), + .gnt_o (wide_gnt_routed_spill[i]), + .addr_i ({wide_addr_routed_spill[i], {AddrWideWordBit{1'b0}}}), + .wdata_i (wide_wdata_routed_spill[i]), + .strb_i (wide_strb_routed_spill[i]), + .wuser_i ('0), + .we_i (wide_we_routed_spill[i]), + .rvalid_o(wide_rvalid_routed_spill[i]), + .rready_i(wide_rready_routed_spill[i]), + .ruser_o (), + .rdata_o (wide_rdata_routed_spill[i]), + + .bank_req_o (wide_req_bank[i]), + .bank_gnt_i (wide_gnt_bank[i]), + .bank_addr_o (bank_addr_tmp), + .bank_wdata_o (wide_wdata_bank[i]), + .bank_strb_o (wide_strb_bank[i]), + .bank_wuser_o (), + .bank_we_o (wide_we_bank[i]), + .bank_rvalid_i(wide_rvalid_bank[i]), + .bank_rdata_i (wide_rdata_bank[i]), + .bank_ruser_i ('0) ); for (genvar j = 0; j < NWDivisor; j++) begin : gen_narrow_banks mem_req_multicut #( - .DataWidth ( NarrowDataWidth ), - .AddrWidth ( BankAddrMemWidth ), - .NumCuts ( SpillWideReqSplit ) + .DataWidth(NarrowDataWidth), + .AddrWidth(BankAddrMemWidth), + .NumCuts (SpillWideReqSplit) ) i_spill_wide_req_split ( .clk_i, .rst_ni, - .req_i ( wide_req_bank [i][j] ), - .gnt_o ( wide_gnt_bank [i][j] ), - .addr_i ( wide_addr_bank [i][j] ), - .we_i ( wide_we_bank [i][j] ), - .wdata_i ( wide_wdata_bank [i][j] ), - .strb_i ( wide_strb_bank [i][j] ), - - .req_o ( wide_req_bank_spill [i][j] ), - .gnt_i ( wide_gnt_bank_spill [i][j] ), - .addr_o ( wide_addr_bank_spill [i][j] ), - .we_o ( wide_we_bank_spill [i][j] ), - .wdata_o ( wide_wdata_bank_spill[i][j] ), - .strb_o ( wide_strb_bank_spill [i][j] ) + .req_i (wide_req_bank[i][j]), + .gnt_o (wide_gnt_bank[i][j]), + .addr_i (wide_addr_bank[i][j]), + .we_i (wide_we_bank[i][j]), + .wdata_i(wide_wdata_bank[i][j]), + .strb_i (wide_strb_bank[i][j]), + + .req_o (wide_req_bank_spill[i][j]), + .gnt_i (wide_gnt_bank_spill[i][j]), + .addr_o (wide_addr_bank_spill[i][j]), + .we_o (wide_we_bank_spill[i][j]), + .wdata_o(wide_wdata_bank_spill[i][j]), + .strb_o (wide_strb_bank_spill[i][j]) ); mem_rsp_multicut #( - .DataWidth ( NarrowDataWidth ), - .NumCuts ( SpillWideRspSplit ) + .DataWidth(NarrowDataWidth), + .NumCuts (SpillWideRspSplit) ) i_spill_wide_rsp_split ( .clk_i, .rst_ni, - .rvalid_i ( wide_rvalid_bank_spill[i][j] ), - .rready_o (), - .rdata_i ( wide_rdata_bank_spill [i][j] ), + .rvalid_i(wide_rvalid_bank_spill[i][j]), + .rready_o(), + .rdata_i (wide_rdata_bank_spill[i][j]), - .rvalid_o ( wide_rvalid_bank [i][j] ), - .rready_i ( 1'b1 ), - .rdata_o ( wide_rdata_bank [i][j] ) + .rvalid_o(wide_rvalid_bank[i][j]), + .rready_i(1'b1), + .rdata_o (wide_rdata_bank[i][j]) ); if (WidePriorityWait == 0) begin : gen_narrow_priority // narrow always has priority assign narrow_priority_req[i][j] = narrow_req_bank[i][j]; - assign wide_priority_d [i][j] = '0; + assign wide_priority_d[i][j] = '0; end else begin : gen_priority always_comb begin // by default reset - wide_priority_d [i][j] = '0; + wide_priority_d[i][j] = '0; // by default narrow priority - narrow_priority_req [i][j] = narrow_req_bank[i][j]; + narrow_priority_req[i][j] = narrow_req_bank[i][j]; // if both are requesting, increment counter - if (narrow_req_bank [i][j] && wide_req_bank_spill[i][j]) begin - wide_priority_d [i][j] = wide_priority_q[i][j] + 1; + if (narrow_req_bank[i][j] && wide_req_bank_spill[i][j]) begin + wide_priority_d[i][j] = wide_priority_q[i][j] + 1; end // if counter has reached max, give wide priority - if (wide_priority_q [i][j] == WidePriorityWait) begin - wide_priority_d [i][j] = '0; + if (wide_priority_q[i][j] == WidePriorityWait) begin + wide_priority_d[i][j] = '0; narrow_priority_req[i][j] = '0; end end end // narrow/wide priority arbitration - assign req_bank [i][j] = narrow_req_bank [i][j] | wide_req_bank_spill [i][j]; - assign narrow_gnt_bank [i][j] = narrow_priority_req[i][j]; - assign wide_gnt_bank_spill [i][j] = ~narrow_priority_req[i][j]; + assign req_bank[i][j] = narrow_req_bank[i][j] | wide_req_bank_spill[i][j]; + assign narrow_gnt_bank[i][j] = narrow_priority_req[i][j]; + assign wide_gnt_bank_spill[i][j] = ~narrow_priority_req[i][j]; assign we_bank [i][j] = narrow_priority_req[i][j] ? narrow_we_bank [i][j]: wide_we_bank_spill [i][j]; assign addr_bank [i][j] = narrow_priority_req[i][j] ? narrow_addr_bank [i][j]: @@ -630,80 +623,80 @@ module memory_island_core #( wide_wdata_bank_spill[i][j]; assign strb_bank [i][j] = narrow_priority_req[i][j] ? narrow_strb_bank [i][j]: wide_strb_bank_spill [i][j]; - assign narrow_rdata_bank [i][j] = rdata_bank [i][j]; - assign wide_rdata_bank_spill[i][j] = rdata_bank [i][j]; + assign narrow_rdata_bank[i][j] = rdata_bank[i][j]; + assign wide_rdata_bank_spill[i][j] = rdata_bank[i][j]; mem_req_multicut #( - .DataWidth ( NarrowDataWidth ), - .AddrWidth ( BankAddrMemWidth ), - .NumCuts ( SpillReqBank ) + .DataWidth(NarrowDataWidth), + .AddrWidth(BankAddrMemWidth), + .NumCuts (SpillReqBank) ) i_spill_req_bank ( .clk_i, .rst_ni, - .req_i ( req_bank [i][j] ), - .gnt_o (), - .addr_i ( addr_bank [i][j] ), - .we_i ( we_bank [i][j] ), - .wdata_i ( wdata_bank [i][j] ), - .strb_i ( strb_bank [i][j] ), - - .req_o ( req_bank_spill [i][j] ), - .gnt_i ( 1'b1 ), - .addr_o ( addr_bank_spill [i][j] ), - .we_o ( we_bank_spill [i][j] ), - .wdata_o ( wdata_bank_spill[i][j] ), - .strb_o ( strb_bank_spill [i][j] ) + .req_i (req_bank[i][j]), + .gnt_o (), + .addr_i (addr_bank[i][j]), + .we_i (we_bank[i][j]), + .wdata_i(wdata_bank[i][j]), + .strb_i (strb_bank[i][j]), + + .req_o (req_bank_spill[i][j]), + .gnt_i (1'b1), + .addr_o (addr_bank_spill[i][j]), + .we_o (we_bank_spill[i][j]), + .wdata_o(wdata_bank_spill[i][j]), + .strb_o (strb_bank_spill[i][j]) ); mem_rsp_multicut #( - .DataWidth ( NarrowDataWidth ), - .NumCuts ( SpillRspBank ) + .DataWidth(NarrowDataWidth), + .NumCuts (SpillRspBank) ) i_spill_rsp_bank ( .clk_i, .rst_ni, - .rvalid_i ( 1'b1 ), - .rready_o (), - .rdata_i ( rdata_bank_spill[i][j] ), + .rvalid_i(1'b1), + .rready_o(), + .rdata_i (rdata_bank_spill[i][j]), - .rvalid_o (), - .rready_i ( 1'b1 ), - .rdata_o ( rdata_bank [i][j] ) + .rvalid_o(), + .rready_i(1'b1), + .rdata_o (rdata_bank[i][j]) ); // Memory bank tc_sram #( - .NumWords ( WordsPerBank ), - .DataWidth ( NarrowDataWidth ), - .ByteWidth ( 8 ), - .NumPorts ( 1 ), - .Latency ( 1 ), - .SimInit ( MemorySimInit ) + .NumWords (WordsPerBank), + .DataWidth(NarrowDataWidth), + .ByteWidth(8), + .NumPorts (1), + .Latency (1), + .SimInit (MemorySimInit) ) i_bank ( .clk_i, .rst_ni, - .req_i ( req_bank_spill [i][j] ), - .we_i ( we_bank_spill [i][j] ), - .addr_i ( addr_bank_spill [i][j] ), - .wdata_i ( wdata_bank_spill[i][j] ), - .be_i ( strb_bank_spill [i][j] ), - .rdata_o ( rdata_bank_spill[i][j] ) + .req_i (req_bank_spill[i][j]), + .we_i (we_bank_spill[i][j]), + .addr_i (addr_bank_spill[i][j]), + .wdata_i(wdata_bank_spill[i][j]), + .be_i (strb_bank_spill[i][j]), + .rdata_o(rdata_bank_spill[i][j]) ); // Shift reg for wide rvalid logic [SpillReqBank+SpillRspBank:0] shift_rvalid_d, shift_rvalid_q; - for (genvar k = 0; k < SpillReqBank+SpillRspBank+1; k++) begin : gen_shift_rvalid - if (k == 0) begin: gen_shift_in + for (genvar k = 0; k < SpillReqBank + SpillRspBank + 1; k++) begin : gen_shift_rvalid + if (k == 0) begin : gen_shift_in assign shift_rvalid_d[k] = req_bank[i][j] & wide_gnt_bank[i][j]; - end else begin: gen_shift + end else begin : gen_shift assign shift_rvalid_d[k] = shift_rvalid_q[k-1]; end end assign wide_rvalid_bank_spill[i][j] = shift_rvalid_q[SpillReqBank+SpillRspBank]; always_ff @(posedge clk_i or negedge rst_ni) begin : proc_wide_bank_rvalid - if(~rst_ni) begin + if (~rst_ni) begin shift_rvalid_q <= '0; end else begin shift_rvalid_q <= shift_rvalid_d; @@ -713,7 +706,7 @@ module memory_island_core #( end always_ff @(posedge clk_i or negedge rst_ni) begin : proc_wide_priority - if(!rst_ni) begin + if (!rst_ni) begin wide_priority_q <= '0; end else begin wide_priority_q <= wide_priority_d; diff --git a/src/stream_mem_to_banks_det.sv b/src/stream_mem_to_banks_det.sv index bc645ad..f8dc0fd 100644 --- a/src/stream_mem_to_banks_det.sv +++ b/src/stream_mem_to_banks_det.sv @@ -14,88 +14,88 @@ /// request and valid response direction. module stream_mem_to_banks_det #( /// Input address width. - parameter int unsigned AddrWidth = 32'd0, + parameter int unsigned AddrWidth = 32'd0, /// Input data width, must be a power of two. - parameter int unsigned DataWidth = 32'd0, + parameter int unsigned DataWidth = 32'd0, /// Request sideband width. - parameter int unsigned WUserWidth = 32'd0, + parameter int unsigned WUserWidth = 32'd0, /// Response sideband width. - parameter int unsigned RUserWidth = 32'd0, + parameter int unsigned RUserWidth = 32'd0, /// Number of banks at output, must evenly divide `DataWidth`. - parameter int unsigned NumBanks = 32'd1, + parameter int unsigned NumBanks = 32'd1, /// Remove transactions that have zero strobe - parameter bit HideStrb = 1'b0, + parameter bit HideStrb = 1'b0, /// Number of outstanding transactions - parameter int unsigned MaxTrans = 32'd1, + parameter int unsigned MaxTrans = 32'd1, /// FIFO depth, must be >=1 - parameter int unsigned FifoDepth = 32'd1, + parameter int unsigned FifoDepth = 32'd1, /// Request sideband type. - parameter type wuser_t = logic [WUserWidth-1:0], + parameter type wuser_t = logic [ WUserWidth-1:0], /// Dependent parameter, do not override! Address type. - localparam type addr_t = logic [AddrWidth-1:0], + localparam type addr_t = logic [ AddrWidth-1:0], /// Dependent parameter, do not override! Input data type. - localparam type inp_data_t = logic [DataWidth-1:0], + localparam type inp_data_t = logic [ DataWidth-1:0], /// Dependent parameter, do not override! Input write strobe type. - localparam type inp_strb_t = logic [DataWidth/8-1:0], + localparam type inp_strb_t = logic [ DataWidth/8-1:0], /// Dependent parameter, do not override! Input response sideband type. - localparam type inp_ruser_t = logic [NumBanks-1:0][RUserWidth-1:0], + localparam type inp_ruser_t = logic [ NumBanks-1:0][RUserWidth-1:0], /// Dependent parameter, do not override! Output data type. - localparam type oup_data_t = logic [DataWidth/NumBanks-1:0], + localparam type oup_data_t = logic [ DataWidth/NumBanks-1:0], /// Dependent parameter, do not override! Output write strobe type. - localparam type oup_strb_t = logic [DataWidth/NumBanks/8-1:0], + localparam type oup_strb_t = logic [DataWidth/NumBanks/8-1:0], /// Dependent parameter, do not override! Output response sideband type. - localparam type oup_ruser_t = logic [RUserWidth-1:0] + localparam type oup_ruser_t = logic [ RUserWidth-1:0] ) ( /// Clock input. - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low. - input logic rst_ni, + input logic rst_ni, /// Memory request to split, request is valid. - input logic req_i, + input logic req_i, /// Memory request to split, request can be granted. - output logic gnt_o, + output logic gnt_o, /// Memory request to split, request address, byte-wise. - input addr_t addr_i, + input addr_t addr_i, /// Memory request to split, request write data. - input inp_data_t wdata_i, + input inp_data_t wdata_i, /// Memory request to split, request write strobe. - input inp_strb_t strb_i, + input inp_strb_t strb_i, /// Memory request to split, request sideband. - input wuser_t wuser_i, + input wuser_t wuser_i, /// Memory request to split, request write enable, active high. - input logic we_i, + input logic we_i, /// Memory request to split, response is valid. Required for read and write requests - output logic rvalid_o, + output logic rvalid_o, /// Memory request to split, response is ready. Required for read and write requests - input logic rready_i, + input logic rready_i, /// Memory request to split, response read data. - output inp_data_t rdata_o, + output inp_data_t rdata_o, /// Memory request to split, response sideband. - output inp_ruser_t ruser_o, + output inp_ruser_t ruser_o, /// Memory bank request, request is valid. - output logic [NumBanks-1:0] bank_req_o, + output logic [NumBanks-1:0] bank_req_o, /// Memory bank request, request can be granted. - input logic [NumBanks-1:0] bank_gnt_i, + input logic [NumBanks-1:0] bank_gnt_i, /// Memory bank request, request address, byte-wise. Will be different for each bank. - output addr_t [NumBanks-1:0] bank_addr_o, + output addr_t [NumBanks-1:0] bank_addr_o, /// Memory bank request, request write data. - output oup_data_t [NumBanks-1:0] bank_wdata_o, + output oup_data_t [NumBanks-1:0] bank_wdata_o, /// Memory bank request, request write strobe. - output oup_strb_t [NumBanks-1:0] bank_strb_o, + output oup_strb_t [NumBanks-1:0] bank_strb_o, /// Memory bank request, request sideband. - output wuser_t [NumBanks-1:0] bank_wuser_o, + output wuser_t [NumBanks-1:0] bank_wuser_o, /// Memory bank request, request write enable, active high. - output logic [NumBanks-1:0] bank_we_o, + output logic [NumBanks-1:0] bank_we_o, /// Memory bank request, response is valid. Required for read and write requests - input logic [NumBanks-1:0] bank_rvalid_i, + input logic [NumBanks-1:0] bank_rvalid_i, /// Memory bank request, response read data. - input oup_data_t [NumBanks-1:0] bank_rdata_i, + input oup_data_t [NumBanks-1:0] bank_rdata_i, /// Memory bank request, response sideband. - input oup_ruser_t [NumBanks-1:0] bank_ruser_i + input oup_ruser_t [NumBanks-1:0] bank_ruser_i ); - localparam int unsigned DataBytes = $bits(inp_strb_t); - localparam int unsigned BitsPerBank = $bits(oup_data_t); + localparam int unsigned DataBytes = $bits(inp_strb_t); + localparam int unsigned BitsPerBank = $bits(oup_data_t); localparam int unsigned BytesPerBank = $bits(oup_strb_t); typedef struct packed { @@ -106,17 +106,12 @@ module stream_mem_to_banks_det #( logic we; } req_t; - logic req_valid; - logic [NumBanks-1:0] req_ready, - resp_valid, resp_ready; - req_t [NumBanks-1:0] bank_req, - bank_oup; - logic [NumBanks-1:0] bank_req_internal, - bank_gnt_internal, - zero_strobe, - dead_response, - dead_response_unmasked; - logic dead_write_fifo_full, dead_write_fifo_empty; + logic req_valid; + logic [NumBanks-1:0] req_ready, resp_valid, resp_ready; + req_t [NumBanks-1:0] bank_req, bank_oup; + logic [NumBanks-1:0] + bank_req_internal, bank_gnt_internal, zero_strobe, dead_response, dead_response_unmasked; + logic dead_write_fifo_full, dead_write_fifo_empty; function automatic addr_t align_addr(input addr_t addr); return (addr >> $clog2(DataBytes)) << $clog2(DataBytes); @@ -131,22 +126,22 @@ module stream_mem_to_banks_det #( assign bank_req[i].wuser = wuser_i; assign bank_req[i].we = we_i; stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DATA_WIDTH ( $bits(req_t) ), - .DEPTH ( FifoDepth ), - .T ( req_t ) + .FALL_THROUGH(1'b1), + .DATA_WIDTH ($bits(req_t)), + .DEPTH (FifoDepth), + .T (req_t) ) i_ft_reg ( .clk_i, .rst_ni, - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .usage_o (), - .data_i ( bank_req[i] ), - .valid_i ( req_valid ), - .ready_o ( req_ready[i] ), - .data_o ( bank_oup[i] ), - .valid_o ( bank_req_internal[i] ), - .ready_i ( bank_gnt_internal[i] ) + .flush_i (1'b0), + .testmode_i(1'b0), + .usage_o (), + .data_i (bank_req[i]), + .valid_i (req_valid), + .ready_o (req_ready[i]), + .data_o (bank_oup[i]), + .valid_o (bank_req_internal[i]), + .ready_i (bank_gnt_internal[i]) ); assign bank_addr_o[i] = bank_oup[i].addr; assign bank_wdata_o[i] = bank_oup[i].wdata; @@ -154,7 +149,7 @@ module stream_mem_to_banks_det #( assign bank_wuser_o[i] = bank_oup[i].wuser; assign bank_we_o[i] = bank_oup[i].we; - assign zero_strobe[i] = (|bank_req[i].strb == '0); + assign zero_strobe[i] = (|bank_req[i].strb == '0); if (HideStrb) begin : gen_hide_strb assign bank_req_o[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? @@ -162,7 +157,7 @@ module stream_mem_to_banks_det #( assign bank_gnt_internal[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? 1'b1 : bank_gnt_i[i]; end else begin : gen_legacy_strb - assign bank_req_o[i] = bank_req_internal[i]; + assign bank_req_o[i] = bank_req_internal[i]; assign bank_gnt_internal[i] = bank_gnt_i[i]; end end @@ -172,65 +167,65 @@ module stream_mem_to_banks_det #( if (HideStrb) begin : gen_dead_write_fifo fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MaxTrans+1 ), - .DATA_WIDTH ( NumBanks ) + .FALL_THROUGH(1'b0), + .DEPTH (MaxTrans + 1), + .DATA_WIDTH (NumBanks) ) i_dead_write_fifo ( .clk_i, .rst_ni, - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .full_o ( dead_write_fifo_full ), - .empty_o ( dead_write_fifo_empty ), - .usage_o (), - .data_i ( {NumBanks{we_i}} & zero_strobe ), - .push_i ( req_i & gnt_o ), - .data_o ( dead_response_unmasked ), - .pop_i ( rvalid_o & rready_i ) + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (dead_write_fifo_full), + .empty_o (dead_write_fifo_empty), + .usage_o (), + .data_i ({NumBanks{we_i}} & zero_strobe), + .push_i (req_i & gnt_o), + .data_o (dead_response_unmasked), + .pop_i (rvalid_o & rready_i) ); assign dead_response = dead_response_unmasked & {NumBanks{~dead_write_fifo_empty}}; end else begin : gen_no_dead_write_fifo assign dead_response_unmasked = '0; - assign dead_response = '0; - assign dead_write_fifo_full = 1'b0; - assign dead_write_fifo_empty = 1'b1; + assign dead_response = '0; + assign dead_write_fifo_full = 1'b0; + assign dead_write_fifo_empty = 1'b1; end // Handle responses. for (genvar i = 0; unsigned'(i) < NumBanks; i++) begin : gen_resp_regs stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DATA_WIDTH ( $bits(oup_data_t) + $bits(oup_ruser_t) ), - .DEPTH ( FifoDepth ) + .FALL_THROUGH(1'b1), + .DATA_WIDTH ($bits(oup_data_t) + $bits(oup_ruser_t)), + .DEPTH (FifoDepth) ) i_ft_reg ( .clk_i, .rst_ni, - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .usage_o (), - .data_i ( {bank_rdata_i[i], bank_ruser_i[i]} ), - .valid_i ( bank_rvalid_i[i] ), - .ready_o ( resp_ready[i] ), - .data_o ( {rdata_o[i*BitsPerBank+:BitsPerBank], ruser_o[i]} ), - .valid_o ( resp_valid[i] ), - .ready_i ( rvalid_o & rready_i & !dead_response[i] ) + .flush_i (1'b0), + .testmode_i(1'b0), + .usage_o (), + .data_i ({bank_rdata_i[i], bank_ruser_i[i]}), + .valid_i (bank_rvalid_i[i]), + .ready_o (resp_ready[i]), + .data_o ({rdata_o[i*BitsPerBank+:BitsPerBank], ruser_o[i]}), + .valid_o (resp_valid[i]), + .ready_i (rvalid_o & rready_i & !dead_response[i]) ); end assign rvalid_o = &(resp_valid | dead_response); // Assertions // pragma translate_off - `ifndef VERILATOR - `ifndef SYNTHESIS - initial begin - assume (DataWidth != 0 && (DataWidth & (DataWidth - 1)) == 0) - else $fatal(1, "Data width must be a power of two!"); - assume (DataWidth % NumBanks == 0) - else $fatal(1, "Data width must be evenly divisible over banks!"); - assume ((DataWidth / NumBanks) % 8 == 0) - else $fatal(1, "Data width of each bank must be divisible into 8-bit bytes!"); - end - `endif - `endif +`ifndef VERILATOR +`ifndef SYNTHESIS + initial begin + assume (DataWidth != 0 && (DataWidth & (DataWidth - 1)) == 0) + else $fatal(1, "Data width must be a power of two!"); + assume (DataWidth % NumBanks == 0) + else $fatal(1, "Data width must be evenly divisible over banks!"); + assume ((DataWidth / NumBanks) % 8 == 0) + else $fatal(1, "Data width of each bank must be divisible into 8-bit bytes!"); + end +`endif +`endif // pragma translate_on endmodule diff --git a/src/varlat_inorder_interco.sv b/src/varlat_inorder_interco.sv index 3bf62c0..57a0fda 100644 --- a/src/varlat_inorder_interco.sv +++ b/src/varlat_inorder_interco.sv @@ -8,37 +8,37 @@ module varlat_inorder_interco #( /////////////////////////// // global parameters /// number of initiator ports (must be aligned with power of 2 for bfly and clos) - parameter int unsigned NumIn = 32, + parameter int unsigned NumIn = 32, /// number of TCDM banks (must be aligned with power of 2 for bfly and clos) - parameter int unsigned NumOut = 64, + parameter int unsigned NumOut = 64, /// address width on initiator side - parameter int unsigned AddrWidth = 32, + parameter int unsigned AddrWidth = 32, /// word width of data - parameter int unsigned DataWidth = 32, + parameter int unsigned DataWidth = 32, /// width of corresponding byte enables - parameter int unsigned BeWidth = DataWidth/8, + parameter int unsigned BeWidth = DataWidth / 8, /// number of address bits per TCDM bank - parameter int unsigned AddrMemWidth = 12, + parameter int unsigned AddrMemWidth = 12, /// defines whether the interconnect returns a write response - parameter bit WriteRespOn = 1, + parameter bit WriteRespOn = 1, /// Number of outstanding requests supported - parameter int unsigned NumOutstanding = 1, + parameter int unsigned NumOutstanding = 1, /// determines the width of the byte offset in a memory word. normally this can be left at the /// default vaule, but sometimes it needs to be overridden (e.g. when meta-data is supplied to /// the memory via the wdata signal). - parameter int unsigned ByteOffWidth = $clog2(DataWidth-1)-3, + parameter int unsigned ByteOffWidth = $clog2(DataWidth - 1) - 3, /// topology can be: LIC, BFLY2, BFLY4, CLOS - parameter tcdm_interconnect_pkg::topo_e Topology = tcdm_interconnect_pkg::LIC, + parameter tcdm_interconnect_pkg::topo_e Topology = tcdm_interconnect_pkg::LIC, /// number of parallel butterfly's to use, only relevant for BFLY topologies - parameter int unsigned NumPar = 1, + parameter int unsigned NumPar = 1, /// this detemines which Clos config to use, only relevant for CLOS topologies /// 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n - parameter int unsigned ClosConfig = 2 + parameter int unsigned ClosConfig = 2 /////////////////////////// ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, /// master side /// request signal input logic [ NumIn-1:0] req_i, @@ -77,23 +77,24 @@ module varlat_inorder_interco #( input logic [NumOut-1:0][ DataWidth-1:0] rdata_i ); - localparam int unsigned NumOutLog2 = $clog2(NumOut); - localparam int unsigned NumInLog2 = $clog2(NumIn); - localparam int unsigned AggDataWidth = 1+BeWidth+AddrMemWidth+DataWidth; + localparam int unsigned NumOutLog2 = $clog2(NumOut); + localparam int unsigned NumInLog2 = $clog2(NumIn); + localparam int unsigned AggDataWidth = 1 + BeWidth + AddrMemWidth + DataWidth; logic [ NumIn-1:0][AggDataWidth-1:0] data_agg_in; logic [NumOut-1:0][AggDataWidth-1:0] data_agg_out; - logic [ NumIn-1:0][ NumOutLog2-1:0] bank_sel, bank_sel_rsp; - logic [NumOut-1:0][ NumInLog2-1:0] ini_addr_req, ini_addr_rsp; + logic [NumIn-1:0][NumOutLog2-1:0] bank_sel, bank_sel_rsp; + logic [NumOut-1:0][NumInLog2-1:0] ini_addr_req, ini_addr_rsp; for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs // extract bank index assign bank_sel[j] = add_i[j][ByteOffWidth+NumOutLog2-1:ByteOffWidth]; // aggregate data to be routed to slaves - assign data_agg_in[j] = {we_i[j], - be_i[j], - add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1: - ByteOffWidth+NumOutLog2], - wdata_i[j]}; + assign data_agg_in[j] = { + we_i[j], + be_i[j], + add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1:ByteOffWidth+NumOutLog2], + wdata_i[j] + }; end // disaggregate data @@ -103,35 +104,35 @@ module varlat_inorder_interco #( if (Topology == tcdm_interconnect_pkg::LIC) begin : gen_lic - logic [ NumIn-1:0] xbar_gnt, fifo_gnt, fifo_gnt_n; + logic [NumIn-1:0] xbar_gnt, fifo_gnt, fifo_gnt_n; logic [NumOut-1:0] out_fifo_gnt, out_fifo_gnt_n; - assign fifo_gnt = ~fifo_gnt_n; - assign gnt_o = xbar_gnt & fifo_gnt; + assign fifo_gnt = ~fifo_gnt_n; + assign gnt_o = xbar_gnt & fifo_gnt; assign out_fifo_gnt = ~out_fifo_gnt_n; // Request path simplex_xbar #( - .NumIn ( NumIn ), - .NumOut ( NumOut ), - .DataWidth ( AggDataWidth ), - .ExtPrio ( 1'b0 ), - .AxiVldRdy ( 1'b1 ), - .SpillRegister ( 1'b0 ), - .FallThroughRegister ( 1'b0 ) + .NumIn (NumIn), + .NumOut (NumOut), + .DataWidth (AggDataWidth), + .ExtPrio (1'b0), + .AxiVldRdy (1'b1), + .SpillRegister (1'b0), + .FallThroughRegister(1'b0) ) req_xbar ( .clk_i, .rst_ni, - .rr_i ( '0 ), - .valid_i ( req_i & fifo_gnt ), - .ready_o ( xbar_gnt ), - .tgt_addr_i ( bank_sel ), - .data_i ( data_agg_in ), - .valid_o ( req_o ), - .ini_addr_o ( ini_addr_req ), - .ready_i ( gnt_i & out_fifo_gnt ), - .data_o ( data_agg_out ) + .rr_i ('0), + .valid_i (req_i & fifo_gnt), + .ready_o (xbar_gnt), + .tgt_addr_i(bank_sel), + .data_i (data_agg_in), + .valid_o (req_o), + .ini_addr_o(ini_addr_req), + .ready_i (gnt_i & out_fifo_gnt), + .data_o (data_agg_out) ); // Response path @@ -147,9 +148,9 @@ module varlat_inorder_interco #( for (genvar i = 0; i < NumIn; i++) begin : gen_rsp_port_match fifo_v3 #( - .FALL_THROUGH( 1'b0 ), // expect at least 1 cycle latency - .DATA_WIDTH ( NumOutLog2 ), - .DEPTH ( NumOutstanding ) + .FALL_THROUGH(1'b0), // expect at least 1 cycle latency + .DATA_WIDTH (NumOutLog2), + .DEPTH (NumOutstanding) ) i_bank_sel ( .clk_i, .rst_ni, @@ -157,23 +158,23 @@ module varlat_inorder_interco #( .flush_i ('0), .testmode_i('0), - .full_o ( fifo_gnt_n[i] ), - .empty_o (), - .usage_o (), + .full_o (fifo_gnt_n[i]), + .empty_o(), + .usage_o(), - .data_i ( bank_sel[i] ), - .push_i ( req_i[i] & gnt_o[i] ), + .data_i(bank_sel[i]), + .push_i(req_i[i] & gnt_o[i]), - .data_o ( bank_sel_rsp[i] ), - .pop_i ( vld_o[i] ) + .data_o(bank_sel_rsp[i]), + .pop_i (vld_o[i]) ); end for (genvar i = 0; i < NumOut; i++) begin : gen_out_fifo fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), // expect at least 1 cycle latency - .DATA_WIDTH ( NumInLog2 ), - .DEPTH ( NumOutstanding ) + .FALL_THROUGH(1'b0), // expect at least 1 cycle latency + .DATA_WIDTH (NumInLog2), + .DEPTH (NumOutstanding) ) i_ini_sel ( .clk_i, .rst_ni, @@ -181,15 +182,15 @@ module varlat_inorder_interco #( .flush_i ('0), .testmode_i('0), - .full_o ( out_fifo_gnt_n[i] ), - .empty_o (), - .usage_o (), + .full_o (out_fifo_gnt_n[i]), + .empty_o(), + .usage_o(), - .data_i ( ini_addr_req[i] ), - .push_i ( req_o[i] & gnt_i[i] & out_fifo_gnt[i] ), + .data_i(ini_addr_req[i]), + .push_i(req_o[i] & gnt_i[i] & out_fifo_gnt[i]), - .data_o ( ini_addr_rsp[i] ), - .pop_i ( rvalid_i[i] & rready_o[i] ) + .data_o(ini_addr_rsp[i]), + .pop_i (rvalid_i[i] & rready_o[i]) ); end end else begin : gen_fail diff --git a/test/axi_memory_island_tb.sv b/test/axi_memory_island_tb.sv index 30335a5..ece4372 100644 --- a/test/axi_memory_island_tb.sv +++ b/test/axi_memory_island_tb.sv @@ -8,30 +8,30 @@ `include "axi/assign.svh" module axi_memory_island_tb #( - parameter int unsigned AddrWidth = 32, + parameter int unsigned AddrWidth = 32, parameter int unsigned NarrowDataWidth = 32, parameter int unsigned WideDataWidth = 512, - parameter int unsigned AxiIdWidth = 2, - parameter int unsigned AxiUserWidth = 1, - parameter int unsigned NumNarrowReq = 4, - parameter int unsigned NumWideReq = 2, - parameter int unsigned NumWideBanks = 8, - parameter int unsigned NarrowExtraBF = 2, - parameter int unsigned WordsPerBank = 512*NumNarrowReq*NumWideReq, - parameter int unsigned TbNumReads = 200, - parameter int unsigned TbNumWrites = 200 + parameter int unsigned AxiIdWidth = 2, + parameter int unsigned AxiUserWidth = 1, + parameter int unsigned NumNarrowReq = 4, + parameter int unsigned NumWideReq = 2, + parameter int unsigned NumWideBanks = 8, + parameter int unsigned NarrowExtraBF = 2, + parameter int unsigned WordsPerBank = 512 * NumNarrowReq * NumWideReq, + parameter int unsigned TbNumReads = 200, + parameter int unsigned TbNumWrites = 200 ) (); parameter time CyclTime = 10ns; parameter time ApplTime = 2ns; parameter time TestTime = 8ns; - localparam int unsigned TotalBytes = WordsPerBank*NumWideBanks*WideDataWidth/8; - localparam int unsigned UsableAddrWidth= $clog2(TotalBytes); + localparam int unsigned TotalBytes = WordsPerBank * NumWideBanks * WideDataWidth / 8; + localparam int unsigned UsableAddrWidth = $clog2(TotalBytes); - localparam int unsigned TotalReq = NumNarrowReq+NumWideReq; + localparam int unsigned TotalReq = NumNarrowReq + NumWideReq; - localparam int unsigned TxInFlight = 16; // pow2 + localparam int unsigned TxInFlight = 16; // pow2 logic clk, rst_n; @@ -41,7 +41,7 @@ module axi_memory_island_tb #( localparam int unsigned TestRegionStart = 0; - localparam int unsigned TestRegionEnd = 16384; + localparam int unsigned TestRegionEnd = 16384; // Clock/Reset generation clk_rst_gen #( @@ -53,65 +53,57 @@ module axi_memory_island_tb #( ); // Main AXI type definitions - `AXI_TYPEDEF_ALL(narrow, - logic[AddrWidth-1:0], - logic[AxiIdWidth-1:0], - logic[NarrowDataWidth-1:0], - logic[NarrowDataWidth/8-1:0], - logic[AxiUserWidth-1:0]) - `AXI_TYPEDEF_ALL(wide, - logic[AddrWidth-1:0], - logic[AxiIdWidth-1:0], - logic[WideDataWidth-1:0], - logic[WideDataWidth/8-1:0], - logic[AxiUserWidth-1:0]) + `AXI_TYPEDEF_ALL(narrow, logic[AddrWidth-1:0], logic[AxiIdWidth-1:0], logic[NarrowDataWidth-1:0], + logic[NarrowDataWidth/8-1:0], logic[AxiUserWidth-1:0]) + `AXI_TYPEDEF_ALL(wide, logic[AddrWidth-1:0], logic[AxiIdWidth-1:0], logic[WideDataWidth-1:0], + logic[WideDataWidth/8-1:0], logic[AxiUserWidth-1:0]) // Narrow Random Master config - typedef axi_test::axi_rand_master #( - .AW ( AddrWidth ), - .DW ( NarrowDataWidth ), - .IW ( AxiIdWidth ), - .UW ( AxiUserWidth ), + typedef axi_test::axi_rand_master#( + .AW (AddrWidth), + .DW (NarrowDataWidth), + .IW (AxiIdWidth), + .UW (AxiUserWidth), // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ), + .TA (ApplTime), + .TT (TestTime), // Maximum number of read and write transactions in flight - .MAX_READ_TXNS ( TxInFlight ), - .MAX_WRITE_TXNS ( TxInFlight ), - - .SIZE_ALIGN ( 0 ), - .AXI_MAX_BURST_LEN ( 0 ), // max - .TRAFFIC_SHAPING ( 0 ), - .AXI_EXCLS ( 1'b0 ), - .AXI_ATOPS ( 1'b0 ), - .AXI_BURST_FIXED ( 1'b0 ), - .AXI_BURST_INCR ( 1'b1 ), - .AXI_BURST_WRAP ( 1'b0 ), - .UNIQUE_IDS ( 1'b0 ) + .MAX_READ_TXNS (TxInFlight), + .MAX_WRITE_TXNS(TxInFlight), + + .SIZE_ALIGN (0), + .AXI_MAX_BURST_LEN(0), // max + .TRAFFIC_SHAPING (0), + .AXI_EXCLS (1'b0), + .AXI_ATOPS (1'b0), + .AXI_BURST_FIXED (1'b0), + .AXI_BURST_INCR (1'b1), + .AXI_BURST_WRAP (1'b0), + .UNIQUE_IDS (1'b0) ) narrow_axi_rand_master_t; // Wide Random Master config - typedef axi_test::axi_rand_master #( - .AW ( AddrWidth ), - .DW ( WideDataWidth ), - .IW ( AxiIdWidth ), - .UW ( AxiUserWidth ), + typedef axi_test::axi_rand_master#( + .AW (AddrWidth), + .DW (WideDataWidth), + .IW (AxiIdWidth), + .UW (AxiUserWidth), // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ), + .TA (ApplTime), + .TT (TestTime), // Maximum number of read and write transactions in flight - .MAX_READ_TXNS ( TxInFlight ), - .MAX_WRITE_TXNS ( TxInFlight ), - - .SIZE_ALIGN ( 0 ), - .AXI_MAX_BURST_LEN ( 0 ), // max - .TRAFFIC_SHAPING ( 0 ), - .AXI_EXCLS ( 1'b0 ), - .AXI_ATOPS ( 1'b0 ), - .AXI_BURST_FIXED ( 1'b0 ), - .AXI_BURST_INCR ( 1'b1 ), - .AXI_BURST_WRAP ( 1'b0 ), - .UNIQUE_IDS ( 1'b0 ) + .MAX_READ_TXNS (TxInFlight), + .MAX_WRITE_TXNS(TxInFlight), + + .SIZE_ALIGN (0), + .AXI_MAX_BURST_LEN(0), // max + .TRAFFIC_SHAPING (0), + .AXI_EXCLS (1'b0), + .AXI_ATOPS (1'b0), + .AXI_BURST_FIXED (1'b0), + .AXI_BURST_INCR (1'b1), + .AXI_BURST_WRAP (1'b0), + .UNIQUE_IDS (1'b0) ) wide_axi_rand_master_t; narrow_req_t [NumNarrowReq-1:0] axi_narrow_req; @@ -120,41 +112,45 @@ module axi_memory_island_tb #( wide_resp_t [ NumWideReq-1:0] axi_wide_rsp; AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AddrWidth ), - .AXI_DATA_WIDTH ( NarrowDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidth ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) axi_narrow_dv [NumNarrowReq-1:0] (clk); + .AXI_ADDR_WIDTH(AddrWidth), + .AXI_DATA_WIDTH(NarrowDataWidth), + .AXI_ID_WIDTH (AxiIdWidth), + .AXI_USER_WIDTH(AxiUserWidth) + ) axi_narrow_dv[NumNarrowReq-1:0] ( + clk + ); AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AddrWidth ), - .AXI_DATA_WIDTH ( WideDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidth ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) axi_wide_dv [NumWideReq-1:0] (clk); - - narrow_axi_rand_master_t narrow_rand_master [NumNarrowReq]; - wide_axi_rand_master_t wide_rand_master [NumWideReq]; - - narrow_req_t [NumNarrowReq-1:0] filtered_narrow_req; - narrow_resp_t [NumNarrowReq-1:0] filtered_narrow_rsp; - wide_req_t [ NumWideReq-1:0] filtered_wide_req; - wide_resp_t [ NumWideReq-1:0] filtered_wide_rsp; - - narrow_req_t [NumNarrowReq-1:0] filtered_narrow_req_cut; - narrow_resp_t [NumNarrowReq-1:0] filtered_narrow_rsp_cut; - wide_req_t [ NumWideReq-1:0] filtered_wide_req_cut; - wide_resp_t [ NumWideReq-1:0] filtered_wide_rsp_cut; - - narrow_req_t [NumNarrowReq-1:0] dut_narrow_req; - narrow_resp_t [NumNarrowReq-1:0] dut_narrow_rsp; - wide_req_t [ NumWideReq-1:0] dut_wide_req; - wide_resp_t [ NumWideReq-1:0] dut_wide_rsp; - - narrow_req_t [NumNarrowReq-1:0] golden_narrow_req; - narrow_resp_t [NumNarrowReq-1:0] golden_narrow_rsp; - wide_req_t [ NumWideReq-1:0] golden_wide_req; - wide_resp_t [ NumWideReq-1:0] golden_wide_rsp; + .AXI_ADDR_WIDTH(AddrWidth), + .AXI_DATA_WIDTH(WideDataWidth), + .AXI_ID_WIDTH (AxiIdWidth), + .AXI_USER_WIDTH(AxiUserWidth) + ) axi_wide_dv[NumWideReq-1:0] ( + clk + ); + + narrow_axi_rand_master_t narrow_rand_master [NumNarrowReq]; + wide_axi_rand_master_t wide_rand_master [ NumWideReq]; + + narrow_req_t [NumNarrowReq-1:0] filtered_narrow_req; + narrow_resp_t [NumNarrowReq-1:0] filtered_narrow_rsp; + wide_req_t [ NumWideReq-1:0] filtered_wide_req; + wide_resp_t [ NumWideReq-1:0] filtered_wide_rsp; + + narrow_req_t [NumNarrowReq-1:0] filtered_narrow_req_cut; + narrow_resp_t [NumNarrowReq-1:0] filtered_narrow_rsp_cut; + wide_req_t [ NumWideReq-1:0] filtered_wide_req_cut; + wide_resp_t [ NumWideReq-1:0] filtered_wide_rsp_cut; + + narrow_req_t [NumNarrowReq-1:0] dut_narrow_req; + narrow_resp_t [NumNarrowReq-1:0] dut_narrow_rsp; + wide_req_t [ NumWideReq-1:0] dut_wide_req; + wide_resp_t [ NumWideReq-1:0] dut_wide_rsp; + + narrow_req_t [NumNarrowReq-1:0] golden_narrow_req; + narrow_resp_t [NumNarrowReq-1:0] golden_narrow_rsp; + wide_req_t [ NumWideReq-1:0] golden_wide_req; + wide_resp_t [ NumWideReq-1:0] golden_wide_rsp; // Filter reads to regions being written // Filter writes to regions being read @@ -163,12 +159,12 @@ module axi_memory_island_tb #( logic [AddrWidth-1:0] end_addr; } addr_range_t; - logic [TotalReq-1:0] blocking_write; - logic [TotalReq-1:0] blocking_read; + logic [TotalReq-1:0] blocking_write; + logic [TotalReq-1:0] blocking_read; // Address range queues to avoid writes interfering with reads or other writes - addr_range_t regions_being_read [TotalReq][2**AxiIdWidth][$]; - addr_range_t regions_being_written [TotalReq][2**AxiIdWidth][$]; + addr_range_t regions_being_read [TotalReq][2**AxiIdWidth][$]; + addr_range_t regions_being_written[TotalReq][2**AxiIdWidth][$]; // Overlap if !(b.end < a.start || b.start > a.end) function automatic logic check_overlap(addr_range_t range_a, addr_range_t range_b); @@ -179,12 +175,12 @@ module axi_memory_island_tb #( addr_range_t [TotalReq-1:0] tmp_read, tmp_write; int read_len [TotalReq][2**AxiIdWidth]; - int write_len [TotalReq][2**AxiIdWidth]; + int write_len[TotalReq][2**AxiIdWidth]; // Get sizes for debug purposes for (genvar i = 0; i < TotalReq; i++) begin : gen_len_req - for (genvar j = 0; j < 2**AxiIdWidth; j++) begin : gen_len_axi_id - assign read_len[i][j] = $size(regions_being_read[i][j]); + for (genvar j = 0; j < 2 ** AxiIdWidth; j++) begin : gen_len_axi_id + assign read_len[i][j] = $size(regions_being_read[i][j]); assign write_len[i][j] = $size(regions_being_written[i][j]); end end @@ -194,13 +190,11 @@ module axi_memory_island_tb #( logic [TotalReq-1:0] aw_hs, ar_hs; - logic [TotalReq-1:0][TotalReq-1:0][2**AxiIdWidth-1:0][TxInFlight-1:0] write_overlapping_write, - write_overlapping_read, - read_overlapping_write; + logic [TotalReq-1:0][TotalReq-1:0][2**AxiIdWidth-1:0][TxInFlight-1:0] + write_overlapping_write, write_overlapping_read, read_overlapping_write; - logic [TotalReq-1:0][TotalReq-1:0] live_write_overlapping_write, - live_write_overlapping_read, - live_read_overlapping_write; + logic [TotalReq-1:0][TotalReq-1:0] + live_write_overlapping_write, live_write_overlapping_read, live_read_overlapping_write; for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_stim `AXI_ASSIGN_TO_REQ(axi_narrow_req[i], axi_narrow_dv[i]) @@ -208,18 +202,17 @@ module axi_memory_island_tb #( // Stimuli Generation initial begin - narrow_rand_master[i] = new( axi_narrow_dv[i] ); + narrow_rand_master[i] = new(axi_narrow_dv[i]); random_mem_filled[i] <= 1'b0; - end_of_sim[i] <= 1'b0; + end_of_sim[i] <= 1'b0; // Allow all of MemoryIsland space - narrow_rand_master[i].add_memory_region(TestRegionStart, - TestRegionEnd, + narrow_rand_master[i].add_memory_region(TestRegionStart, TestRegionEnd, axi_pkg::DEVICE_NONBUFFERABLE); narrow_rand_master[i].reset(); @(posedge rst_n); narrow_rand_master[i].run(0, TbNumWrites); random_mem_filled[i] <= 1'b1; - wait(&random_mem_filled); + wait (&random_mem_filled); narrow_rand_master[i].run(TbNumReads, TbNumWrites); end_of_sim[i] <= 1'b1; end @@ -230,7 +223,7 @@ module axi_memory_island_tb #( assign write_range[i].start_addr = axi_narrow_req[i].aw.addr; assign write_range[i].end_addr = axi_narrow_req[i].aw.addr + ((2**axi_narrow_req[i].aw.size)*(axi_narrow_req[i].aw.len+1)); - assign read_range[i].start_addr = axi_narrow_req[i].ar.addr; + assign read_range[i].start_addr = axi_narrow_req[i].ar.addr; assign read_range[i].end_addr = axi_narrow_req[i].ar.addr + ((2**axi_narrow_req[i].ar.size)*(axi_narrow_req[i].ar.len+1)); @@ -239,7 +232,7 @@ module axi_memory_island_tb #( // Store in-flight address ranges into a queue always @(posedge clk) begin - for (int id = 0; id < 2**AxiIdWidth; id++) begin + for (int id = 0; id < 2 ** AxiIdWidth; id++) begin // push write queue on actual AW if (aw_hs[i] && axi_narrow_req[i].aw.id == id) begin regions_being_written[i][id].push_back(write_range[i]); @@ -267,28 +260,37 @@ module axi_memory_island_tb #( end for (genvar requestIdx = 0; requestIdx < TotalReq; requestIdx++) begin : gen_overlap_check_reqs - for (genvar axiIdx = 0; axiIdx < 2**AxiIdWidth; axiIdx++) begin : gen_overlap_check_ids + for (genvar axiIdx = 0; axiIdx < 2 ** AxiIdWidth; axiIdx++) begin : gen_overlap_check_ids for (genvar txIdx = 0; txIdx < TxInFlight; txIdx++) begin : gen_overlap_check_txns // Block write if overlapping region is already being written assign write_overlapping_write[i][requestIdx][axiIdx][txIdx] = txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(write_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; + check_overlap( + write_range[i], regions_being_written[requestIdx][axiIdx][txIdx] + ) : '0; // Block reads if overlapping region is already being written assign read_overlapping_write[i][requestIdx][axiIdx][txIdx] = txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(read_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; + check_overlap( + read_range[i], regions_being_written[requestIdx][axiIdx][txIdx] + ) : '0; // Block write if overlapping region is already being read assign write_overlapping_read[i][requestIdx][axiIdx][txIdx] = txIdx < read_len[requestIdx][axiIdx] ? - check_overlap(write_range[i], regions_being_read[requestIdx][axiIdx][txIdx]) : '0; + check_overlap( + write_range[i], regions_being_read[requestIdx][axiIdx][txIdx] + ) : '0; end end - assign live_write_overlapping_write[i][requestIdx] = - check_overlap(write_range[i], write_range[requestIdx]); - assign live_write_overlapping_read[i][requestIdx] = - check_overlap(write_range[i], read_range[requestIdx]); - assign live_read_overlapping_write[i][requestIdx] = - check_overlap(read_range[i], write_range[requestIdx]); + assign live_write_overlapping_write[i][requestIdx] = check_overlap( + write_range[i], write_range[requestIdx] + ); + assign live_write_overlapping_read[i][requestIdx] = check_overlap( + write_range[i], read_range[requestIdx] + ); + assign live_read_overlapping_write[i][requestIdx] = check_overlap( + read_range[i], write_range[requestIdx] + ); end always_comb begin : proc_filter_narrow @@ -296,15 +298,15 @@ module axi_memory_island_tb #( `AXI_SET_REQ_STRUCT(filtered_narrow_req[i], axi_narrow_req[i]) `AXI_SET_RESP_STRUCT(axi_narrow_rsp[i], filtered_narrow_rsp[i]) blocking_write[i] = '0; - blocking_read[i] = '0; + blocking_read[i] = '0; // Block writes if necessary if (axi_narrow_req[i].aw_valid && filtered_narrow_rsp[i].aw_ready) begin // check in-flight requests if (|write_overlapping_write[i] || |write_overlapping_read[i]) begin filtered_narrow_req[i].aw_valid = 1'b0; - axi_narrow_rsp[i].aw_ready = 1'b0; - blocking_write[i] = 1'b1; + axi_narrow_rsp[i].aw_ready = 1'b0; + blocking_write[i] = 1'b1; end // check other ports for (int j = 0; j < i; j++) begin @@ -312,26 +314,26 @@ module axi_memory_island_tb #( if ( (live_write_overlapping_write[i][j] && aw_hs[j]) || (live_write_overlapping_read [i][j] && ar_hs[j]) ) begin filtered_narrow_req[i].aw_valid = 1'b0; - axi_narrow_rsp[i].aw_ready = 1'b0; - blocking_write[i] = 1'b1; + axi_narrow_rsp[i].aw_ready = 1'b0; + blocking_write[i] = 1'b1; end end end // Block reads if necessary if (axi_narrow_req[i].ar_valid && filtered_narrow_rsp[i].ar_ready) begin // check in-flight requests - if ( |read_overlapping_write[i] ) begin + if (|read_overlapping_write[i]) begin filtered_narrow_req[i].ar_valid = 1'b0; - axi_narrow_rsp[i].ar_ready = 1'b0; - blocking_read[i] = 1'b1; + axi_narrow_rsp[i].ar_ready = 1'b0; + blocking_read[i] = 1'b1; end // check other ports for (int j = 0; j <= i; j++) begin // Block read if overlapping region is starting to be written by lower or same ID - if ( (live_write_overlapping_write[i][j] && aw_hs[j]) ) begin + if ((live_write_overlapping_write[i][j] && aw_hs[j])) begin filtered_narrow_req[i].ar_valid = 1'b0; - axi_narrow_rsp[i].ar_ready = 1'b0; - blocking_read[i] = 1'b1; + axi_narrow_rsp[i].ar_ready = 1'b0; + blocking_read[i] = 1'b1; end end end @@ -341,45 +343,45 @@ module axi_memory_island_tb #( for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_check // Cut for TB logic loop axi_cut #( - .aw_chan_t ( narrow_aw_chan_t ), - .w_chan_t ( narrow_w_chan_t ), - .b_chan_t ( narrow_b_chan_t ), - .ar_chan_t ( narrow_ar_chan_t ), - .r_chan_t ( narrow_r_chan_t ), - .axi_req_t ( narrow_req_t ), - .axi_resp_t( narrow_resp_t ) + .aw_chan_t (narrow_aw_chan_t), + .w_chan_t (narrow_w_chan_t), + .b_chan_t (narrow_b_chan_t), + .ar_chan_t (narrow_ar_chan_t), + .r_chan_t (narrow_r_chan_t), + .axi_req_t (narrow_req_t), + .axi_resp_t(narrow_resp_t) ) i_cut_filtered_narrow ( .clk_i (clk), .rst_ni (rst_n), - .slv_req_i ( filtered_narrow_req[i] ), - .slv_resp_o( filtered_narrow_rsp[i] ), - .mst_req_o ( filtered_narrow_req_cut[i] ), - .mst_resp_i( filtered_narrow_rsp_cut[i] ) + .slv_req_i (filtered_narrow_req[i]), + .slv_resp_o(filtered_narrow_rsp[i]), + .mst_req_o (filtered_narrow_req_cut[i]), + .mst_resp_i(filtered_narrow_rsp_cut[i]) ); // Test axi_slave_compare #( - .AxiIdWidth ( AxiIdWidth ), - .FifoDepth ( 32 ), - .UseSize ( 1'b1 ), - .DataWidth ( NarrowDataWidth ), - .axi_aw_chan_t( narrow_aw_chan_t ), - .axi_w_chan_t ( narrow_w_chan_t ), - .axi_b_chan_t ( narrow_b_chan_t ), - .axi_ar_chan_t( narrow_ar_chan_t ), - .axi_r_chan_t ( narrow_r_chan_t ), - .axi_req_t ( narrow_req_t ), - .axi_rsp_t ( narrow_resp_t ) + .AxiIdWidth (AxiIdWidth), + .FifoDepth (32), + .UseSize (1'b1), + .DataWidth (NarrowDataWidth), + .axi_aw_chan_t(narrow_aw_chan_t), + .axi_w_chan_t (narrow_w_chan_t), + .axi_b_chan_t (narrow_b_chan_t), + .axi_ar_chan_t(narrow_ar_chan_t), + .axi_r_chan_t (narrow_r_chan_t), + .axi_req_t (narrow_req_t), + .axi_rsp_t (narrow_resp_t) ) i_narrow_compare ( - .clk_i ( clk ), + .clk_i (clk), .rst_ni (rst_n), - .testmode_i ('0 ), - .axi_mst_req_i ( filtered_narrow_req_cut[i] ), - .axi_mst_rsp_o ( filtered_narrow_rsp_cut[i] ), - .axi_ref_req_o ( dut_narrow_req [i] ), // bus_compare a - .axi_ref_rsp_i ( dut_narrow_rsp [i] ), // bus_compare a - .axi_test_req_o( golden_narrow_req[i] ), // bus_compare b - .axi_test_rsp_i( golden_narrow_rsp[i] ), // bus_compare b + .testmode_i ('0), + .axi_mst_req_i (filtered_narrow_req_cut[i]), + .axi_mst_rsp_o (filtered_narrow_rsp_cut[i]), + .axi_ref_req_o (dut_narrow_req[i]), // bus_compare a + .axi_ref_rsp_i (dut_narrow_rsp[i]), // bus_compare a + .axi_test_req_o(golden_narrow_req[i]), // bus_compare b + .axi_test_rsp_i(golden_narrow_rsp[i]), // bus_compare b .aw_mismatch_o (), .w_mismatch_o (), .b_mismatch_o (), @@ -396,29 +398,28 @@ module axi_memory_island_tb #( // Stimuli Generation initial begin - wide_rand_master[i] = new( axi_wide_dv[i] ); + wide_rand_master[i] = new(axi_wide_dv[i]); random_mem_filled[NumNarrowReq+i] <= 1'b0; - end_of_sim[NumNarrowReq+i] <= 1'b0; - wide_rand_master[i].add_memory_region(TestRegionStart, - TestRegionEnd, + end_of_sim[NumNarrowReq+i] <= 1'b0; + wide_rand_master[i].add_memory_region(TestRegionStart, TestRegionEnd, axi_pkg::DEVICE_NONBUFFERABLE); wide_rand_master[i].reset(); @(posedge rst_n); wide_rand_master[i].run(0, TbNumWrites); random_mem_filled[NumNarrowReq+i] <= 1'b1; - wait(&random_mem_filled); + wait (&random_mem_filled); wide_rand_master[i].run(TbNumReads, TbNumWrites); end_of_sim[NumNarrowReq+i] <= 1'b1; end end for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_limiting - localparam int unsigned ReqIdx = NumNarrowReq+i; + localparam int unsigned ReqIdx = NumNarrowReq + i; // Log address ranges of the requests assign write_range[ReqIdx].start_addr = axi_wide_req[i].aw.addr; assign write_range[ReqIdx].end_addr = axi_wide_req[i].aw.addr + ((2**axi_wide_req[i].aw.size)*(axi_wide_req[i].aw.len+1)); - assign read_range[ReqIdx].start_addr = axi_wide_req[i].ar.addr; + assign read_range[ReqIdx].start_addr = axi_wide_req[i].ar.addr; assign read_range[ReqIdx].end_addr = axi_wide_req[i].ar.addr + ((2**axi_wide_req[i].ar.size)*(axi_wide_req[i].ar.len+1)); @@ -446,31 +447,37 @@ module axi_memory_island_tb #( end for (genvar requestIdx = 0; requestIdx < TotalReq; requestIdx++) begin : gen_overlap_check_reqs - for (genvar axiIdx = 0; axiIdx < 2**AxiIdWidth; axiIdx++) begin : gen_overlap_check_ids - for (genvar txIdx = 0; txIdx < TxInFlight; txIdx++) begin : gen_overlap_check_txns + for (genvar axiIdx = 0; axiIdx < 2 ** AxiIdWidth; axiIdx++) begin : gen_overlap_check_ids + for (genvar txIdx = 0; txIdx < TxInFlight; txIdx++) begin : gen_overlap_check_txns // Block write if overlapping region is already being written assign write_overlapping_write[ReqIdx][requestIdx][axiIdx][txIdx] = txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(write_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx]): - '0; + check_overlap( + write_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx] + ) : '0; // Block reads if overlapping region is already being written assign read_overlapping_write[ReqIdx][requestIdx][axiIdx][txIdx] = txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(read_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx]): - '0; + check_overlap( + read_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx] + ) : '0; // Block write if overlapping region is already being read assign write_overlapping_read[ReqIdx][requestIdx][axiIdx][txIdx] = txIdx < read_len[requestIdx][axiIdx] ? - check_overlap(write_range[ReqIdx], regions_being_read[requestIdx][axiIdx][txIdx]): - '0; + check_overlap( + write_range[ReqIdx], regions_being_read[requestIdx][axiIdx][txIdx] + ) : '0; end end - assign live_write_overlapping_write[ReqIdx][requestIdx] = - check_overlap(write_range[ReqIdx], write_range[requestIdx]); - assign live_write_overlapping_read[ReqIdx][requestIdx] = - check_overlap(write_range[ReqIdx], read_range[requestIdx]); - assign live_read_overlapping_write[ReqIdx][requestIdx] = - check_overlap(read_range[ReqIdx], write_range[requestIdx]); + assign live_write_overlapping_write[ReqIdx][requestIdx] = check_overlap( + write_range[ReqIdx], write_range[requestIdx] + ); + assign live_write_overlapping_read[ReqIdx][requestIdx] = check_overlap( + write_range[ReqIdx], read_range[requestIdx] + ); + assign live_read_overlapping_write[ReqIdx][requestIdx] = check_overlap( + read_range[ReqIdx], write_range[requestIdx] + ); end always_comb begin : proc_filter_wide @@ -478,15 +485,15 @@ module axi_memory_island_tb #( `AXI_SET_REQ_STRUCT(filtered_wide_req[i], axi_wide_req[i]) `AXI_SET_RESP_STRUCT(axi_wide_rsp[i], filtered_wide_rsp[i]) blocking_write[ReqIdx] = '0; - blocking_read[ReqIdx] = '0; + blocking_read[ReqIdx] = '0; // Block writes if necessary if (axi_wide_req[i].aw_valid && filtered_wide_rsp[i].aw_ready) begin // check in-flight requests if (|write_overlapping_write[ReqIdx] || |write_overlapping_read[ReqIdx]) begin filtered_wide_req[i].aw_valid = 1'b0; - axi_wide_rsp[i].aw_ready = 1'b0; - blocking_write[ReqIdx] = 1'b1; + axi_wide_rsp[i].aw_ready = 1'b0; + blocking_write[ReqIdx] = 1'b1; end // check other ports for (int j = 0; j < ReqIdx; j++) begin @@ -494,26 +501,26 @@ module axi_memory_island_tb #( if ( (live_write_overlapping_write[ReqIdx][j] && aw_hs[j]) || (live_write_overlapping_read [ReqIdx][j] && ar_hs[j]) ) begin filtered_wide_req[i].aw_valid = 1'b0; - axi_wide_rsp[i].aw_ready = 1'b0; - blocking_write[ReqIdx] = 1'b1; + axi_wide_rsp[i].aw_ready = 1'b0; + blocking_write[ReqIdx] = 1'b1; end end end // Block reads if necessary if (axi_wide_req[i].ar_valid && filtered_wide_rsp[i].ar_ready) begin // check in-flight requests - if ( |read_overlapping_write[ReqIdx] ) begin + if (|read_overlapping_write[ReqIdx]) begin filtered_wide_req[i].ar_valid = 1'b0; - axi_wide_rsp[i].ar_ready = 1'b0; - blocking_read[ReqIdx] = 1'b1; + axi_wide_rsp[i].ar_ready = 1'b0; + blocking_read[ReqIdx] = 1'b1; end // check other ports for (int j = 0; j <= ReqIdx; j++) begin // Block read if overlapping region is starting to be written by lower or same ID - if ( (live_write_overlapping_write[ReqIdx][j] && aw_hs[j]) ) begin + if ((live_write_overlapping_write[ReqIdx][j] && aw_hs[j])) begin filtered_wide_req[i].ar_valid = 1'b0; - axi_wide_rsp[i].ar_ready = 1'b0; - blocking_read[ReqIdx] = 1'b1; + axi_wide_rsp[i].ar_ready = 1'b0; + blocking_read[ReqIdx] = 1'b1; end end end @@ -523,45 +530,45 @@ module axi_memory_island_tb #( for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_check // Cut for TB logic loop axi_cut #( - .aw_chan_t ( wide_aw_chan_t ), - .w_chan_t ( wide_w_chan_t ), - .b_chan_t ( wide_b_chan_t ), - .ar_chan_t ( wide_ar_chan_t ), - .r_chan_t ( wide_r_chan_t ), - .axi_req_t ( wide_req_t ), - .axi_resp_t( wide_resp_t ) + .aw_chan_t (wide_aw_chan_t), + .w_chan_t (wide_w_chan_t), + .b_chan_t (wide_b_chan_t), + .ar_chan_t (wide_ar_chan_t), + .r_chan_t (wide_r_chan_t), + .axi_req_t (wide_req_t), + .axi_resp_t(wide_resp_t) ) i_cut_filtered_wide ( .clk_i (clk), .rst_ni (rst_n), - .slv_req_i ( filtered_wide_req[i] ), - .slv_resp_o( filtered_wide_rsp[i] ), - .mst_req_o ( filtered_wide_req_cut[i] ), - .mst_resp_i( filtered_wide_rsp_cut[i] ) + .slv_req_i (filtered_wide_req[i]), + .slv_resp_o(filtered_wide_rsp[i]), + .mst_req_o (filtered_wide_req_cut[i]), + .mst_resp_i(filtered_wide_rsp_cut[i]) ); // Test axi_slave_compare #( - .AxiIdWidth ( AxiIdWidth ), - .FifoDepth ( 32 ), - .UseSize ( 1'b1 ), - .DataWidth ( WideDataWidth ), - .axi_aw_chan_t( wide_aw_chan_t ), - .axi_w_chan_t ( wide_w_chan_t ), - .axi_b_chan_t ( wide_b_chan_t ), - .axi_ar_chan_t( wide_ar_chan_t ), - .axi_r_chan_t ( wide_r_chan_t ), - .axi_req_t ( wide_req_t ), - .axi_rsp_t ( wide_resp_t ) + .AxiIdWidth (AxiIdWidth), + .FifoDepth (32), + .UseSize (1'b1), + .DataWidth (WideDataWidth), + .axi_aw_chan_t(wide_aw_chan_t), + .axi_w_chan_t (wide_w_chan_t), + .axi_b_chan_t (wide_b_chan_t), + .axi_ar_chan_t(wide_ar_chan_t), + .axi_r_chan_t (wide_r_chan_t), + .axi_req_t (wide_req_t), + .axi_rsp_t (wide_resp_t) ) i_wide_compare ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .testmode_i ( '0 ), - .axi_mst_req_i ( filtered_wide_req_cut[i] ), - .axi_mst_rsp_o ( filtered_wide_rsp_cut[i] ), - .axi_ref_req_o ( dut_wide_req [i] ), // bus_compare a - .axi_ref_rsp_i ( dut_wide_rsp [i] ), // bus_compare a - .axi_test_req_o( golden_wide_req [i] ), // bus_compare b - .axi_test_rsp_i( golden_wide_rsp [i] ), // bus_compare b + .clk_i (clk), + .rst_ni (rst_n), + .testmode_i ('0), + .axi_mst_req_i (filtered_wide_req_cut[i]), + .axi_mst_rsp_o (filtered_wide_rsp_cut[i]), + .axi_ref_req_o (dut_wide_req[i]), // bus_compare a + .axi_ref_rsp_i (dut_wide_rsp[i]), // bus_compare a + .axi_test_req_o(golden_wide_req[i]), // bus_compare b + .axi_test_rsp_i(golden_wide_rsp[i]), // bus_compare b .aw_mismatch_o (), .w_mismatch_o (), .b_mismatch_o (), @@ -574,45 +581,45 @@ module axi_memory_island_tb #( // DUT axi_memory_island_wrap #( - .AddrWidth ( AddrWidth ), - .NarrowDataWidth ( NarrowDataWidth ), - .WideDataWidth ( WideDataWidth ), - .AxiNarrowIdWidth ( AxiIdWidth ), - .AxiWideIdWidth ( AxiIdWidth ), - .axi_narrow_req_t ( narrow_req_t ), - .axi_narrow_rsp_t ( narrow_resp_t ), - .axi_wide_req_t ( wide_req_t ), - .axi_wide_rsp_t ( wide_resp_t ), - .NumNarrowReq ( NumNarrowReq ), - .NumWideReq ( NumWideReq ), - - .SpillNarrowReqEntry ( 0 ), - .SpillNarrowRspEntry ( 0 ), - .SpillNarrowReqRouted ( 0 ), - .SpillNarrowRspRouted ( 0 ), - - .SpillWideReqEntry ( 0 ), - .SpillWideRspEntry ( 0 ), - .SpillWideReqRouted ( 0 ), - .SpillWideRspRouted ( 0 ), - .SpillWideReqSplit ( 0 ), - .SpillWideRspSplit ( 0 ), - - .SpillReqBank ( 0 ), - .SpillRspBank ( 0 ), - .WidePriorityWait ( 3 ), - - .NumWideBanks ( NumWideBanks ), - .NarrowExtraBF ( NarrowExtraBF ), - .WordsPerBank ( WordsPerBank ), - .MemorySimInit ( "zeros" ) + .AddrWidth (AddrWidth), + .NarrowDataWidth (NarrowDataWidth), + .WideDataWidth (WideDataWidth), + .AxiNarrowIdWidth(AxiIdWidth), + .AxiWideIdWidth (AxiIdWidth), + .axi_narrow_req_t(narrow_req_t), + .axi_narrow_rsp_t(narrow_resp_t), + .axi_wide_req_t (wide_req_t), + .axi_wide_rsp_t (wide_resp_t), + .NumNarrowReq (NumNarrowReq), + .NumWideReq (NumWideReq), + + .SpillNarrowReqEntry (0), + .SpillNarrowRspEntry (0), + .SpillNarrowReqRouted(0), + .SpillNarrowRspRouted(0), + + .SpillWideReqEntry (0), + .SpillWideRspEntry (0), + .SpillWideReqRouted(0), + .SpillWideRspRouted(0), + .SpillWideReqSplit (0), + .SpillWideRspSplit (0), + + .SpillReqBank (0), + .SpillRspBank (0), + .WidePriorityWait(3), + + .NumWideBanks (NumWideBanks), + .NarrowExtraBF(NarrowExtraBF), + .WordsPerBank (WordsPerBank), + .MemorySimInit("zeros") ) i_dut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_narrow_req_i ( dut_narrow_req ), - .axi_narrow_rsp_o ( dut_narrow_rsp ), - .axi_wide_req_i ( dut_wide_req ), - .axi_wide_rsp_o ( dut_wide_rsp ) + .clk_i (clk), + .rst_ni (rst_n), + .axi_narrow_req_i(dut_narrow_req), + .axi_narrow_rsp_o(dut_narrow_rsp), + .axi_wide_req_i (dut_wide_req), + .axi_wide_rsp_o (dut_wide_rsp) ); // Golden model @@ -622,22 +629,22 @@ module axi_memory_island_tb #( for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_golden_narrow_upsizer axi_dw_upsizer #( - .AxiMaxReads ( TxInFlight ), - .AxiSlvPortDataWidth( NarrowDataWidth ), - .AxiMstPortDataWidth( WideDataWidth ), - .AxiAddrWidth ( AddrWidth ), - .AxiIdWidth ( AxiIdWidth ), - .aw_chan_t ( narrow_aw_chan_t ), - .mst_w_chan_t ( wide_w_chan_t ), - .slv_w_chan_t ( narrow_w_chan_t ), - .b_chan_t ( narrow_b_chan_t ), - .ar_chan_t ( narrow_ar_chan_t ), - .mst_r_chan_t ( wide_r_chan_t ), - .slv_r_chan_t ( narrow_r_chan_t ), - .axi_mst_req_t ( wide_req_t ), - .axi_mst_resp_t ( wide_resp_t ), - .axi_slv_req_t ( narrow_req_t ), - .axi_slv_resp_t ( narrow_resp_t ) + .AxiMaxReads (TxInFlight), + .AxiSlvPortDataWidth(NarrowDataWidth), + .AxiMstPortDataWidth(WideDataWidth), + .AxiAddrWidth (AddrWidth), + .AxiIdWidth (AxiIdWidth), + .aw_chan_t (narrow_aw_chan_t), + .mst_w_chan_t (wide_w_chan_t), + .slv_w_chan_t (narrow_w_chan_t), + .b_chan_t (narrow_b_chan_t), + .ar_chan_t (narrow_ar_chan_t), + .mst_r_chan_t (wide_r_chan_t), + .slv_r_chan_t (narrow_r_chan_t), + .axi_mst_req_t (wide_req_t), + .axi_mst_resp_t (wide_resp_t), + .axi_slv_req_t (narrow_req_t), + .axi_slv_resp_t (narrow_resp_t) ) i_narrow_upsizer ( .clk_i (clk), .rst_ni (rst_n), @@ -653,23 +660,23 @@ module axi_memory_island_tb #( end axi_sim_mem #( - .AddrWidth ( AddrWidth ), - .DataWidth ( WideDataWidth ), - .IdWidth ( AxiIdWidth ), - .UserWidth ( AxiUserWidth ), - .NumPorts ( TotalReq ), - .axi_req_t ( wide_req_t ), - .axi_rsp_t ( wide_resp_t ), - .WarnUninitialized ( 1'b0 ), - .UninitializedData ( "zeros" ), - .ClearErrOnAccess ( 1'b0 ), - .ApplDelay ( ApplTime ), - .AcqDelay ( TestTime ) + .AddrWidth (AddrWidth), + .DataWidth (WideDataWidth), + .IdWidth (AxiIdWidth), + .UserWidth (AxiUserWidth), + .NumPorts (TotalReq), + .axi_req_t (wide_req_t), + .axi_rsp_t (wide_resp_t), + .WarnUninitialized(1'b0), + .UninitializedData("zeros"), + .ClearErrOnAccess (1'b0), + .ApplDelay (ApplTime), + .AcqDelay (TestTime) ) i_sim_mem ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_req_i ( golden_all_req ), - .axi_rsp_o ( golden_all_rsp ), + .clk_i (clk), + .rst_ni (rst_n), + .axi_req_i (golden_all_req), + .axi_rsp_o (golden_all_rsp), .mon_w_valid_o (), .mon_w_addr_o (), .mon_w_data_o (), diff --git a/test/synth/axi_memory_island_synth.sv b/test/synth/axi_memory_island_synth.sv index 3762758..2be7ceb 100644 --- a/test/synth/axi_memory_island_synth.sv +++ b/test/synth/axi_memory_island_synth.sv @@ -12,14 +12,15 @@ module axi_memory_island_synth #( localparam int unsigned NarrowDataWidth = 32, localparam int unsigned WideDataWidth = 512, - localparam int unsigned AxiIdWidth = 3, + localparam int unsigned AxiIdWidth = 3, - localparam int unsigned NumNarrowReq = 5, - localparam int unsigned NumWideReq = 4, - localparam int unsigned WordsPerBank = 8192 + localparam int unsigned NumNarrowReq = 5, + localparam int unsigned NumWideReq = 4, + localparam int unsigned NumWideBanks = 4, + localparam int unsigned WordsPerBank = 8192 ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, input logic [NumNarrowReq-1:0] s_axi_narrow_awvalid, input logic [NumNarrowReq-1:0][ AxiIdWidth-1:0] s_axi_narrow_awid, @@ -114,18 +115,10 @@ module axi_memory_island_synth #( output logic [NumWideReq-1:0] s_axi_wide_ruser ); - `AXI_TYPEDEF_ALL(axi_narrow, - logic[AddrWidth-1:0], - logic[AxiIdWidth-1:0], - logic[NarrowDataWidth-1:0], - logic[NarrowDataWidth/8-1:0], - logic) - `AXI_TYPEDEF_ALL(axi_wide, - logic[AddrWidth-1:0], - logic[AxiIdWidth-1:0], - logic[WideDataWidth-1:0], - logic[WideDataWidth/8-1:0], - logic) + `AXI_TYPEDEF_ALL(axi_narrow, logic[AddrWidth-1:0], logic[AxiIdWidth-1:0], + logic[NarrowDataWidth-1:0], logic[NarrowDataWidth/8-1:0], logic) + `AXI_TYPEDEF_ALL(axi_wide, logic[AddrWidth-1:0], logic[AxiIdWidth-1:0], logic[WideDataWidth-1:0], + logic[WideDataWidth/8-1:0], logic) axi_narrow_req_t [NumNarrowReq-1:0] narrow_req; axi_narrow_resp_t [NumNarrowReq-1:0] narrow_rsp; @@ -138,170 +131,171 @@ module axi_memory_island_synth #( axi_wide_resp_t [NumWideReq -1:0] wide_cut_rsp; for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_assign - assign narrow_req[i].aw_valid = s_axi_narrow_awvalid [i]; - assign narrow_req[i].aw.id = s_axi_narrow_awid [i]; - assign narrow_req[i].aw.addr = s_axi_narrow_awaddr [i]; - assign narrow_req[i].aw.len = s_axi_narrow_awlen [i]; - assign narrow_req[i].aw.size = s_axi_narrow_awsize [i]; - assign narrow_req[i].aw.burst = s_axi_narrow_awburst [i]; - assign narrow_req[i].aw.lock = s_axi_narrow_awlock [i]; - assign narrow_req[i].aw.cache = s_axi_narrow_awcache [i]; - assign narrow_req[i].aw.prot = s_axi_narrow_awprot [i]; - assign narrow_req[i].aw.qos = s_axi_narrow_awqos [i]; + assign narrow_req[i].aw_valid = s_axi_narrow_awvalid[i]; + assign narrow_req[i].aw.id = s_axi_narrow_awid[i]; + assign narrow_req[i].aw.addr = s_axi_narrow_awaddr[i]; + assign narrow_req[i].aw.len = s_axi_narrow_awlen[i]; + assign narrow_req[i].aw.size = s_axi_narrow_awsize[i]; + assign narrow_req[i].aw.burst = s_axi_narrow_awburst[i]; + assign narrow_req[i].aw.lock = s_axi_narrow_awlock[i]; + assign narrow_req[i].aw.cache = s_axi_narrow_awcache[i]; + assign narrow_req[i].aw.prot = s_axi_narrow_awprot[i]; + assign narrow_req[i].aw.qos = s_axi_narrow_awqos[i]; assign narrow_req[i].aw.region = s_axi_narrow_awregion[i]; - assign narrow_req[i].aw.atop = s_axi_narrow_awatop [i]; - assign narrow_req[i].aw.user = s_axi_narrow_awuser [i]; - assign narrow_req[i].w_valid = s_axi_narrow_wvalid [i]; - assign narrow_req[i].w.data = s_axi_narrow_wdata [i]; - assign narrow_req[i].w.strb = s_axi_narrow_wstrb [i]; - assign narrow_req[i].w.last = s_axi_narrow_wlast [i]; - assign narrow_req[i].w.user = s_axi_narrow_wuser [i]; - assign narrow_req[i].b_ready = s_axi_narrow_bready [i]; - assign narrow_req[i].ar_valid = s_axi_narrow_arvalid [i]; - assign narrow_req[i].ar.id = s_axi_narrow_arid [i]; - assign narrow_req[i].ar.addr = s_axi_narrow_araddr [i]; - assign narrow_req[i].ar.len = s_axi_narrow_arlen [i]; - assign narrow_req[i].ar.size = s_axi_narrow_arsize [i]; - assign narrow_req[i].ar.burst = s_axi_narrow_arburst [i]; - assign narrow_req[i].ar.lock = s_axi_narrow_arlock [i]; - assign narrow_req[i].ar.cache = s_axi_narrow_arcache [i]; - assign narrow_req[i].ar.prot = s_axi_narrow_arprot [i]; - assign narrow_req[i].ar.qos = s_axi_narrow_arqos [i]; + assign narrow_req[i].aw.atop = s_axi_narrow_awatop[i]; + assign narrow_req[i].aw.user = s_axi_narrow_awuser[i]; + assign narrow_req[i].w_valid = s_axi_narrow_wvalid[i]; + assign narrow_req[i].w.data = s_axi_narrow_wdata[i]; + assign narrow_req[i].w.strb = s_axi_narrow_wstrb[i]; + assign narrow_req[i].w.last = s_axi_narrow_wlast[i]; + assign narrow_req[i].w.user = s_axi_narrow_wuser[i]; + assign narrow_req[i].b_ready = s_axi_narrow_bready[i]; + assign narrow_req[i].ar_valid = s_axi_narrow_arvalid[i]; + assign narrow_req[i].ar.id = s_axi_narrow_arid[i]; + assign narrow_req[i].ar.addr = s_axi_narrow_araddr[i]; + assign narrow_req[i].ar.len = s_axi_narrow_arlen[i]; + assign narrow_req[i].ar.size = s_axi_narrow_arsize[i]; + assign narrow_req[i].ar.burst = s_axi_narrow_arburst[i]; + assign narrow_req[i].ar.lock = s_axi_narrow_arlock[i]; + assign narrow_req[i].ar.cache = s_axi_narrow_arcache[i]; + assign narrow_req[i].ar.prot = s_axi_narrow_arprot[i]; + assign narrow_req[i].ar.qos = s_axi_narrow_arqos[i]; assign narrow_req[i].ar.region = s_axi_narrow_arregion[i]; - assign narrow_req[i].ar.user = s_axi_narrow_aruser [i]; - assign narrow_req[i].r_ready = s_axi_narrow_rready [i]; + assign narrow_req[i].ar.user = s_axi_narrow_aruser[i]; + assign narrow_req[i].r_ready = s_axi_narrow_rready[i]; assign s_axi_narrow_awready[i] = narrow_rsp[i].aw_ready; assign s_axi_narrow_arready[i] = narrow_rsp[i].ar_ready; - assign s_axi_narrow_wready [i] = narrow_rsp[i].w_ready; - assign s_axi_narrow_bvalid [i] = narrow_rsp[i].b_valid; - assign s_axi_narrow_bid [i] = narrow_rsp[i].b.id; - assign s_axi_narrow_bresp [i] = narrow_rsp[i].b.resp; - assign s_axi_narrow_buser [i] = narrow_rsp[i].b.user; - assign s_axi_narrow_rvalid [i] = narrow_rsp[i].r_valid; - assign s_axi_narrow_rid [i] = narrow_rsp[i].r.id; - assign s_axi_narrow_rdata [i] = narrow_rsp[i].r.data; - assign s_axi_narrow_rresp [i] = narrow_rsp[i].r.resp; - assign s_axi_narrow_rlast [i] = narrow_rsp[i].r.last; - assign s_axi_narrow_ruser [i] = narrow_rsp[i].r.user; + assign s_axi_narrow_wready[i] = narrow_rsp[i].w_ready; + assign s_axi_narrow_bvalid[i] = narrow_rsp[i].b_valid; + assign s_axi_narrow_bid[i] = narrow_rsp[i].b.id; + assign s_axi_narrow_bresp[i] = narrow_rsp[i].b.resp; + assign s_axi_narrow_buser[i] = narrow_rsp[i].b.user; + assign s_axi_narrow_rvalid[i] = narrow_rsp[i].r_valid; + assign s_axi_narrow_rid[i] = narrow_rsp[i].r.id; + assign s_axi_narrow_rdata[i] = narrow_rsp[i].r.data; + assign s_axi_narrow_rresp[i] = narrow_rsp[i].r.resp; + assign s_axi_narrow_rlast[i] = narrow_rsp[i].r.last; + assign s_axi_narrow_ruser[i] = narrow_rsp[i].r.user; axi_cut #( - .aw_chan_t ( axi_narrow_aw_chan_t ), - .w_chan_t ( axi_narrow_w_chan_t ), - .b_chan_t ( axi_narrow_b_chan_t ), - .ar_chan_t ( axi_narrow_ar_chan_t ), - .r_chan_t ( axi_narrow_r_chan_t ), - .axi_req_t ( axi_narrow_req_t ), - .axi_resp_t( axi_narrow_resp_t ) + .aw_chan_t (axi_narrow_aw_chan_t), + .w_chan_t (axi_narrow_w_chan_t), + .b_chan_t (axi_narrow_b_chan_t), + .ar_chan_t (axi_narrow_ar_chan_t), + .r_chan_t (axi_narrow_r_chan_t), + .axi_req_t (axi_narrow_req_t), + .axi_resp_t(axi_narrow_resp_t) ) i_cut ( .clk_i, .rst_ni, - .slv_req_i ( narrow_req [i] ), - .slv_resp_o( narrow_rsp [i] ), - .mst_req_o ( narrow_cut_req[i] ), - .mst_resp_i( narrow_cut_rsp[i] ) + .slv_req_i (narrow_req[i]), + .slv_resp_o(narrow_rsp[i]), + .mst_req_o (narrow_cut_req[i]), + .mst_resp_i(narrow_cut_rsp[i]) ); end for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_assign - assign wide_req[i].aw_valid = s_axi_wide_awvalid [i]; - assign wide_req[i].aw.id = s_axi_wide_awid [i]; - assign wide_req[i].aw.addr = s_axi_wide_awaddr [i]; - assign wide_req[i].aw.len = s_axi_wide_awlen [i]; - assign wide_req[i].aw.size = s_axi_wide_awsize [i]; - assign wide_req[i].aw.burst = s_axi_wide_awburst [i]; - assign wide_req[i].aw.lock = s_axi_wide_awlock [i]; - assign wide_req[i].aw.cache = s_axi_wide_awcache [i]; - assign wide_req[i].aw.prot = s_axi_wide_awprot [i]; - assign wide_req[i].aw.qos = s_axi_wide_awqos [i]; + assign wide_req[i].aw_valid = s_axi_wide_awvalid[i]; + assign wide_req[i].aw.id = s_axi_wide_awid[i]; + assign wide_req[i].aw.addr = s_axi_wide_awaddr[i]; + assign wide_req[i].aw.len = s_axi_wide_awlen[i]; + assign wide_req[i].aw.size = s_axi_wide_awsize[i]; + assign wide_req[i].aw.burst = s_axi_wide_awburst[i]; + assign wide_req[i].aw.lock = s_axi_wide_awlock[i]; + assign wide_req[i].aw.cache = s_axi_wide_awcache[i]; + assign wide_req[i].aw.prot = s_axi_wide_awprot[i]; + assign wide_req[i].aw.qos = s_axi_wide_awqos[i]; assign wide_req[i].aw.region = s_axi_wide_awregion[i]; - assign wide_req[i].aw.atop = s_axi_wide_awatop [i]; - assign wide_req[i].aw.user = s_axi_wide_awuser [i]; - assign wide_req[i].w_valid = s_axi_wide_wvalid [i]; - assign wide_req[i].w.data = s_axi_wide_wdata [i]; - assign wide_req[i].w.strb = s_axi_wide_wstrb [i]; - assign wide_req[i].w.last = s_axi_wide_wlast [i]; - assign wide_req[i].w.user = s_axi_wide_wuser [i]; - assign wide_req[i].b_ready = s_axi_wide_bready [i]; - assign wide_req[i].ar_valid = s_axi_wide_arvalid [i]; - assign wide_req[i].ar.id = s_axi_wide_arid [i]; - assign wide_req[i].ar.addr = s_axi_wide_araddr [i]; - assign wide_req[i].ar.len = s_axi_wide_arlen [i]; - assign wide_req[i].ar.size = s_axi_wide_arsize [i]; - assign wide_req[i].ar.burst = s_axi_wide_arburst [i]; - assign wide_req[i].ar.lock = s_axi_wide_arlock [i]; - assign wide_req[i].ar.cache = s_axi_wide_arcache [i]; - assign wide_req[i].ar.prot = s_axi_wide_arprot [i]; - assign wide_req[i].ar.qos = s_axi_wide_arqos [i]; + assign wide_req[i].aw.atop = s_axi_wide_awatop[i]; + assign wide_req[i].aw.user = s_axi_wide_awuser[i]; + assign wide_req[i].w_valid = s_axi_wide_wvalid[i]; + assign wide_req[i].w.data = s_axi_wide_wdata[i]; + assign wide_req[i].w.strb = s_axi_wide_wstrb[i]; + assign wide_req[i].w.last = s_axi_wide_wlast[i]; + assign wide_req[i].w.user = s_axi_wide_wuser[i]; + assign wide_req[i].b_ready = s_axi_wide_bready[i]; + assign wide_req[i].ar_valid = s_axi_wide_arvalid[i]; + assign wide_req[i].ar.id = s_axi_wide_arid[i]; + assign wide_req[i].ar.addr = s_axi_wide_araddr[i]; + assign wide_req[i].ar.len = s_axi_wide_arlen[i]; + assign wide_req[i].ar.size = s_axi_wide_arsize[i]; + assign wide_req[i].ar.burst = s_axi_wide_arburst[i]; + assign wide_req[i].ar.lock = s_axi_wide_arlock[i]; + assign wide_req[i].ar.cache = s_axi_wide_arcache[i]; + assign wide_req[i].ar.prot = s_axi_wide_arprot[i]; + assign wide_req[i].ar.qos = s_axi_wide_arqos[i]; assign wide_req[i].ar.region = s_axi_wide_arregion[i]; - assign wide_req[i].ar.user = s_axi_wide_aruser [i]; - assign wide_req[i].r_ready = s_axi_wide_rready [i]; + assign wide_req[i].ar.user = s_axi_wide_aruser[i]; + assign wide_req[i].r_ready = s_axi_wide_rready[i]; assign s_axi_wide_awready[i] = wide_rsp[i].aw_ready; assign s_axi_wide_arready[i] = wide_rsp[i].ar_ready; - assign s_axi_wide_wready [i] = wide_rsp[i].w_ready; - assign s_axi_wide_bvalid [i] = wide_rsp[i].b_valid; - assign s_axi_wide_bid [i] = wide_rsp[i].b.id; - assign s_axi_wide_bresp [i] = wide_rsp[i].b.resp; - assign s_axi_wide_buser [i] = wide_rsp[i].b.user; - assign s_axi_wide_rvalid [i] = wide_rsp[i].r_valid; - assign s_axi_wide_rid [i] = wide_rsp[i].r.id; - assign s_axi_wide_rdata [i] = wide_rsp[i].r.data; - assign s_axi_wide_rresp [i] = wide_rsp[i].r.resp; - assign s_axi_wide_rlast [i] = wide_rsp[i].r.last; - assign s_axi_wide_ruser [i] = wide_rsp[i].r.user; + assign s_axi_wide_wready[i] = wide_rsp[i].w_ready; + assign s_axi_wide_bvalid[i] = wide_rsp[i].b_valid; + assign s_axi_wide_bid[i] = wide_rsp[i].b.id; + assign s_axi_wide_bresp[i] = wide_rsp[i].b.resp; + assign s_axi_wide_buser[i] = wide_rsp[i].b.user; + assign s_axi_wide_rvalid[i] = wide_rsp[i].r_valid; + assign s_axi_wide_rid[i] = wide_rsp[i].r.id; + assign s_axi_wide_rdata[i] = wide_rsp[i].r.data; + assign s_axi_wide_rresp[i] = wide_rsp[i].r.resp; + assign s_axi_wide_rlast[i] = wide_rsp[i].r.last; + assign s_axi_wide_ruser[i] = wide_rsp[i].r.user; axi_cut #( - .aw_chan_t ( axi_wide_aw_chan_t ), - .w_chan_t ( axi_wide_w_chan_t ), - .b_chan_t ( axi_wide_b_chan_t ), - .ar_chan_t ( axi_wide_ar_chan_t ), - .r_chan_t ( axi_wide_r_chan_t ), - .axi_req_t ( axi_wide_req_t ), - .axi_resp_t( axi_wide_resp_t ) + .aw_chan_t (axi_wide_aw_chan_t), + .w_chan_t (axi_wide_w_chan_t), + .b_chan_t (axi_wide_b_chan_t), + .ar_chan_t (axi_wide_ar_chan_t), + .r_chan_t (axi_wide_r_chan_t), + .axi_req_t (axi_wide_req_t), + .axi_resp_t(axi_wide_resp_t) ) i_cut ( .clk_i, .rst_ni, - .slv_req_i ( wide_req [i] ), - .slv_resp_o( wide_rsp [i] ), - .mst_req_o ( wide_cut_req[i] ), - .mst_resp_i( wide_cut_rsp[i] ) + .slv_req_i (wide_req[i]), + .slv_resp_o(wide_rsp[i]), + .mst_req_o (wide_cut_req[i]), + .mst_resp_i(wide_cut_rsp[i]) ); end axi_memory_island_wrap #( - .AddrWidth ( AddrWidth ), - .NarrowDataWidth ( NarrowDataWidth ), - .WideDataWidth ( WideDataWidth ), - .AxiNarrowIdWidth ( AxiIdWidth ), - .AxiWideIdWidth ( AxiIdWidth ), - .axi_narrow_req_t ( axi_narrow_req_t ), - .axi_narrow_rsp_t ( axi_narrow_resp_t ), - .axi_wide_req_t ( axi_wide_req_t ), - .axi_wide_rsp_t ( axi_wide_resp_t ), - .NumNarrowReq ( NumNarrowReq ), - .NumWideReq ( NumWideReq ), - .WordsPerBank ( WordsPerBank ), + .AddrWidth (AddrWidth), + .NarrowDataWidth (NarrowDataWidth), + .WideDataWidth (WideDataWidth), + .AxiNarrowIdWidth (AxiIdWidth), + .AxiWideIdWidth (AxiIdWidth), + .axi_narrow_req_t (axi_narrow_req_t), + .axi_narrow_rsp_t (axi_narrow_resp_t), + .axi_wide_req_t (axi_wide_req_t), + .axi_wide_rsp_t (axi_wide_resp_t), + .NumNarrowReq (NumNarrowReq), + .NumWideReq (NumWideReq), + .WordsPerBank (WordsPerBank), .SpillNarrowReqEntry (0), .SpillNarrowRspEntry (0), .SpillNarrowReqRouted(0), .SpillNarrowRspRouted(0), .SpillWideReqEntry (0), .SpillWideRspEntry (0), - .SpillWideReqRouted (0), - .SpillWideRspRouted (0), + .SpillWideReqRouted (1), + .SpillWideRspRouted (1), .SpillWideReqSplit (0), .SpillWideRspSplit (0), .SpillReqBank (1), .SpillRspBank (1), - .WidePriorityWait (2) + .WidePriorityWait (2), + .NumWideBanks (NumWideBanks) ) i_mem_island ( .clk_i, .rst_ni, - .axi_narrow_req_i ( narrow_cut_req ), - .axi_narrow_rsp_o ( narrow_cut_rsp ), + .axi_narrow_req_i(narrow_cut_req), + .axi_narrow_rsp_o(narrow_cut_rsp), - .axi_wide_req_i ( wide_cut_req ), - .axi_wide_rsp_o ( wide_cut_rsp ) -); + .axi_wide_req_i(wide_cut_req), + .axi_wide_rsp_o(wide_cut_rsp) + ); endmodule