diff --git a/.verilog_format b/.verilog_format index 444c19d..79cf152 100644 --- a/.verilog_format +++ b/.verilog_format @@ -1,7 +1,7 @@ --column_limit=100 --indentation_spaces=2 --line_break_penalty=2 ---over_column_limit_penalty=10000 +--over_column_limit_penalty=100 --wrap_spaces=4 --assignment_statement_alignment=align --case_items_alignment=align @@ -18,7 +18,7 @@ --port_declarations_alignment=align --port_declarations_indentation=indent --struct_union_members_alignment=align ---try_wrap_long_lines=false +--try_wrap_long_lines=true --wrap_end_else_clauses=false --port_declarations_right_align_packed_dimensions=false --port_declarations_right_align_unpacked_dimensions=false diff --git a/Bender.yml b/Bender.yml index abd0797..ae3363e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -6,6 +6,7 @@ package: name: memory_island authors: - "Michael Rogenmoser " + - "Moritz Scherer " dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.37.0 } diff --git a/src/axi_memory_island_wrap.sv b/src/axi_memory_island_wrap.sv index 97bd5a1..aa06a3f 100644 --- a/src/axi_memory_island_wrap.sv +++ b/src/axi_memory_island_wrap.sv @@ -3,6 +3,7 @@ // SPDX-License-Identifier: SHL-0.51 // Michael Rogenmoser +// Moritz Scherer module axi_memory_island_wrap #( /// Address Width @@ -51,13 +52,15 @@ module axi_memory_island_wrap #( parameter int unsigned WidePriorityWait = 1, /// Banking Factor for the Wide Ports (power of 2) - parameter int unsigned NumWideBanks = (1 << $clog2(NumWideReq)) * 2 * 2, + parameter int unsigned NumWideBanks = (1 << $clog2(NumWideReq)) * 2 * 2, /// Extra multiplier for the Narrow banking factor (baseline is WideWidth/NarrowWidth) (power of 2) - parameter int unsigned NarrowExtraBF = 1, + parameter int unsigned NarrowExtraBF = 1, /// Words per memory bank. (Total number of banks is (WideWidth/NarrowWidth)*NumWideBanks) - parameter int unsigned WordsPerBank = 1024, + parameter int unsigned WordsPerBank = 1024, // verilog_lint: waive explicit-parameter-storage-type - parameter MemorySimInit = "none" + parameter MemorySimInit = "none", + /// Number of cycles a memory macro takes to respond to a read request + parameter int unsigned BankAccessLatency = 1 ) ( input logic clk_i, input logic rst_ni, @@ -68,29 +71,19 @@ module axi_memory_island_wrap #( input axi_wide_req_t [NumWideReq-1:0] axi_wide_req_i, output axi_wide_rsp_t [NumWideReq-1:0] axi_wide_rsp_o ); - + localparam int unsigned NWDivisor = WideDataWidth / NarrowDataWidth; + localparam int unsigned BankAddrMemWidth = $clog2(WordsPerBank); localparam int unsigned NarrowStrbWidth = NarrowDataWidth / 8; localparam int unsigned WideStrbWidth = WideDataWidth / 8; localparam int unsigned InternalNumNarrow = NumNarrowReq + $countones(NarrowRW); localparam int unsigned InternalNumWide = NumWideReq + $countones(WideRW); - localparam int unsigned NarrowMemRspLatency = SpillNarrowReqEntry + - SpillNarrowReqRouted + - SpillReqBank + - SpillRspBank + - SpillNarrowRspRouted + - SpillNarrowRspEntry + - 1; - localparam int unsigned WideMemRspLatency = SpillWideReqEntry + - SpillWideReqRouted + - SpillWideReqSplit + - SpillReqBank + - SpillRspBank + - SpillWideRspSplit + - SpillWideRspRouted + - SpillWideRspEntry + - 1; + localparam int unsigned NarrowMemRspLatency = SpillNarrowReqEntry + SpillNarrowReqRouted + + SpillReqBank + SpillRspBank + SpillNarrowRspRouted + SpillNarrowRspEntry + BankAccessLatency; + localparam int unsigned WideMemRspLatency = SpillWideReqEntry + SpillWideReqRouted + + SpillWideReqSplit + SpillReqBank + SpillRspBank + SpillWideRspSplit + SpillWideRspRouted + + SpillWideRspEntry + BankAccessLatency; logic [InternalNumNarrow-1:0] narrow_req; logic [InternalNumNarrow-1:0] narrow_gnt; @@ -206,7 +199,7 @@ module axi_memory_island_wrap #( .axi_req_t (axi_wide_req_t), .axi_resp_t (axi_wide_rsp_t), .AddrWidth (AddrWidth), - .AxiDataWidth(WideDataWidth), + .DataWidth (WideDataWidth), .IdWidth (AxiWideIdWidth), .NumBanks (1), .BufDepth (1 + WideMemRspLatency), @@ -254,7 +247,8 @@ module axi_memory_island_wrap #( .SpillReqBank (SpillReqBank), .SpillRspBank (SpillRspBank), .WidePriorityWait (WidePriorityWait), - .MemorySimInit (MemorySimInit) + .MemorySimInit (MemorySimInit), + .BankAccessLatency (BankAccessLatency) ) i_memory_island ( .clk_i, .rst_ni, diff --git a/src/memory_island_core.sv b/src/memory_island_core.sv index 756463a..f12c200 100644 --- a/src/memory_island_core.sv +++ b/src/memory_island_core.sv @@ -3,6 +3,7 @@ // SPDX-License-Identifier: SHL-0.51 // Michael Rogenmoser +// Moritz Scherer module memory_island_core #( /// Address Width @@ -47,9 +48,11 @@ module memory_island_core #( parameter int unsigned WidePriorityWait = 1, // Derived, DO NOT OVERRIDE - parameter int unsigned NarrowStrbWidth = NarrowDataWidth / 8, - parameter int unsigned WideStrbWidth = WideDataWidth / 8, - parameter int unsigned NWDivisor = WideDataWidth / NarrowDataWidth + parameter int unsigned NarrowStrbWidth = NarrowDataWidth / 8, + parameter int unsigned WideStrbWidth = WideDataWidth / 8, + parameter int unsigned NWDivisor = WideDataWidth / NarrowDataWidth, + parameter int unsigned BankAddrMemWidth = $clog2(WordsPerBank), + parameter int unsigned BankAccessLatency = 1 ) ( input logic clk_i, input logic rst_ni, @@ -73,6 +76,7 @@ module memory_island_core #( input logic [NumWideReq-1:0][WideStrbWidth-1:0] wide_strb_i, output logic [NumWideReq-1:0] wide_rvalid_o, output logic [NumWideReq-1:0][WideDataWidth-1:0] wide_rdata_o + ); initial begin @@ -100,19 +104,15 @@ module memory_island_core #( localparam int unsigned AddrNarrowWordBit = $clog2(NarrowDataWidth / 8); localparam int unsigned AddrWideWordBit = $clog2(WideDataWidth / 8); localparam int unsigned AddrNarrowWideBit = AddrWideWordBit + $clog2(NarrowExtraBF); + localparam int unsigned AddrWideBankBit = AddrWideWordBit + $clog2(NumWideBanks); localparam int unsigned AddrTopBit = AddrWideBankBit + $clog2(WordsPerBank); localparam int unsigned NarrowAddrMemWidth = AddrTopBit - AddrNarrowWideBit; - localparam int unsigned BankAddrMemWidth = $clog2(WordsPerBank); - localparam int unsigned NarrowIntcBankLat = 1 + - SpillNarrowReqRouted + - SpillNarrowRspRouted + - SpillReqBank + - SpillRspBank; - localparam int unsigned PriorityWaitWidth = cf_math_pkg::idx_width(WidePriorityWait); + localparam int unsigned NarrowIntcBankLat = BankAccessLatency + SpillNarrowReqRouted + + SpillNarrowRspRouted + SpillReqBank + SpillRspBank; logic [NumNarrowReq-1:0] narrow_req_entry_spill; logic [NumNarrowReq-1:0] narrow_gnt_entry_spill; @@ -209,7 +209,8 @@ module memory_island_core #( logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] rdata_bank_spill; logic [NumWideBanks-1:0][NWDivisor-1:0] narrow_priority_req; - logic [NumWideBanks-1:0][NWDivisor-1:0][PriorityWaitWidth-1:0] wide_priority_d, wide_priority_q; + logic [NumWideBanks-1:0][NWDivisor-1:0][cf_math_pkg::idx_width(WidePriorityWait)-1:0] + wide_priority_d, wide_priority_q; for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_entry_cuts mem_req_multicut #( @@ -382,7 +383,7 @@ module memory_island_core #( for (int wideBank = 0; wideBank < TotalBanks / WidePseudoBanks; wideBank++) begin if (narrow_addr_routed_spill[PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank) begin narrow_gnt_routed_spill[PseudoIdx] = - narrow_gnt_bank [(wideBank*NarrowExtraBF)+extraFactor][subBank]; + narrow_gnt_bank[(wideBank*NarrowExtraBF)+extraFactor][subBank]; end end end @@ -400,10 +401,10 @@ module memory_island_core #( for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_routed_bank_l3 localparam int unsigned WideBankIdx = (wideBank * NarrowExtraBF) + extraFactor; localparam int unsigned PseudoIdx = (extraFactor * NWDivisor) + subBank; - assign narrow_req_bank [WideBankIdx][subBank] = narrow_req_routed_spill [PseudoIdx] & - (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank); - assign narrow_addr_bank [WideBankIdx][subBank] = - narrow_addr_routed_spill [PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth]; + assign narrow_req_bank[WideBankIdx][subBank] = narrow_req_routed_spill[PseudoIdx] & + (narrow_addr_routed_spill[PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank); + assign narrow_addr_bank[WideBankIdx][subBank] = + narrow_addr_routed_spill[PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth]; assign narrow_we_bank[WideBankIdx][subBank] = narrow_we_routed_spill[PseudoIdx]; assign narrow_wdata_bank[WideBankIdx][subBank] = narrow_wdata_routed_spill[PseudoIdx]; assign narrow_strb_bank[WideBankIdx][subBank] = narrow_strb_routed_spill[PseudoIdx]; @@ -428,7 +429,7 @@ module memory_island_core #( .d_o(narrow_rdata_sel) ); assign narrow_rdata_routed_spill[PseudoIdx] = - narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF) + extraFactor][subBank]; + narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF)+extraFactor][subBank]; end end @@ -615,14 +616,14 @@ module memory_island_core #( assign req_bank[i][j] = narrow_req_bank[i][j] | wide_req_bank_spill[i][j]; assign narrow_gnt_bank[i][j] = narrow_priority_req[i][j]; assign wide_gnt_bank_spill[i][j] = ~narrow_priority_req[i][j]; - assign we_bank [i][j] = narrow_priority_req[i][j] ? narrow_we_bank [i][j]: - wide_we_bank_spill [i][j]; - assign addr_bank [i][j] = narrow_priority_req[i][j] ? narrow_addr_bank [i][j]: - wide_addr_bank_spill [i][j]; - assign wdata_bank [i][j] = narrow_priority_req[i][j] ? narrow_wdata_bank [i][j]: - wide_wdata_bank_spill[i][j]; - assign strb_bank [i][j] = narrow_priority_req[i][j] ? narrow_strb_bank [i][j]: - wide_strb_bank_spill [i][j]; + assign we_bank[i][j] = narrow_priority_req[i][j] ? narrow_we_bank[i][j] : + wide_we_bank_spill[i][j]; + assign addr_bank[i][j] = narrow_priority_req[i][j] ? narrow_addr_bank[i][j] : + wide_addr_bank_spill[i][j]; + assign wdata_bank[i][j] = narrow_priority_req[i][j] ? narrow_wdata_bank[i][j] : + wide_wdata_bank_spill[i][j]; + assign strb_bank[i][j] = narrow_priority_req[i][j] ? narrow_strb_bank[i][j] : + wide_strb_bank_spill[i][j]; assign narrow_rdata_bank[i][j] = rdata_bank[i][j]; assign wide_rdata_bank_spill[i][j] = rdata_bank[i][j]; @@ -671,7 +672,7 @@ module memory_island_core #( .DataWidth(NarrowDataWidth), .ByteWidth(8), .NumPorts (1), - .Latency (1), + .Latency (BankAccessLatency), .SimInit (MemorySimInit) ) i_bank ( .clk_i, @@ -685,15 +686,18 @@ module memory_island_core #( ); // Shift reg for wide rvalid - logic [SpillReqBank+SpillRspBank:0] shift_rvalid_d, shift_rvalid_q; - for (genvar k = 0; k < SpillReqBank + SpillRspBank + 1; k++) begin : gen_shift_rvalid + logic [SpillReqBank+SpillRspBank+BankAccessLatency-1:0] shift_rvalid_d, shift_rvalid_q; + for ( + genvar k = 0; k < SpillReqBank + SpillRspBank + BankAccessLatency; k++ + ) begin : gen_shift_rvalid if (k == 0) begin : gen_shift_in assign shift_rvalid_d[k] = req_bank[i][j] & wide_gnt_bank[i][j]; end else begin : gen_shift assign shift_rvalid_d[k] = shift_rvalid_q[k-1]; end end - assign wide_rvalid_bank_spill[i][j] = shift_rvalid_q[SpillReqBank+SpillRspBank]; + assign wide_rvalid_bank_spill[i][j] = + shift_rvalid_q[SpillReqBank+SpillRspBank+BankAccessLatency-1]; always_ff @(posedge clk_i or negedge rst_ni) begin : proc_wide_bank_rvalid if (~rst_ni) begin diff --git a/src/stream_mem_to_banks_det.sv b/src/stream_mem_to_banks_det.sv index f8dc0fd..16a5a32 100644 --- a/src/stream_mem_to_banks_det.sv +++ b/src/stream_mem_to_banks_det.sv @@ -152,10 +152,10 @@ module stream_mem_to_banks_det #( assign zero_strobe[i] = (|bank_req[i].strb == '0); if (HideStrb) begin : gen_hide_strb - assign bank_req_o[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? - 1'b0 : bank_req_internal[i]; - assign bank_gnt_internal[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? - 1'b1 : bank_gnt_i[i]; + assign bank_req_o[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? 1'b0 : + bank_req_internal[i]; + assign bank_gnt_internal[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? 1'b1 : + bank_gnt_i[i]; end else begin : gen_legacy_strb assign bank_req_o[i] = bank_req_internal[i]; assign bank_gnt_internal[i] = bank_gnt_i[i]; diff --git a/src/varlat_inorder_interco.sv b/src/varlat_inorder_interco.sv index 57a0fda..fe4a8d5 100644 --- a/src/varlat_inorder_interco.sv +++ b/src/varlat_inorder_interco.sv @@ -137,9 +137,8 @@ module varlat_inorder_interco #( // Response path for (genvar i = 0; i < NumIn; i++) begin : gen_rsp - assign vld_o[i] = rvalid_i[bank_sel_rsp[i]] & - rready_o[bank_sel_rsp[i]] & - (ini_addr_rsp[bank_sel_rsp[i]] == i); + assign vld_o[i] = rvalid_i[bank_sel_rsp[i]] & rready_o[bank_sel_rsp[i]] & + (ini_addr_rsp[bank_sel_rsp[i]] == i); assign rdata_o[i] = rdata_i[bank_sel_rsp[i]]; end for (genvar i = 0; i < NumOut; i++) begin : gen_rready diff --git a/test/axi_memory_island_tb.sv b/test/axi_memory_island_tb.sv index fefa36c..aa35b7e 100644 --- a/test/axi_memory_island_tb.sv +++ b/test/axi_memory_island_tb.sv @@ -11,28 +11,29 @@ `include "common_cells/assertions.svh" module axi_memory_island_tb #( - parameter int unsigned AddrWidth = 32, - parameter int unsigned NarrowDataWidth = 32, - parameter int unsigned WideDataWidth = 512, - parameter int unsigned AxiIdWidth = 2, - parameter int unsigned AxiUserWidth = 1, - parameter int unsigned NumNarrowReq = 4, - parameter int unsigned NumWideReq = 2, - parameter int unsigned NumWideBanks = 8, - parameter int unsigned NarrowExtraBF = 2, - parameter int unsigned WordsPerBank = 512 * NumNarrowReq * NumWideReq, - parameter int unsigned TbNumReads = 200, - parameter int unsigned TbNumWrites = 200, - parameter time CyclTime = 10ns, - parameter time ApplTime = 2ns, - parameter time TestTime = 8ns, + parameter int unsigned AddrWidth = 32, + parameter int unsigned NarrowDataWidth = 32, + parameter int unsigned WideDataWidth = 512, + parameter int unsigned AxiIdWidth = 2, + parameter int unsigned AxiUserWidth = 1, + parameter int unsigned NumNarrowReq = 4, + parameter int unsigned NumWideReq = 2, + parameter int unsigned NumWideBanks = 8, + parameter int unsigned NarrowExtraBF = 2, + parameter int unsigned WordsPerBank = 512 * NumNarrowReq * NumWideReq, + parameter int unsigned TbNumReads = 200, + parameter int unsigned TbNumWrites = 200, + parameter int unsigned BankAccessLatency = 2, + parameter time CyclTime = 10ns, + parameter time ApplTime = 2ns, + parameter time TestTime = 8ns, localparam int unsigned TestRegionStart = 0, localparam int unsigned TestRegionEnd = 16384 ) (); - localparam int unsigned TotalNumberOfWords = WordsPerBank * NumWideBanks * - WideDataWidth / NarrowDataWidth; + localparam int unsigned TotalNumberOfWords = WordsPerBank * NumWideBanks * WideDataWidth / + NarrowDataWidth; localparam int unsigned TotalBytes = WordsPerBank * NumWideBanks * WideDataWidth / 8; localparam int unsigned WideToNarrowFactor = WideDataWidth / NarrowDataWidth; @@ -178,8 +179,8 @@ module axi_memory_island_tb #( // Overlap if !(b.end < a.start || b.start > a.end) function automatic logic check_overlap(addr_range_t range_a, addr_range_t range_b); - check_overlap = !((range_a.start_addr > range_b.end_addr) || - (range_a.end_addr < range_b.start_addr)); + check_overlap = + !((range_a.start_addr > range_b.end_addr) || (range_a.end_addr < range_b.start_addr)); endfunction addr_range_t [TotalReq-1:0] tmp_read, tmp_write; @@ -206,9 +207,8 @@ module axi_memory_island_tb #( // $display("writing to [%x, %x]", write_range[i].start_addr, write_range[i].end_addr); end // pop write queue on B - if (axi_narrow_rsp[i].b_valid && - filtered_narrow_req[i].b_ready && - axi_narrow_rsp[i].b.id == id ) begin + if (axi_narrow_rsp[i].b_valid && filtered_narrow_req[i].b_ready && + axi_narrow_rsp[i].b.id == id) begin tmp_write[i] = regions_being_written[i][id].pop_front(); // $display("done writing [%x, %x]",tmp_write[i].start_addr, tmp_write[i].end_addr); end @@ -219,7 +219,7 @@ module axi_memory_island_tb #( end // pop read queue on last R if (axi_narrow_rsp[i].r_valid && filtered_narrow_req[i].r_ready && - axi_narrow_rsp[i].r.last && axi_narrow_rsp[i].r.id == id ) begin + axi_narrow_rsp[i].r.last && axi_narrow_rsp[i].r.id == id) begin tmp_read[i] = regions_being_read[i][id].pop_front(); // $display("done reading [%x, %x]",tmp_read[i].start_addr, tmp_read[i].end_addr); end @@ -260,11 +260,11 @@ module axi_memory_island_tb #( for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_limiting // Log address ranges of the requests assign write_range[i].start_addr = axi_narrow_req[i].aw.addr; - assign write_range[i].end_addr = axi_narrow_req[i].aw.addr + - ((2**axi_narrow_req[i].aw.size)*(axi_narrow_req[i].aw.len+1)); + assign write_range[i].end_addr = axi_narrow_req[i].aw.addr + + ((2 ** axi_narrow_req[i].aw.size) * (axi_narrow_req[i].aw.len + 1)); assign read_range[i].start_addr = axi_narrow_req[i].ar.addr; - assign read_range[i].end_addr = axi_narrow_req[i].ar.addr + - ((2**axi_narrow_req[i].ar.size)*(axi_narrow_req[i].ar.len+1)); + assign read_range[i].end_addr = axi_narrow_req[i].ar.addr + + ((2 ** axi_narrow_req[i].ar.size) * (axi_narrow_req[i].ar.len + 1)); assign aw_hs[i] = filtered_narrow_req[i].aw_valid && axi_narrow_rsp[i].aw_ready; assign ar_hs[i] = filtered_narrow_req[i].ar_valid && axi_narrow_rsp[i].ar_ready; @@ -276,16 +276,16 @@ module axi_memory_island_tb #( // Block write if overlapping region is already being written write_overlapping_write[i][requestIdx][axiIdx][txIdx] = - txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(write_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; + txIdx < write_len[requestIdx][axiIdx] ? check_overlap( + write_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; // Block reads if overlapping region is already being written - read_overlapping_write[i][requestIdx][axiIdx][txIdx] = - txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(read_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; + read_overlapping_write[i][requestIdx][axiIdx][txIdx] = + txIdx < write_len[requestIdx][axiIdx] ? + check_overlap(read_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; // Block write if overlapping region is already being read - write_overlapping_read[i][requestIdx][axiIdx][txIdx] = - txIdx < read_len[requestIdx][axiIdx] ? - check_overlap(write_range[i], regions_being_read[requestIdx][axiIdx][txIdx]) : '0; + write_overlapping_read[i][requestIdx][axiIdx][txIdx] = + txIdx < read_len[requestIdx][axiIdx] ? + check_overlap(write_range[i], regions_being_read[requestIdx][axiIdx][txIdx]) : '0; end end live_write_overlapping_write[i][requestIdx] = @@ -315,8 +315,8 @@ module axi_memory_island_tb #( // check other ports for (int j = 0; j < i; j++) begin // Block write if overlapping region is starting to be written/read by lower ID - if ( (live_write_overlapping_write[i][j] && aw_hs[j]) || - (live_write_overlapping_read [i][j] && ar_hs[j]) ) begin + if ((live_write_overlapping_write[i][j] && aw_hs[j]) || + (live_write_overlapping_read[i][j] && ar_hs[j])) begin filtered_narrow_req[i].aw_valid = 1'b0; axi_narrow_rsp[i].aw_ready = 1'b0; blocking_write[i] = 1'b1; @@ -421,11 +421,11 @@ module axi_memory_island_tb #( localparam int unsigned ReqIdx = NumNarrowReq + i; // Log address ranges of the requests assign write_range[ReqIdx].start_addr = axi_wide_req[i].aw.addr; - assign write_range[ReqIdx].end_addr = axi_wide_req[i].aw.addr + - ((2**axi_wide_req[i].aw.size)*(axi_wide_req[i].aw.len+1)); + assign write_range[ReqIdx].end_addr = axi_wide_req[i].aw.addr + + ((2 ** axi_wide_req[i].aw.size) * (axi_wide_req[i].aw.len + 1)); assign read_range[ReqIdx].start_addr = axi_wide_req[i].ar.addr; - assign read_range[ReqIdx].end_addr = axi_wide_req[i].ar.addr + - ((2**axi_wide_req[i].ar.size)*(axi_wide_req[i].ar.len+1)); + assign read_range[ReqIdx].end_addr = axi_wide_req[i].ar.addr + + ((2 ** axi_wide_req[i].ar.size) * (axi_wide_req[i].ar.len + 1)); assign aw_hs[ReqIdx] = filtered_wide_req[i].aw_valid && axi_wide_rsp[i].aw_ready; assign ar_hs[ReqIdx] = filtered_wide_req[i].ar_valid && axi_wide_rsp[i].ar_ready; @@ -456,19 +456,16 @@ module axi_memory_island_tb #( for (int txIdx = 0; txIdx < TxInFlight; txIdx++) begin : gen_overlap_check_txns // Block write if overlapping region is already being written write_overlapping_write[ReqIdx][requestIdx][axiIdx][txIdx] = - txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(write_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx]) : - '0; + txIdx < write_len[requestIdx][axiIdx] ? check_overlap( + write_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; // Block reads if overlapping region is already being written - read_overlapping_write[ReqIdx][requestIdx][axiIdx][txIdx] = - txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(read_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx]) : - '0; + read_overlapping_write[ReqIdx][requestIdx][axiIdx][txIdx] = + txIdx < write_len[requestIdx][axiIdx] ? check_overlap( + read_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; // Block write if overlapping region is already being read - write_overlapping_read[ReqIdx][requestIdx][axiIdx][txIdx] = - txIdx < read_len[requestIdx][axiIdx] ? - check_overlap(write_range[ReqIdx], regions_being_read[requestIdx][axiIdx][txIdx]) : - '0; + write_overlapping_read[ReqIdx][requestIdx][axiIdx][txIdx] = + txIdx < read_len[requestIdx][axiIdx] ? check_overlap( + write_range[ReqIdx], regions_being_read[requestIdx][axiIdx][txIdx]) : '0; end end live_write_overlapping_write[ReqIdx][requestIdx] = @@ -498,8 +495,8 @@ module axi_memory_island_tb #( // check other ports for (int j = 0; j < ReqIdx; j++) begin // Block write if overlapping region is starting to be written by lower ID - if ( (live_write_overlapping_write[ReqIdx][j] && aw_hs[j]) || - (live_write_overlapping_read [ReqIdx][j] && ar_hs[j]) ) begin + if ((live_write_overlapping_write[ReqIdx][j] && aw_hs[j]) || + (live_write_overlapping_read[ReqIdx][j] && ar_hs[j])) begin filtered_wide_req[i].aw_valid = 1'b0; axi_wide_rsp[i].aw_ready = 1'b0; blocking_write[ReqIdx] = 1'b1; @@ -609,10 +606,11 @@ module axi_memory_island_tb #( .SpillRspBank (0), .WidePriorityWait(3), - .NumWideBanks (NumWideBanks), - .NarrowExtraBF(NarrowExtraBF), - .WordsPerBank (WordsPerBank), - .MemorySimInit("zeros") + .NumWideBanks (NumWideBanks), + .NarrowExtraBF (NarrowExtraBF), + .WordsPerBank (WordsPerBank), + .MemorySimInit ("zeros"), + .BankAccessLatency(BankAccessLatency) ) i_dut ( .clk_i (clk), .rst_ni (rst_n),