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treewide: Add clock gate and reset registers + systemRDL generated addressmap #541

treewide: Add clock gate and reset registers + systemRDL generated addressmap

treewide: Add clock gate and reset registers + systemRDL generated addressmap #541

Workflow file for this run

# Copyright 2025 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
# Author: Tim Fischer <fischeti@iis.ee.ethz.ch>
name: lint
on:
pull_request:
push:
branches:
- main
jobs:
################
# Verible Lint #
################
verible-lint:
name: Lint SV sources
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
- uses: chipsalliance/verible-linter-action@main
with:
paths: |
./hw
./target/sim/src
github_token: ${{ secrets.GITHUB_TOKEN }}
fail_on_error: true
reviewdog_reporter: github-check
##################
# Verible Format #
##################
lint-sv-format:
name: Format SV sources
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
with:
ref: ${{ github.event.pull_request.head.sha }}
- uses: chipsalliance/verible-formatter-action@main
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
parameters:
--flagfile .verilog_format
fail_on_formatting_suggestions: true
#################
# Check License #
#################
lint-license:
name: Lint License Headers
runs-on: ubuntu-latest
steps:
- name: lint license
uses: pulp-platform/pulp-actions/lint-license@v2
with:
license: |
Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors).
(Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details.
SPDX-License-Identifier: (SHL-0.51|Apache-2.0)