tb_channel_allocator: Fix port assignment (#24)

Author: niwis

test/tb_channel_allocator.sv

@@ -309,32 +309,32 @@ module tb_channel_allocator;
   slink_ch_alloc #(
     .NumChannels ( ChannelCount )
   ) i_channel_allocator (
-    .clk_i                     ( clk                          ),
-    .rst_ni                    ( rstn                         ),
-    .cfg_tx_clear_i            ( cfg_tx_clear                 ),
-    .cfg_rx_clear_i            ( cfg_rx_clear                 ),
-    .cfg_tx_channel_en_i       ( cfg_tx_channel_en            ),
-    .cfg_tx_bypass_en_i        ( cfg_tx_bypass_en             ),
-    .cfg_tx_auto_flush_en_i    ( cfg_tx_auto_flush_en         ),
-    .cfg_tx_flush_trigger_i    ( cfg_tx_flush_trigger         ),
-    .cfg_tx_auto_flush_count_i ( cfg_tx_auto_flush_count      ),
-    .cfg_rx_channel_en_i       ( cfg_rx_channel_en            ),
-    .cfg_rx_auto_flush_en_i    ( cfg_rx_auto_flush_en         ),
-    .cfg_rx_auto_flush_count_i ( cfg_rx_auto_flush_count      ),
-    .cfg_rx_bypass_en_i        ( cfg_rx_bypass_en             ),
-    .cfg_rx_sync_en_i          ( cfg_rx_sync_en               ),
-    .data_out_i                ( source_bus.data              ),
-    .data_out_valid_i          ( source_bus_valid             ),
-    .data_out_ready_o          ( source_bus.ready             ),
-    .data_out_o                ( s_data_out_alloc2spill_data  ),
-    .data_out_valid_o          ( s_data_out_alloc2spill_valid ),
-    .data_out_ready_i          ( s_data_out_spill2alloc_ready ),
-    .data_in_o                 ( sink_bus.data                ),
-    .data_in_valid_o           ( sink_bus_valid               ),
-    .data_in_ready_i           ( '{default: sink_bus.ready}   ),
-    .data_in_i                 ( s_data_in                    ),
-    .data_in_valid_i           ( s_data_in_valid              ),
-    .data_in_ready_o           ( s_data_in_ready              )
+    .clk_i                     ( clk                            ),
+    .rst_ni                    ( rstn                           ),
+    .cfg_tx_clear_i            ( cfg_tx_clear                   ),
+    .cfg_rx_clear_i            ( cfg_rx_clear                   ),
+    .cfg_tx_channel_en_i       ( cfg_tx_channel_en              ),
+    .cfg_tx_bypass_en_i        ( cfg_tx_bypass_en               ),
+    .cfg_tx_auto_flush_en_i    ( cfg_tx_auto_flush_en           ),
+    .cfg_tx_flush_trigger_i    ( cfg_tx_flush_trigger           ),
+    .cfg_tx_auto_flush_count_i ( cfg_tx_auto_flush_count        ),
+    .cfg_rx_channel_en_i       ( cfg_rx_channel_en              ),
+    .cfg_rx_auto_flush_en_i    ( cfg_rx_auto_flush_en           ),
+    .cfg_rx_auto_flush_count_i ( cfg_rx_auto_flush_count        ),
+    .cfg_rx_bypass_en_i        ( cfg_rx_bypass_en               ),
+    .cfg_rx_sync_en_i          ( cfg_rx_sync_en                 ),
+    .data_out_i                ( source_bus.data                ),
+    .data_out_valid_i          ( source_bus_valid               ),
+    .data_out_ready_o          ( source_bus.ready               ),
+    .data_out_o                ( s_data_out_alloc2spill_data    ),
+    .data_out_valid_o          ( s_data_out_alloc2spill_valid   ),
+    .data_out_ready_i          ( s_data_out_spill2alloc_ready   ),
+    .data_in_o                 ( sink_bus.data                  ),
+    .data_in_valid_o           ( sink_bus_valid                 ),
+    .data_in_ready_i           ( {ChannelCount{sink_bus.ready}} ),
+    .data_in_i                 ( s_data_in                      ),
+    .data_in_valid_i           ( s_data_in_valid                ),
+    .data_in_ready_o           ( s_data_in_ready                )
   );
 
   // Instantiate feedback through randomized delay modules